Lines Matching +full:stm32 +full:- +full:dsi
1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
9 #include <linux/clk-provider.h>
17 #include <linux/reset-controller.h>
21 #include <dt-bindings/clock/stm32mp1-clks.h>
23 #include "reset-stm32.h"
171 "ck_hse", "pll4_r", "clk-hse-div2"
384 /* STM32 Composite clock */
397 struct gate_cfg *gate_cfg = cfg->cfg; in _clk_hw_register_gate()
400 cfg->name, in _clk_hw_register_gate()
401 cfg->parent_name, in _clk_hw_register_gate()
402 cfg->flags, in _clk_hw_register_gate()
403 gate_cfg->reg_off + base, in _clk_hw_register_gate()
404 gate_cfg->bit_idx, in _clk_hw_register_gate()
405 gate_cfg->gate_flags, in _clk_hw_register_gate()
415 struct fixed_factor_cfg *ff_cfg = cfg->cfg; in _clk_hw_register_fixed_factor()
417 return clk_hw_register_fixed_factor(dev, cfg->name, cfg->parent_name, in _clk_hw_register_fixed_factor()
418 cfg->flags, ff_cfg->mult, in _clk_hw_register_fixed_factor()
419 ff_cfg->div); in _clk_hw_register_fixed_factor()
428 struct div_cfg *div_cfg = cfg->cfg; in _clk_hw_register_divider_table()
431 cfg->name, in _clk_hw_register_divider_table()
432 cfg->parent_name, in _clk_hw_register_divider_table()
433 cfg->flags, in _clk_hw_register_divider_table()
434 div_cfg->reg_off + base, in _clk_hw_register_divider_table()
435 div_cfg->shift, in _clk_hw_register_divider_table()
436 div_cfg->width, in _clk_hw_register_divider_table()
437 div_cfg->div_flags, in _clk_hw_register_divider_table()
438 div_cfg->table, in _clk_hw_register_divider_table()
448 struct mux_cfg *mux_cfg = cfg->cfg; in _clk_hw_register_mux()
450 return clk_hw_register_mux(dev, cfg->name, cfg->parent_names, in _clk_hw_register_mux()
451 cfg->num_parents, cfg->flags, in _clk_hw_register_mux()
452 mux_cfg->reg_off + base, mux_cfg->shift, in _clk_hw_register_mux()
453 mux_cfg->width, mux_cfg->mux_flags, lock); in _clk_hw_register_mux()
472 spin_lock_irqsave(gate->lock, flags); in mp1_gate_clk_disable()
473 writel_relaxed(BIT(gate->bit_idx), gate->reg + RCC_CLR); in mp1_gate_clk_disable()
474 spin_unlock_irqrestore(gate->lock, flags); in mp1_gate_clk_disable()
492 if (cfg->mmux) { in _get_stm32_mux()
495 return ERR_PTR(-ENOMEM); in _get_stm32_mux()
497 mmux->mux.reg = cfg->mux->reg_off + base; in _get_stm32_mux()
498 mmux->mux.shift = cfg->mux->shift; in _get_stm32_mux()
499 mmux->mux.mask = (1 << cfg->mux->width) - 1; in _get_stm32_mux()
500 mmux->mux.flags = cfg->mux->mux_flags; in _get_stm32_mux()
501 mmux->mux.table = cfg->mux->table; in _get_stm32_mux()
502 mmux->mux.lock = lock; in _get_stm32_mux()
503 mmux->mmux = cfg->mmux; in _get_stm32_mux()
504 mux_hw = &mmux->mux.hw; in _get_stm32_mux()
505 cfg->mmux->hws[cfg->mmux->nbr_clk++] = mux_hw; in _get_stm32_mux()
510 return ERR_PTR(-ENOMEM); in _get_stm32_mux()
512 mux->reg = cfg->mux->reg_off + base; in _get_stm32_mux()
513 mux->shift = cfg->mux->shift; in _get_stm32_mux()
514 mux->mask = (1 << cfg->mux->width) - 1; in _get_stm32_mux()
515 mux->flags = cfg->mux->mux_flags; in _get_stm32_mux()
516 mux->table = cfg->mux->table; in _get_stm32_mux()
517 mux->lock = lock; in _get_stm32_mux()
518 mux_hw = &mux->hw; in _get_stm32_mux()
533 return ERR_PTR(-ENOMEM); in _get_stm32_div()
535 div->reg = cfg->div->reg_off + base; in _get_stm32_div()
536 div->shift = cfg->div->shift; in _get_stm32_div()
537 div->width = cfg->div->width; in _get_stm32_div()
538 div->flags = cfg->div->div_flags; in _get_stm32_div()
539 div->table = cfg->div->table; in _get_stm32_div()
540 div->lock = lock; in _get_stm32_div()
542 return &div->hw; in _get_stm32_div()
553 if (cfg->mgate) { in _get_stm32_gate()
556 return ERR_PTR(-ENOMEM); in _get_stm32_gate()
558 mgate->gate.reg = cfg->gate->reg_off + base; in _get_stm32_gate()
559 mgate->gate.bit_idx = cfg->gate->bit_idx; in _get_stm32_gate()
560 mgate->gate.flags = cfg->gate->gate_flags; in _get_stm32_gate()
561 mgate->gate.lock = lock; in _get_stm32_gate()
562 mgate->mask = BIT(cfg->mgate->nbr_clk++); in _get_stm32_gate()
564 mgate->mgate = cfg->mgate; in _get_stm32_gate()
566 gate_hw = &mgate->gate.hw; in _get_stm32_gate()
571 return ERR_PTR(-ENOMEM); in _get_stm32_gate()
573 gate->reg = cfg->gate->reg_off + base; in _get_stm32_gate()
574 gate->bit_idx = cfg->gate->bit_idx; in _get_stm32_gate()
575 gate->flags = cfg->gate->gate_flags; in _get_stm32_gate()
576 gate->lock = lock; in _get_stm32_gate()
578 gate_hw = &gate->hw; in _get_stm32_gate()
608 if (cfg->ops) in clk_stm32_register_gate_ops()
609 init.ops = cfg->ops; in clk_stm32_register_gate_ops()
613 return ERR_PTR(-ENOMEM); in clk_stm32_register_gate_ops()
615 hw->init = &init; in clk_stm32_register_gate_ops()
642 if (cfg->mux) { in clk_stm32_register_composite()
643 mux_hw = _get_stm32_mux(dev, base, cfg->mux, lock); in clk_stm32_register_composite()
648 if (cfg->mux->ops) in clk_stm32_register_composite()
649 mux_ops = cfg->mux->ops; in clk_stm32_register_composite()
653 if (cfg->div) { in clk_stm32_register_composite()
654 div_hw = _get_stm32_div(dev, base, cfg->div, lock); in clk_stm32_register_composite()
659 if (cfg->div->ops) in clk_stm32_register_composite()
660 div_ops = cfg->div->ops; in clk_stm32_register_composite()
664 if (cfg->gate) { in clk_stm32_register_composite()
665 gate_hw = _get_stm32_gate(dev, base, cfg->gate, lock); in clk_stm32_register_composite()
670 if (cfg->gate->ops) in clk_stm32_register_composite()
671 gate_ops = cfg->gate->ops; in clk_stm32_register_composite()
687 clk_mgate->mgate->flag |= clk_mgate->mask; in mp1_mgate_clk_enable()
699 clk_mgate->mgate->flag &= ~clk_mgate->mask; in mp1_mgate_clk_disable()
701 if (clk_mgate->mgate->flag == 0) in mp1_mgate_clk_disable()
732 for (n = 0; n < clk_mmux->mmux->nbr_clk; n++) in clk_mmux_set_parent()
733 if (clk_mmux->mmux->hws[n] != hw) in clk_mmux_set_parent()
734 clk_hw_reparent(clk_mmux->mmux->hws[n], hwp); in clk_mmux_set_parent()
745 /* STM32 PLL */
773 return readl_relaxed(clk_elem->reg) & PLL_ON; in __pll_is_enabled()
786 spin_lock_irqsave(clk_elem->lock, flags); in pll_enable()
791 reg = readl_relaxed(clk_elem->reg); in pll_enable()
793 writel_relaxed(reg, clk_elem->reg); in pll_enable()
801 bit_status = !(readl_relaxed(clk_elem->reg) & PLL_RDY); in pll_enable()
806 } while (bit_status && --timeout); in pll_enable()
809 spin_unlock_irqrestore(clk_elem->lock, flags); in pll_enable()
820 spin_lock_irqsave(clk_elem->lock, flags); in pll_disable()
822 reg = readl_relaxed(clk_elem->reg); in pll_disable()
824 writel_relaxed(reg, clk_elem->reg); in pll_disable()
826 spin_unlock_irqrestore(clk_elem->lock, flags); in pll_disable()
834 reg = readl_relaxed(clk_elem->reg + FRAC_OFFSET); in pll_frac_val()
849 reg = readl_relaxed(clk_elem->reg + 4); in pll_recalc_rate()
872 spin_lock_irqsave(clk_elem->lock, flags); in pll_is_enabled()
874 spin_unlock_irqrestore(clk_elem->lock, flags); in pll_is_enabled()
882 struct clk_hw *mux_hw = &clk_elem->mux.hw; in pll_get_parent()
912 return ERR_PTR(-ENOMEM); in clk_register_pll()
920 element->mux.lock = lock; in clk_register_pll()
921 element->mux.reg = mux_reg; in clk_register_pll()
922 element->mux.shift = PLL_MUX_SHIFT; in clk_register_pll()
923 element->mux.mask = PLL_MUX_MASK; in clk_register_pll()
924 element->mux.flags = CLK_MUX_READ_ONLY; in clk_register_pll()
925 element->mux.reg = mux_reg; in clk_register_pll()
927 element->hw.init = &init; in clk_register_pll()
928 element->reg = reg; in clk_register_pll()
929 element->lock = lock; in clk_register_pll()
931 hw = &element->hw; in clk_register_pll()
961 prescaler = readl_relaxed(tim_ker->apbdiv) & APB_DIV_MASK; in __bestmult()
989 spin_lock_irqsave(tim_ker->lock, flags); in timer_ker_set_rate()
995 writel_relaxed(0, tim_ker->timpre); in timer_ker_set_rate()
998 writel_relaxed(1, tim_ker->timpre); in timer_ker_set_rate()
1001 ret = -EINVAL; in timer_ker_set_rate()
1003 spin_unlock_irqrestore(tim_ker->lock, flags); in timer_ker_set_rate()
1015 prescaler = readl_relaxed(tim_ker->apbdiv) & APB_DIV_MASK; in timer_ker_recalc_rate()
1017 timpre = readl_relaxed(tim_ker->timpre) & TIM_PRE_MASK; in timer_ker_recalc_rate()
1048 return ERR_PTR(-ENOMEM); in clk_register_cktim()
1056 tim_ker->hw.init = &init; in clk_register_cktim()
1057 tim_ker->lock = lock; in clk_register_cktim()
1058 tim_ker->apbdiv = apbdiv; in clk_register_cktim()
1059 tim_ker->timpre = timpre; in clk_register_cktim()
1061 hw = &tim_ker->hw; in clk_register_cktim()
1093 if (req->best_parent_hw == clk_hw_get_parent_by_index(hw, HSE_RTC)) in clk_divider_rtc_determine_rate()
1096 req->rate = req->best_parent_rate; in clk_divider_rtc_determine_rate()
1117 struct stm32_pll_cfg *stm_pll_cfg = cfg->cfg; in _clk_register_pll()
1119 return clk_register_pll(dev, cfg->name, cfg->parent_names, in _clk_register_pll()
1120 cfg->num_parents, in _clk_register_pll()
1121 base + stm_pll_cfg->offset, in _clk_register_pll()
1122 base + stm_pll_cfg->muxoff, in _clk_register_pll()
1123 cfg->flags, lock); in _clk_register_pll()
1136 struct stm32_cktim_cfg *cktim_cfg = cfg->cfg; in _clk_register_cktim()
1138 return clk_register_cktim(dev, cfg->name, cfg->parent_name, cfg->flags, in _clk_register_cktim()
1139 cktim_cfg->offset_apbdiv + base, in _clk_register_cktim()
1140 cktim_cfg->offset_timpre + base, lock); in _clk_register_cktim()
1150 cfg->name, in _clk_stm32_register_gate()
1151 cfg->parent_name, in _clk_stm32_register_gate()
1152 cfg->parent_data, in _clk_stm32_register_gate()
1153 cfg->flags, in _clk_stm32_register_gate()
1155 cfg->cfg, in _clk_stm32_register_gate()
1165 return clk_stm32_register_composite(dev, cfg->name, cfg->parent_names, in _clk_stm32_register_composite()
1166 cfg->parent_data, cfg->num_parents, in _clk_stm32_register_composite()
1167 base, cfg->cfg, cfg->flags, lock); in _clk_stm32_register_composite()
1265 /* STM32 GATE */
1762 GATE_MP1(CK_HSE, "ck_hse", "clk-hse", 0, RCC_OCENSETR, 8, 0),
1764 GATE_MP1(CK_CSI, "ck_csi", "clk-csi", CLK_IS_CRITICAL,
1766 COMPOSITE(CK_HSI, "ck_hsi", PARENT("clk-hsi"), 0,
1771 GATE(CK_LSI, "ck_lsi", "clk-lsi", 0, RCC_RDLSICR, 0, 0),
1772 GATE(CK_LSE, "ck_lse", "clk-lse", 0, RCC_BDCR, 0, 0),
1774 FIXED_FACTOR(CK_HSE_DIV2, "clk-hse-div2", "ck_hse", 0, 1, 2),
1938 PCLK(DSI, "dsi", "pclk4", 0, G_DSI),
2135 if (cfg->id == stm32mp1_clock_secured[i]) in stm32_check_security()
2170 .compatible = "st,stm32mp1-rcc",
2174 .compatible = "st,stm32mp1-rcc-secure",
2187 struct clk_hw *hw = ERR_PTR(-ENOENT); in stm32_register_hw_clk()
2189 hws = clk_data->hws; in stm32_register_hw_clk()
2191 if (cfg->func) in stm32_register_hw_clk()
2192 hw = (*cfg->func)(dev, clk_data, base, lock, cfg); in stm32_register_hw_clk()
2195 pr_err("Unable to register %s\n", cfg->name); in stm32_register_hw_clk()
2199 if (cfg->id != NO_ID) in stm32_register_hw_clk()
2200 hws[cfg->id] = hw; in stm32_register_hw_clk()
2208 const struct stm32_rcc_match_data *data = match->data; in stm32_rcc_clock_init()
2213 max_binding = data->maxbinding; in stm32_rcc_clock_init()
2218 return -ENOMEM; in stm32_rcc_clock_init()
2220 clk_data->num = max_binding; in stm32_rcc_clock_init()
2222 hws = clk_data->hws; in stm32_rcc_clock_init()
2225 hws[n] = ERR_PTR(-ENOENT); in stm32_rcc_clock_init()
2227 for (n = 0; n < data->num; n++) { in stm32_rcc_clock_init()
2228 if (data->check_security && data->check_security(&data->cfg[n])) in stm32_rcc_clock_init()
2232 &data->cfg[n]); in stm32_rcc_clock_init()
2235 data->cfg[n].name, err); in stm32_rcc_clock_init()
2254 return -ENODEV; in stm32_rcc_init()
2257 rcc_match_data = match->data; in stm32_rcc_init()
2260 err = stm32_rcc_reset_init(dev, rcc_match_data->reset_data, base); in stm32_rcc_init()
2284 ret = -ENOMEM; in stm32mp1_rcc_init()
2312 return -ENOMEM; in get_clock_deps()
2319 if (PTR_ERR(clk) != -EINVAL && PTR_ERR(clk) != -ENOENT) in get_clock_deps()
2333 struct device *dev = &pdev->dev; in stm32mp1_rcc_clocks_probe()
2344 struct device *dev = &pdev->dev; in stm32mp1_rcc_clocks_remove()