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Searched +full:stih407 +full:- +full:sbc +full:- +full:syscfg (Results 1 – 7 of 7) sorted by relevance

/linux/Documentation/devicetree/bindings/soc/sti/
H A Dst,sti-syscon.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/sti/st,sti-syscon.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Patrice Chotard <patrice.chotard@foss.st.com>
14 platform device-tree to point to some common configuration
20 - enum:
21 - st,stih407-core-syscfg
22 - st,stih407-flash-syscfg
23 - st,stih407-front-syscfg
[all …]
/linux/arch/arm/boot/dts/st/
H A Dstih407-family.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 #include "stih407-pinctrl.dtsi"
7 #include <dt-bindings/mfd/st-lpc.h>
8 #include <dt-bindings/phy/phy.h>
9 #include <dt-bindings/reset/stih407-resets.h>
10 #include <dt-bindings/interrupt-controller/irq-st.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
15 reserved-memory {
16 #address-cells = <1>;
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H A Dstih418.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 #include "stih418-clock.dtsi"
7 #include "stih407-family.dtsi"
8 #include "stih410-pinctrl.dtsi"
9 #include <dt-bindings/thermal/thermal.h>
12 #address-cells = <1>;
13 #size-cells = <0>;
16 compatible = "arm,cortex-a9";
18 /* u-boot puts hpen in SBC dmem at 0xa4 offset */
19 cpu-release-addr = <0x94100A4>;
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H A Dstih407-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 #include "st-pincfg.h"
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 /* 0-5: PIO_SBC */
18 /* 10-19: PIO_FRONT0 */
31 /* 30-35: PIO_REAR */
38 /* 40-42: PIO_FLASH */
45 pin-controller-sbc@961f080 {
46 #address-cells = <1>;
47 #size-cells = <1>;
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/linux/drivers/reset/sti/
H A Dreset-stih407.c1 // SPDX-License-Identifier: GPL-2.0-or-later
10 #include <dt-bindings/reset/stih407-resets.h>
11 #include "reset-syscfg.h"
13 /* STiH407 Peripheral powerdown definitions. */
14 static const char stih407_core[] = "st,stih407-core-syscfg";
15 static const char stih407_sbc_reg[] = "st,stih407-sbc-reg-syscfg";
16 static const char stih407_lpm[] = "st,stih407-lpm-syscfg";
55 #define LPM_SYSCFG_1 0x4 /* Softreset IRB & SBC UART */
132 .compatible = "st,stih407-powerdown",
136 .compatible = "st,stih407-softreset",
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/linux/Documentation/devicetree/bindings/pinctrl/
H A Dpinctrl-st.txt3 Each multi-function pin is controlled, driven and routed through the
5 and multiple alternate functions(ALT1 - ALTx) that directly connect
14 GPIO bank can have one of the two possible types of interrupt-wirings.
20 | |----> [gpio-bank (n) ]
21 | |----> [gpio-bank (n + 1)]
22 [irqN]-- | irq-mux |----> [gpio-bank (n + 2)]
23 | |----> [gpio-bank (... )]
24 |_________|----> [gpio-bank (n + 7)]
28 [irqN]----> [gpio-bank (n)]
33 - compatible : should be "st,stih407-<pio-block>-pinctrl"
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/linux/drivers/pinctrl/
H A Dpinctrl-st.c1 // SPDX-License-Identifier: GPL-2.0-only
100 * (direction, retime-type, retime-clk, retime-delay)
102 * +----------------+
103 *[31:28]| reserved-3 |
104 * +----------------+-------------
106 * +----------------+ v
108 * +----------------+ ^
110 * +----------------+-------------
111 *[24] | reserved-2 |
112 * +----------------+-------------
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