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/linux/Documentation/devicetree/bindings/watchdog/
H A Dstarfive,jh7100-wdt.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/watchdog/starfive,jh7100-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: StarFive Watchdog for JH7100 and JH7110 SoC
10 - Xingyu Wu <xingyu.wu@starfivetech.com>
11 - Samin Guo <samin.guo@starfivetech.com>
14 The JH7100 and JH7110 watchdog both are 32 bit counters. JH7100 watchdog
25 - enum:
26 - starfive,jh7100-wdt
[all …]
/linux/drivers/clk/starfive/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
7 bool "StarFive JH7100 clock support"
12 Say yes here to support the clock controller on the StarFive JH7100
16 tristate "StarFive JH7100 audio clock support"
21 Say Y or M here to support the audio clocks on the StarFive JH7100
25 bool "StarFive JH7110 PLL clock support"
30 StarFive JH7110 SoC.
33 bool "StarFive JH7110 system clock support"
42 StarFive JH7110 SoC.
45 tristate "StarFive JH7110 always-on clock support"
[all …]
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_CLK_STARFIVE_JH71X0) += clk-starfive-jh71x0.o
4 obj-$(CONFIG_CLK_STARFIVE_JH7100) += clk-starfive-jh7100.o
5 obj-$(CONFIG_CLK_STARFIVE_JH7100_AUDIO) += clk-starfive-jh7100-audio.o
7 obj-$(CONFIG_CLK_STARFIVE_JH7110_PLL) += clk-starfive-jh7110-pll.o
8 obj-$(CONFIG_CLK_STARFIVE_JH7110_SYS) += clk-starfive-jh7110-sys.o
9 obj-$(CONFIG_CLK_STARFIVE_JH7110_AON) += clk-starfive-jh7110-aon.o
10 obj-$(CONFIG_CLK_STARFIVE_JH7110_STG) += clk-starfive-jh7110-stg.o
11 obj-$(CONFIG_CLK_STARFIVE_JH7110_ISP) += clk-starfive-jh7110-isp.o
12 obj-$(CONFIG_CLK_STARFIVE_JH7110_VOUT) += clk-starfive-jh7110-vout.o
H A Dclk-starfive-jh7100-audio.c1 // SPDX-License-Identifier: GPL-2.0
3 * StarFive JH7100 Audio Clock Driver
9 #include <linux/clk-provider.h>
16 #include <dt-bindings/clock/starfive-jh7100-audio.h>
18 #include "clk-starfive-jh71x0.h"
90 unsigned int idx = clkspec->args[0]; in jh7100_audclk_get()
93 return &priv->reg[idx].hw; in jh7100_audclk_get()
95 return ERR_PTR(-EINVAL); in jh7100_audclk_get()
104 priv = devm_kzalloc(&pdev->dev, struct_size(priv, reg, JH7100_AUDCLK_END), GFP_KERNEL); in jh7100_audclk_probe()
106 return -ENOMEM; in jh7100_audclk_probe()
[all …]
H A Dclk-starfive-jh7100.c1 // SPDX-License-Identifier: GPL-2.0
3 * StarFive JH7100 Clock Generator Driver
10 #include <linux/clk-provider.h>
16 #include <dt-bindings/clock/starfive-jh7100.h>
18 #include "clk-starfive-jh71x0.h"
273 unsigned int idx = clkspec->args[0]; in jh7100_clk_get()
276 return &priv->reg[idx].hw; in jh7100_clk_get()
279 return priv->pll[idx - JH7100_CLK_PLL0_OUT]; in jh7100_clk_get()
281 return ERR_PTR(-EINVAL); in jh7100_clk_get()
290 priv = devm_kzalloc(&pdev->dev, struct_size(priv, reg, JH7100_CLK_PLL0_OUT), GFP_KERNEL); in clk_starfive_jh7100_probe()
[all …]
/linux/Documentation/devicetree/bindings/clock/
H A Dstarfive,jh7100-audclk.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/starfive,jh7100-audclk.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: StarFive JH7100 Audio Clock Generator
10 - Emil Renner Berthing <kernel@esmil.dk>
14 const: starfive,jh7100-audclk
21 - description: Audio source clock
22 - description: External 12.288MHz clock
23 - description: Domain 7 AHB bus clock
[all …]
H A Dstarfive,jh7100-clkgen.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/starfive,jh7100-clkgen.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: StarFive JH7100 Clock Generator
10 - Geert Uytterhoeven <geert@linux-m68k.org>
11 - Emil Renner Berthing <kernel@esmil.dk>
15 const: starfive,jh7100-clkgen
22 - description: Main clock source (25 MHz)
23 - description: Application-specific clock source (12-27 MHz)
[all …]
/linux/Documentation/devicetree/bindings/hwmon/
H A Dstarfive,jh71x0-temp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/hwmon/starfive,jh71x0-temp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: StarFive JH71x0 Temperature Sensor
10 - Emil Renner Berthing <kernel@esmil.dk>
13 StarFive Technology Co. JH71x0 embedded temperature sensor
18 - starfive,jh7100-temp
19 - starfive,jh7110-temp
28 clock-names:
[all …]
/linux/Documentation/devicetree/bindings/reset/
H A Dstarfive,jh7100-reset.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/reset/starfive,jh7100-reset.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: StarFive JH7100 SoC Reset Controller
10 - Emil Renner Berthing <kernel@esmil.dk>
15 - starfive,jh7100-reset
20 "#reset-cells":
24 - compatible
25 - reg
[all …]
/linux/Documentation/devicetree/bindings/pinctrl/
H A Dstarfive,jh7100-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/starfive,jh7100-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: StarFive JH7100 Pin Controller
10 Bindings for the JH7100 RISC-V SoC from StarFive Ltd.
15 interesting 2-layered approach to pin muxing best illustrated by the diagram
21 LCD output -----------------| |
22 CMOS Camera interface ------| |--- PAD_GPIO[0]
23 Ethernet PHY interface -----| MUX |--- PAD_GPIO[1]
[all …]
/linux/drivers/reset/starfive/
H A Dreset-starfive-jh7100.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Reset driver for the StarFive JH7100 SoC
11 #include "reset-starfive-jh71x0.h"
13 #include <dt-bindings/reset/starfive-jh7100.h>
54 return reset_starfive_jh71x0_register(&pdev->dev, pdev->dev.of_node, in jh7100_reset_probe()
63 { .compatible = "starfive,jh7100-reset" },
69 .name = "jh7100-reset",
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
7 bool "StarFive JH7100 Reset Driver"
12 This enables the reset controller driver for the StarFive JH7100 SoC.
15 bool "StarFive JH7110 Reset Driver"
21 This enables the reset controller driver for the StarFive JH7110 SoC.
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_RESET_STARFIVE_JH71X0) += reset-starfive-jh71x0.o
4 obj-$(CONFIG_RESET_STARFIVE_JH7100) += reset-starfive-jh7100.o
5 obj-$(CONFIG_RESET_STARFIVE_JH7110) += reset-starfive-jh7110.o
/linux/Documentation/devicetree/bindings/net/
H A Dstarfive,jh7110-dwmac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2022 StarFive Technology Co., Ltd.
4 ---
5 $id: http://devicetree.org/schemas/net/starfive,jh7110-dwmac.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: StarFive JH7110 DWMAC glue layer
11 - Emil Renner Berthing <kernel@esmil.dk>
12 - Samin Guo <samin.guo@starfivetech.com>
19 - starfive,jh7100-dwmac
20 - starfive,jh7110-dwmac
[all …]
/linux/drivers/pinctrl/starfive/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
4 tristate "Pinctrl and GPIO driver for the StarFive JH7100 SoC"
15 Say yes here to support pin control on the StarFive JH7100 SoC.
17 peripherals supporting inputs, outputs, configuring pull-up/pull-down
30 tristate "System pinctrl and GPIO driver for the StarFive JH7110 SoC"
36 Say yes here to support system pin control on the StarFive JH7110 SoC.
38 peripherals supporting inputs, outputs, configuring pull-up/pull-down
42 tristate "Always-on pinctrl and GPIO driver for the StarFive JH7110 SoC"
48 Say yes here to support always-on pin control on the StarFive JH7110 SoC.
50 peripherals supporting inputs, outputs, configuring pull-up/pull-down
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
3 obj-$(CONFIG_PINCTRL_STARFIVE_JH7100) += pinctrl-starfive-jh7100.o
5 obj-$(CONFIG_PINCTRL_STARFIVE_JH7110) += pinctrl-starfive-jh7110.o
6 obj-$(CONFIG_PINCTRL_STARFIVE_JH7110_SYS) += pinctrl-starfive-jh7110-sys.o
7 obj-$(CONFIG_PINCTRL_STARFIVE_JH7110_AON) += pinctrl-starfive-jh7110-aon.o
/linux/Documentation/devicetree/bindings/cache/
H A Dsifive,ccache0.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Paul Walmsley <paul.walmsley@sifive.com>
16 acts as directory-based coherency manager.
24 - sifive,ccache0
25 - sifive,fu540-c000-ccache
26 - sifive,fu740-c000-ccache
29 - compatible
34 - items:
[all …]
/linux/arch/riscv/boot/dts/starfive/
H A Djh7100-beaglev-starlight.dts1 // SPDX-License-Identifier: GPL-2.0 OR MIT
3 * Copyright (C) 2021 StarFive Technology Co., Ltd.
7 /dts-v1/;
8 #include "jh7100-common.dtsi"
12 compatible = "beagle,beaglev-starlight-jh7100-r0", "starfive,jh7100";
16 phy-handle = <&phy>;
20 phy: ethernet-phy@7 {
22 reset-gpios = <&gpio 63 GPIO_ACTIVE_LOW>;
H A Djh7100-starfive-visionfive-v1.dts1 // SPDX-License-Identifier: GPL-2.0 OR MIT
3 * Copyright (C) 2021 StarFive Technology Co., Ltd.
7 /dts-v1/;
8 #include "jh7100-common.dtsi"
11 model = "StarFive VisionFive V1";
12 compatible = "starfive,visionfive-v1", "starfive,jh7100";
14 gpio-restart {
15 compatible = "gpio-restart";
22 phy-handle = <&phy>;
26 * The board uses a Motorcomm YT8521 PHY supporting RGMII-ID, but requires
[all …]
/linux/Documentation/devicetree/bindings/timer/
H A Dsifive,clint.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Palmer Dabbelt <palmer@dabbelt.com>
11 - Anup Patel <anup.patel@wdc.com>
14 SiFive (and other RISC-V) SOCs include an implementation of the SiFive
15 Core Local Interruptor (CLINT) for M-mode timer and M-mode inter-processor
16 interrupts. It directly connects to the timer and inter-processor interrupt
17 lines of various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local
19 The clock frequency of CLINT is specified via "timebase-frequency" DT
[all …]
/linux/Documentation/hwmon/
H A Dsfctemp.rst1 .. SPDX-License-Identifier: GPL-2.0
7 - StarFive JH7100
8 - StarFive JH7110
11 - Emil Renner Berthing <kernel@esmil.dk>
14 -----------
16 This driver adds support for reading the built-in temperature sensor on the
17 JH7100 and JH7110 RISC-V SoCs by StarFive Technology Co. Ltd.
20 -------------------
32 temp1_input RO Temperature reading in milli-degrees Celsius.
/linux/arch/riscv/
H A DKconfig.errata20 non-standard handling on non-coherent operations on Andes cores.
35 bool "Apply SiFive errata CIP-453"
39 This will apply the SiFive CIP-453 errata to add sign extension
46 bool "Apply SiFive errata CIP-1200"
50 This will apply the SiFive CIP-1200 errata to repalce all
57 bool "StarFive JH7100 support"
67 The StarFive JH7100 was a test chip for the JH7110 and has
68 caches that are non-coherent with respect to peripheral DMAs.
69 It was designed before the Zicbom extension so needs non-standard
73 StarFive VisionFive V1 boards.
[all …]
/linux/Documentation/devicetree/bindings/serial/
H A Dsnps-dw-apb-uart.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/serial/snps-dw-apb-uart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
13 - $ref: serial.yaml#
14 - $ref: rs485.yaml#
16 - if:
20 const: starfive,jh7110-uart
33 - items:
[all …]
/linux/Documentation/devicetree/bindings/pwm/
H A Dopencores,pwm.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - William Qiu <william.qiu@starfivetech.com>
14 mode, the PTC core generates binary signal with user-programmable low and
15 high periods. All PTC counters and registers are 32-bit.
18 - $ref: pwm.yaml#
23 - enum:
24 - starfive,jh7100-pwm
25 - starfive,jh7110-pwm
[all …]
/linux/drivers/watchdog/
H A Dstarfive-wdt.c1 // SPDX-License-Identifier: GPL-2.0
3 * Starfive Watchdog driver
5 * Copyright (C) 2022 StarFive Technology Co., Ltd.
17 /* JH7100 Watchdog register define */
112 /* Register layout and configuration for the JH7100 */
150 ret = clk_prepare_enable(wdt->apb_clk); in starfive_wdt_enable_clock()
152 return dev_err_probe(wdt->wdd.parent, ret, "failed to enable apb clock\n"); in starfive_wdt_enable_clock()
154 ret = clk_prepare_enable(wdt->core_clk); in starfive_wdt_enable_clock()
156 clk_disable_unprepare(wdt->apb_clk); in starfive_wdt_enable_clock()
157 return dev_err_probe(wdt->wdd.parent, ret, "failed to enable core clock\n"); in starfive_wdt_enable_clock()
[all …]

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