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Searched +full:sram +full:- +full:supply (Results 1 – 25 of 44) sorted by relevance

12

/linux/drivers/gpu/drm/panthor/
H A Dpanthor_devfreq.c1 // SPDX-License-Identifier: GPL-2.0 or MIT
16 * struct panthor_devfreq - Device frequency management
52 last = pdevfreq->time_last_update; in panthor_devfreq_update_utilization()
54 if (pdevfreq->last_busy_state) in panthor_devfreq_update_utilization()
55 pdevfreq->busy_time += ktime_sub(now, last); in panthor_devfreq_update_utilization()
57 pdevfreq->idle_time += ktime_sub(now, last); in panthor_devfreq_update_utilization()
59 pdevfreq->time_last_update = now; in panthor_devfreq_update_utilization()
76 ptdev->current_frequency = *freq; in panthor_devfreq_target()
83 pdevfreq->busy_time = 0; in panthor_devfreq_reset()
84 pdevfreq->idle_time = 0; in panthor_devfreq_reset()
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/linux/Documentation/devicetree/bindings/gpu/
H A Darm,mali-valhall-csf.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/gpu/arm,mali-valhall-csf.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Liviu Dudau <liviu.dudau@arm.com>
11 - Boris Brezillon <boris.brezillon@collabora.com>
15 pattern: '^gpu@[a-f0-9]+$'
19 - items:
20 - enum:
21 - rockchip,rk3588-mali
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/linux/Documentation/devicetree/bindings/interconnect/
H A Dmediatek,cci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jia-Wei Chang <jia-wei.chang@mediatek.com>
11 - Johnson Wang <johnson.wang@mediatek.com>
21 - enum:
22 - mediatek,mt8183-cci
23 - mediatek,mt8186-cci
24 - items:
25 - enum:
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/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8365-evk.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2021-2022 BayLibre, SAS.
10 /dts-v1/;
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/input/input.h>
14 #include <dt-bindings/pinctrl/mt8365-pinfunc.h>
20 compatible = "mediatek,mt8365-evk", "mediatek,mt8365";
28 stdout-path = "serial0:921600n8";
32 compatible = "hdmi-connector";
37 #address-cells = <1>;
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H A Dmt7622-rfb1.dts6 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
9 /dts-v1/;
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/gpio/gpio.h>
18 chassis-type = "embedded";
19 compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622";
26 stdout-path = "serial0:115200n8";
32 proc-supply = <&mt6380_vcpu_reg>;
33 sram-supply = <&mt6380_vm_reg>;
37 proc-supply = <&mt6380_vcpu_reg>;
[all …]
H A Dmt7622-bananapi-bpi-r64.dts5 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 /dts-v1/;
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/leds/common.h>
17 model = "Bananapi BPI-R64";
18 chassis-type = "embedded";
19 compatible = "bananapi,bpi-r64", "mediatek,mt7622";
26 stdout-path = "serial0:115200n8";
32 proc-supply = <&mt6380_vcpu_reg>;
[all …]
H A Dmt8173-elm.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <dt-bindings/input/input.h>
7 #include <dt-bindings/input/linux-event-codes.h>
8 #include <dt-bindings/regulator/dlg,da9211-regulator.h>
9 #include <dt-bindings/gpio/gpio.h>
25 compatible = "pwm-backlight";
27 power-supply = <&bl_fixed_reg>;
28 enable-gpios = <&pio 95 GPIO_ACTIVE_HIGH>;
30 pinctrl-names = "default";
31 pinctrl-0 = <&panel_backlight_en_pins>;
[all …]
/linux/arch/arm/boot/dts/st/
H A Dste-dbx5x0.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/clock/ste-db8500-clkout.h>
9 #include <dt-bindings/reset/stericsson,db8500-prcc-reset.h>
10 #include <dt-bindings/mfd/dbx500-prcmu.h>
11 #include <dt-bindings/arm/ux500_pm_domains.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/thermal/thermal.h>
16 #address-cells = <1>;
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/linux/arch/arm64/boot/dts/rockchip/
H A Drk3588-orangepi-5.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/leds/common.h>
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/pinctrl/rockchip.h>
12 #include <dt-bindings/usb/pd.h>
22 stdout-path = "serial2:1500000n8";
25 adc-keys-0 {
26 compatible = "adc-keys";
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H A Drk3588-mnt-reform2.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/pinctrl/rockchip.h>
12 #include <dt-bindings/soc/rockchip,vop2.h>
13 #include <dt-bindings/usb/pd.h>
15 #include "rk3588-firefly-icore-3588q.dtsi"
19 compatible = "mntre,reform2-rcore", "firefly,icore-3588q", "rockchip,rk3588";
20 chassis-type = "laptop";
[all …]
H A Drk3588-friendlyelec-cm3588.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
9 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/leds/common.h>
13 #include <dt-bindings/pinctrl/rockchip.h>
26 stdout-path = "serial2:1500000n8";
30 compatible = "gpio-leds";
32 led_sys: led-0 {
36 linux,default-trigger = "heartbeat";
37 pinctrl-names = "default";
[all …]
H A Drk3588-firefly-itx-3588j.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 /dts-v1/;
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/input/input.h>
7 #include <dt-bindings/leds/common.h>
8 #include <dt-bindings/pinctrl/rockchip.h>
9 #include <dt-bindings/pwm/pwm.h>
10 #include <dt-bindings/soc/rockchip,vop2.h>
11 #include "dt-bindings/usb/pd.h"
13 #include "rk3588-firefly-core-3588j.dtsi"
[all …]
H A Drk3588-evb2-v10.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
9 #include <dt-bindings/clock/rockchip,rk3588-cru.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/pinctrl/rockchip.h>
12 #include <dt-bindings/soc/rockchip,vop2.h>
17 compatible = "rockchip,rk3588-evb2-v10", "rockchip,rk3588";
25 stdout-path = "serial2:1500000n8";
28 hdmi-con {
29 compatible = "hdmi-connector";
[all …]
/linux/arch/arm/boot/dts/samsung/
H A Dexynos4210-universal_c210.dts1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd.
12 /dts-v1/;
14 #include <dt-bindings/gpio/gpio.h>
19 chassis-type = "handset";
35 stdout-path = "serial2:115200n8";
39 fixed-rate-clocks {
41 compatible = "samsung,clock-xxti";
42 clock-frequency = <0>;
46 compatible = "samsung,clock-xusbxti";
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/linux/arch/arm/boot/dts/nspire/
H A Dnspire.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
7 #address-cells = <1>;
8 #size-cells = <1>;
9 interrupt-parent = <&intc>;
12 #address-cells = <1>;
13 #size-cells = <0>;
16 compatible = "arm,arm926ej-s";
26 sram: sram@a4000000 { label
27 compatible = "mmio-sram";
29 #address-cells = <1>;
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/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx27-phytec-phycore-som.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
6 /dts-v1/;
11 compatible = "phytec,imx27-pcm038", "fsl,imx27";
18 reg_3v3: regulator-0 {
19 compatible = "regulator-fixed";
20 regulator-name = "3V3";
21 regulator-min-microvolt = <3300000>;
22 regulator-max-microvolt = <3300000>;
25 reg_5v0: regulator-1 {
26 compatible = "regulator-fixed";
[all …]
H A Dimx6q.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 #include <dt-bindings/interrupt-controller/irq.h>
6 #include "imx6q-pinfunc.h"
16 #address-cells = <1>;
17 #size-cells = <0>;
20 compatible = "arm,cortex-a9";
23 next-level-cache = <&L2>;
24 operating-points = <
32 fsl,soc-operating-points = <
33 /* ARM kHz SOC-PU uV */
[all …]
H A Dimx6dl.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 #include <dt-bindings/interrupt-controller/irq.h>
6 #include "imx6dl-pinfunc.h"
15 #address-cells = <1>;
16 #size-cells = <0>;
19 compatible = "arm,cortex-a9";
22 next-level-cache = <&L2>;
23 operating-points = <
29 fsl,soc-operating-points = <
30 /* ARM kHz SOC-PU uV */
[all …]
H A Dimx7d-smegw01.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
13 compatible = "storopack,imx7d-smegw01", "fsl,imx7d";
26 stdout-path = &uart1;
34 reg_lte_on: regulator-lte-on {
35 compatible = "regulator-fixed";
36 pinctrl-names = "default";
37 pinctrl-0 = <&pinctrl_lte_on>;
38 regulator-min-microvolt = <3300000>;
[all …]
/linux/arch/arm/boot/dts/qcom/
H A Dqcom-apq8064-asus-nexus7-flo.dts1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/gpio/gpio.h>
3 #include <dt-bindings/input/input.h>
4 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
6 #include "qcom-apq8064-v2.0.dtsi"
12 compatible = "asus,nexus7-flo", "qcom,apq8064";
13 chassis-type = "tablet";
21 stdout-path = "serial0:115200n8";
24 reserved-memory {
25 #address-cells = <1>;
[all …]
/linux/arch/sparc/include/asm/
H A Dfhc.h1 /* SPDX-License-Identifier: GPL-2.0 */
44 #define FHC_CONTROL_DCD 0x00008000 /* DC-->DC Converter Disable */
47 #define FHC_CONTROL_AOFF 0x00001000 /* CPU A SRAM/SBD Low Power Mode */
48 #define FHC_CONTROL_BOFF 0x00000800 /* CPU B SRAM/SBD Low Power Mode */
49 #define FHC_CONTROL_PSOFF 0x00000400 /* Turns off this FHC's power supply */
/linux/Documentation/devicetree/bindings/power/
H A Drockchip-io-domain.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/power/rockchip-io-domain.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip SRAM for IO Voltage Domains
10 - Heiko Stuebner <heiko@sntech.de>
42 to report their voltage. The IO Voltage Domain for any non-specified
48 - rockchip,px30-io-voltage-domain
49 - rockchip,px30-pmu-io-voltage-domain
50 - rockchip,rk3188-io-voltage-domain
[all …]
/linux/drivers/net/wireless/intel/iwlegacy/
H A D4965.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
8 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
15 #include <linux/dma-mapping.h>
29 * il_verify_inst_sparse - verify runtime uCode image in card vs. host,
44 /* read data comes through single port, auto-incr addr */ in il4965_verify_inst_sparse()
50 ret = -EIO; in il4965_verify_inst_sparse()
61 * il4965_verify_inst_full - verify runtime uCode image in card vs. host,
77 for (; len > 0; len -= sizeof(u32), image++) { in il4965_verify_inst_full()
78 /* read data comes through single port, auto-incr addr */ in il4965_verify_inst_full()
[all …]
/linux/arch/arm/boot/dts/xilinx/
H A Dzynq-7000.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2011 - 2014 Xilinx
7 #address-cells = <1>;
8 #size-cells = <1>;
9 compatible = "xlnx,zynq-7000";
12 u-boot {
13 compatible = "u-boot,config";
14 bootscr-address = /bits/ 64 <0x3000000>;
19 #address-cells = <1>;
20 #size-cells = <0>;
[all …]
/linux/drivers/pmdomain/mediatek/
H A Dmtk-scpsys.c1 // SPDX-License-Identifier: GPL-2.0-only
16 #include <dt-bindings/power/mt2701-power.h>
17 #include <dt-bindings/power/mt2712-power.h>
18 #include <dt-bindings/power/mt6797-power.h>
19 #include <dt-bindings/power/mt7622-power.h>
20 #include <dt-bindings/power/mt7623a-power.h>
21 #include <dt-bindings/power/mt8173-power.h>
28 #define MTK_SCPD_CAPS(_scpd, _x) ((_scpd)->data->caps & (_x))
112 * struct scp_domain_data - scp domain data for power on/off flow
116 * @sram_pdn_bits: The mask for sram power control bits.
[all …]

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