xref: /linux/arch/arm64/boot/dts/mediatek/mt8365-evk.dts (revision 3a39d672e7f48b8d6b91a09afa4b55352773b4b5)

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (c) 2021-2022 BayLibre, SAS.
 * Authors:
 * Fabien Parent <fparent@baylibre.com>
 * Bernhard Rosenkränzer <bero@baylibre.com>
 * Alexandre Mergnat <amergnat@baylibre.com>
 */

/dts-v1/;

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/pinctrl/mt8365-pinfunc.h>
#include "mt8365.dtsi"
#include "mt6357.dtsi"

/ {
	model = "MediaTek MT8365 Open Platform EVK";
	compatible = "mediatek,mt8365-evk", "mediatek,mt8365";

	aliases {
		serial0 = &uart0;
	};

	chosen {
		stdout-path = "serial0:921600n8";
	};

	firmware {
		optee {
			compatible = "linaro,optee-tz";
			method = "smc";
		};
	};

	gpio-keys {
		compatible = "gpio-keys";
		pinctrl-names = "default";
		pinctrl-0 = <&gpio_keys>;

		key-volume-up {
			gpios = <&pio 24 GPIO_ACTIVE_LOW>;
			label = "volume_up";
			linux,code = <KEY_VOLUMEUP>;
			wakeup-source;
			debounce-interval = <15>;
		};
	};

	memory@40000000 {
		device_type = "memory";
		reg = <0 0x40000000 0 0xc0000000>;
	};

	usb_otg_vbus: regulator-0 {
		compatible = "regulator-fixed";
		regulator-name = "otg_vbus";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		gpio = <&pio 16 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		/* 192 KiB reserved for ARM Trusted Firmware (BL31) */
		bl31_secmon_reserved: secmon@43000000 {
			no-map;
			reg = <0 0x43000000 0 0x30000>;
		};

		/* 12 MiB reserved for OP-TEE (BL32)
		 * +-----------------------+ 0x43e0_0000
		 * |      SHMEM 2MiB       |
		 * +-----------------------+ 0x43c0_0000
		 * |        | TA_RAM  8MiB |
		 * + TZDRAM +--------------+ 0x4340_0000
		 * |        | TEE_RAM 2MiB |
		 * +-----------------------+ 0x4320_0000
		 */
		optee_reserved: optee@43200000 {
			no-map;
			reg = <0 0x43200000 0 0x00c00000>;
		};
	};

	sound: sound {
		compatible = "mediatek,mt8365-mt6357";
		pinctrl-names = "default",
				"dmic",
				"miso_off",
				"miso_on",
				"mosi_off",
				"mosi_on";
		pinctrl-0 = <&aud_default_pins>;
		pinctrl-1 = <&aud_dmic_pins>;
		pinctrl-2 = <&aud_miso_off_pins>;
		pinctrl-3 = <&aud_miso_on_pins>;
		pinctrl-4 = <&aud_mosi_off_pins>;
		pinctrl-5 = <&aud_mosi_on_pins>;
		mediatek,platform = <&afe>;
	};
};

&afe {
	mediatek,dmic-mode = <1>;
	status = "okay";
};

&cpu0 {
	proc-supply = <&mt6357_vproc_reg>;
	sram-supply = <&mt6357_vsram_proc_reg>;
};

&cpu1 {
	proc-supply = <&mt6357_vproc_reg>;
	sram-supply = <&mt6357_vsram_proc_reg>;
};

&cpu2 {
	proc-supply = <&mt6357_vproc_reg>;
	sram-supply = <&mt6357_vsram_proc_reg>;
};

&cpu3 {
	proc-supply = <&mt6357_vproc_reg>;
	sram-supply = <&mt6357_vsram_proc_reg>;
};

&ethernet {
	pinctrl-0 = <&ethernet_pins>;
	pinctrl-names = "default";
	phy-handle = <&eth_phy>;
	phy-mode = "rmii";
	/*
	 * Ethernet and HDMI (DSI0) are sharing pins.
	 * Only one can be enabled at a time and require the physical switch
	 * SW2101 to be set on LAN position
	 * mt6357_vibr_reg and mt6357_vsim2_reg are needed to supply ethernet
	 */
	status = "disabled";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		eth_phy: ethernet-phy@0 {
			reg = <0>;
		};
	};
};

&i2c0 {
	clock-frequency = <100000>;
	pinctrl-0 = <&i2c0_pins>;
	pinctrl-names = "default";
	status = "okay";
};

&mmc0 {
	assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL>;
	assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>;
	bus-width = <8>;
	cap-mmc-highspeed;
	cap-mmc-hw-reset;
	hs400-ds-delay = <0x12012>;
	max-frequency = <200000000>;
	mmc-hs200-1_8v;
	mmc-hs400-1_8v;
	no-sd;
	no-sdio;
	non-removable;
	pinctrl-0 = <&mmc0_default_pins>;
	pinctrl-1 = <&mmc0_uhs_pins>;
	pinctrl-names = "default", "state_uhs";
	vmmc-supply = <&mt6357_vemc_reg>;
	vqmmc-supply = <&mt6357_vio18_reg>;
	status = "okay";
};

&mmc1 {
	bus-width = <4>;
	cap-sd-highspeed;
	cd-gpios = <&pio 76 GPIO_ACTIVE_LOW>;
	max-frequency = <200000000>;
	pinctrl-0 = <&mmc1_default_pins>;
	pinctrl-1 = <&mmc1_uhs_pins>;
	pinctrl-names = "default", "state_uhs";
	sd-uhs-sdr104;
	sd-uhs-sdr50;
	vmmc-supply = <&mt6357_vmch_reg>;
	vqmmc-supply = <&mt6357_vmc_reg>;
	status = "okay";
};

&mt6357_pmic {
	interrupts-extended = <&pio 145 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-controller;
	#interrupt-cells = <2>;
	mediatek,micbias0-microvolt = <1900000>;
	mediatek,micbias1-microvolt = <1700000>;
};

&pio {
	aud_default_pins: audiodefault-pins {
		clk-dat-pins {
			pinmux = <MT8365_PIN_72_CMDAT4__FUNC_I2S3_BCK>,
				 <MT8365_PIN_73_CMDAT5__FUNC_I2S3_LRCK>,
				 <MT8365_PIN_74_CMDAT6__FUNC_I2S3_MCK>,
				 <MT8365_PIN_75_CMDAT7__FUNC_I2S3_DO>;
		};
	};

	aud_dmic_pins: audiodmic-pins {
		clk-dat-pins {
			pinmux = <MT8365_PIN_117_DMIC0_CLK__FUNC_DMIC0_CLK>,
				 <MT8365_PIN_118_DMIC0_DAT0__FUNC_DMIC0_DAT0>,
				 <MT8365_PIN_119_DMIC0_DAT1__FUNC_DMIC0_DAT1>;
		};
	};

	aud_miso_off_pins: misooff-pins {
		clk-dat-pins {
			pinmux = <MT8365_PIN_53_AUD_CLK_MISO__FUNC_GPIO53>,
				 <MT8365_PIN_54_AUD_SYNC_MISO__FUNC_GPIO54>,
				 <MT8365_PIN_55_AUD_DAT_MISO0__FUNC_GPIO55>,
				 <MT8365_PIN_56_AUD_DAT_MISO1__FUNC_GPIO56>;
			input-enable;
			bias-pull-down;
			drive-strength = <2>;
		};
	};

	aud_miso_on_pins: misoon-pins {
		clk-dat-pins {
			pinmux = <MT8365_PIN_53_AUD_CLK_MISO__FUNC_AUD_CLK_MISO>,
				 <MT8365_PIN_54_AUD_SYNC_MISO__FUNC_AUD_SYNC_MISO>,
				 <MT8365_PIN_55_AUD_DAT_MISO0__FUNC_AUD_DAT_MISO0>,
				 <MT8365_PIN_56_AUD_DAT_MISO1__FUNC_AUD_DAT_MISO1>;
			drive-strength = <6>;
		};
	};

	aud_mosi_off_pins: mosioff-pins {
		clk-dat-pins {
			pinmux = <MT8365_PIN_49_AUD_CLK_MOSI__FUNC_GPIO49>,
				 <MT8365_PIN_50_AUD_SYNC_MOSI__FUNC_GPIO50>,
				 <MT8365_PIN_51_AUD_DAT_MOSI0__FUNC_GPIO51>,
				 <MT8365_PIN_52_AUD_DAT_MOSI1__FUNC_GPIO52>;
			input-enable;
			bias-pull-down;
			drive-strength = <2>;
		};
	};

	aud_mosi_on_pins: mosion-pins {
		clk-dat-pins {
			pinmux = <MT8365_PIN_49_AUD_CLK_MOSI__FUNC_AUD_CLK_MOSI>,
				 <MT8365_PIN_50_AUD_SYNC_MOSI__FUNC_AUD_SYNC_MOSI>,
				 <MT8365_PIN_51_AUD_DAT_MOSI0__FUNC_AUD_DAT_MOSI0>,
				 <MT8365_PIN_52_AUD_DAT_MOSI1__FUNC_AUD_DAT_MOSI1>;
			drive-strength = <6>;
		};
	};

	ethernet_pins: ethernet-pins {
		phy_reset_pins {
			pinmux = <MT8365_PIN_133_TDM_TX_DATA1__FUNC_GPIO133>;
		};

		rmii_pins {
			pinmux = <MT8365_PIN_0_GPIO0__FUNC_EXT_TXD0>,
				 <MT8365_PIN_1_GPIO1__FUNC_EXT_TXD1>,
				 <MT8365_PIN_2_GPIO2__FUNC_EXT_TXD2>,
				 <MT8365_PIN_3_GPIO3__FUNC_EXT_TXD3>,
				 <MT8365_PIN_4_GPIO4__FUNC_EXT_TXC>,
				 <MT8365_PIN_5_GPIO5__FUNC_EXT_RXER>,
				 <MT8365_PIN_6_GPIO6__FUNC_EXT_RXC>,
				 <MT8365_PIN_7_GPIO7__FUNC_EXT_RXDV>,
				 <MT8365_PIN_8_GPIO8__FUNC_EXT_RXD0>,
				 <MT8365_PIN_9_GPIO9__FUNC_EXT_RXD1>,
				 <MT8365_PIN_10_GPIO10__FUNC_EXT_RXD2>,
				 <MT8365_PIN_11_GPIO11__FUNC_EXT_RXD3>,
				 <MT8365_PIN_12_GPIO12__FUNC_EXT_TXEN>,
				 <MT8365_PIN_13_GPIO13__FUNC_EXT_COL>,
				 <MT8365_PIN_14_GPIO14__FUNC_EXT_MDIO>,
				 <MT8365_PIN_15_GPIO15__FUNC_EXT_MDC>;
		};
	};

	gpio_keys: gpio-keys-pins {
		pins {
			pinmux = <MT8365_PIN_24_KPCOL0__FUNC_KPCOL0>;
			bias-pull-up;
			input-enable;
		};
	};

	i2c0_pins: i2c0-pins {
		pins {
			pinmux = <MT8365_PIN_57_SDA0__FUNC_SDA0_0>,
				 <MT8365_PIN_58_SCL0__FUNC_SCL0_0>;
			bias-pull-up;
		};
	};

	mmc0_default_pins: mmc0-default-pins {
		clk-pins {
			pinmux = <MT8365_PIN_99_MSDC0_CLK__FUNC_MSDC0_CLK>;
			bias-pull-down;
		};

		cmd-dat-pins {
			pinmux = <MT8365_PIN_103_MSDC0_DAT0__FUNC_MSDC0_DAT0>,
				 <MT8365_PIN_102_MSDC0_DAT1__FUNC_MSDC0_DAT1>,
				 <MT8365_PIN_101_MSDC0_DAT2__FUNC_MSDC0_DAT2>,
				 <MT8365_PIN_100_MSDC0_DAT3__FUNC_MSDC0_DAT3>,
				 <MT8365_PIN_96_MSDC0_DAT4__FUNC_MSDC0_DAT4>,
				 <MT8365_PIN_95_MSDC0_DAT5__FUNC_MSDC0_DAT5>,
				 <MT8365_PIN_94_MSDC0_DAT6__FUNC_MSDC0_DAT6>,
				 <MT8365_PIN_93_MSDC0_DAT7__FUNC_MSDC0_DAT7>,
				 <MT8365_PIN_98_MSDC0_CMD__FUNC_MSDC0_CMD>;
			input-enable;
			bias-pull-up;
		};

		rst-pins {
			pinmux = <MT8365_PIN_97_MSDC0_RSTB__FUNC_MSDC0_RSTB>;
			bias-pull-up;
		};
	};

	mmc0_uhs_pins: mmc0-uhs-pins {
		clk-pins {
			pinmux = <MT8365_PIN_99_MSDC0_CLK__FUNC_MSDC0_CLK>;
			drive-strength = <MTK_DRIVE_10mA>;
			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
		};

		cmd-dat-pins {
			pinmux = <MT8365_PIN_103_MSDC0_DAT0__FUNC_MSDC0_DAT0>,
				 <MT8365_PIN_102_MSDC0_DAT1__FUNC_MSDC0_DAT1>,
				 <MT8365_PIN_101_MSDC0_DAT2__FUNC_MSDC0_DAT2>,
				 <MT8365_PIN_100_MSDC0_DAT3__FUNC_MSDC0_DAT3>,
				 <MT8365_PIN_96_MSDC0_DAT4__FUNC_MSDC0_DAT4>,
				 <MT8365_PIN_95_MSDC0_DAT5__FUNC_MSDC0_DAT5>,
				 <MT8365_PIN_94_MSDC0_DAT6__FUNC_MSDC0_DAT6>,
				 <MT8365_PIN_93_MSDC0_DAT7__FUNC_MSDC0_DAT7>,
				 <MT8365_PIN_98_MSDC0_CMD__FUNC_MSDC0_CMD>;
			input-enable;
			drive-strength = <MTK_DRIVE_10mA>;
			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
		};

		ds-pins {
			pinmux = <MT8365_PIN_104_MSDC0_DSL__FUNC_MSDC0_DSL>;
			drive-strength = <MTK_DRIVE_10mA>;
			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
		};

		rst-pins {
			pinmux = <MT8365_PIN_97_MSDC0_RSTB__FUNC_MSDC0_RSTB>;
			drive-strength = <MTK_DRIVE_10mA>;
			bias-pull-up;
		};
	};

	mmc1_default_pins: mmc1-default-pins {
		cd-pins {
			pinmux = <MT8365_PIN_76_CMDAT8__FUNC_GPIO76>;
			bias-pull-up;
		};

		clk-pins {
			pinmux = <MT8365_PIN_88_MSDC1_CLK__FUNC_MSDC1_CLK>;
			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
		};

		cmd-dat-pins {
			pinmux = <MT8365_PIN_89_MSDC1_DAT0__FUNC_MSDC1_DAT0>,
				 <MT8365_PIN_90_MSDC1_DAT1__FUNC_MSDC1_DAT1>,
				 <MT8365_PIN_91_MSDC1_DAT2__FUNC_MSDC1_DAT2>,
				 <MT8365_PIN_92_MSDC1_DAT3__FUNC_MSDC1_DAT3>,
				 <MT8365_PIN_87_MSDC1_CMD__FUNC_MSDC1_CMD>;
			input-enable;
			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
		};
	};

	mmc1_uhs_pins: mmc1-uhs-pins {
		clk-pins {
			pinmux = <MT8365_PIN_88_MSDC1_CLK__FUNC_MSDC1_CLK>;
			drive-strength = <8>;
			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
		};

		cmd-dat-pins {
			pinmux = <MT8365_PIN_89_MSDC1_DAT0__FUNC_MSDC1_DAT0>,
				 <MT8365_PIN_90_MSDC1_DAT1__FUNC_MSDC1_DAT1>,
				 <MT8365_PIN_91_MSDC1_DAT2__FUNC_MSDC1_DAT2>,
				 <MT8365_PIN_92_MSDC1_DAT3__FUNC_MSDC1_DAT3>,
				 <MT8365_PIN_87_MSDC1_CMD__FUNC_MSDC1_CMD>;
			input-enable;
			drive-strength = <6>;
			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
		};
	};

	uart0_pins: uart0-pins {
		pins {
			pinmux = <MT8365_PIN_35_URXD0__FUNC_URXD0>,
				 <MT8365_PIN_36_UTXD0__FUNC_UTXD0>;
		};
	};

	uart1_pins: uart1-pins {
		pins {
			pinmux = <MT8365_PIN_37_URXD1__FUNC_URXD1>,
				 <MT8365_PIN_38_UTXD1__FUNC_UTXD1>;
		};
	};

	uart2_pins: uart2-pins {
		pins {
			pinmux = <MT8365_PIN_39_URXD2__FUNC_URXD2>,
				 <MT8365_PIN_40_UTXD2__FUNC_UTXD2>;
		};
	};

	usb_pins: usb-pins {
		id-pins {
			pinmux = <MT8365_PIN_17_GPIO17__FUNC_GPIO17>;
			input-enable;
			bias-pull-up;
		};

		usb0-vbus-pins {
			pinmux = <MT8365_PIN_16_GPIO16__FUNC_USB_DRVVBUS>;
			output-high;
		};

		usb1-vbus-pins {
			pinmux = <MT8365_PIN_18_GPIO18__FUNC_GPIO18>;
			output-high;
		};
	};

	pwm_pins: pwm-pins {
		pins {
			pinmux = <MT8365_PIN_19_DISP_PWM__FUNC_PWM_A>,
				 <MT8365_PIN_116_I2S_BCK__FUNC_PWM_C>;
		};
	};
};

&pwm {
	pinctrl-0 = <&pwm_pins>;
	pinctrl-names = "default";
	status = "okay";
};

&ssusb {
	dr_mode = "otg";
	maximum-speed = "high-speed";
	pinctrl-0 = <&usb_pins>;
	pinctrl-names = "default";
	usb-role-switch;
	vusb33-supply = <&mt6357_vusb33_reg>;
	status = "okay";

	connector {
		compatible = "gpio-usb-b-connector", "usb-b-connector";
		id-gpios = <&pio 17 GPIO_ACTIVE_HIGH>;
		type = "micro";
		vbus-supply = <&usb_otg_vbus>;
	};
};

&usb_host {
	vusb33-supply = <&mt6357_vusb33_reg>;
	status = "okay";
};

&uart0 {
	pinctrl-0 = <&uart0_pins>;
	pinctrl-names = "default";
	status = "okay";
};

&uart1 {
	pinctrl-0 = <&uart1_pins>;
	pinctrl-names = "default";
	status = "okay";
};

&uart2 {
	pinctrl-0 = <&uart2_pins>;
	pinctrl-names = "default";
	status = "okay";
};