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/linux/Documentation/devicetree/bindings/mailbox/
H A Dfsl,mu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dong Aisheng <aisheng.dong@nxp.com>
22 registers (Processor A-facing, Processor B-facing).
27 - const: fsl,imx6sx-mu
28 - const: fsl,imx7ulp-mu
29 - const: fsl,imx8ulp-mu
30 - const: fsl,imx8-mu-scu
31 - const: fsl,imx8-mu-seco
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/linux/Documentation/devicetree/bindings/firmware/
H A Darm,scmi.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Sudeep Holla <sudeep.holla@arm.com>
26 - $ref: /schemas/firmware/nxp,imx95-scmi.yaml
34 - description: SCMI compliant firmware with mailbox transport
36 - const: arm,scmi
37 - description: SCMI compliant firmware with ARM SMC/HVC transport
39 - const: arm,scmi-smc
40 - description: SCMI compliant firmware with ARM SMC/HVC transport
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H A Darm,scpi.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Sudeep Holla <sudeep.holla@arm.com>
33 - const: arm,scpi # SCPI v1.0 and above
34 - const: arm,scpi-pre-1.0 # Unversioned SCPI before v1.0
35 - items:
36 - enum:
37 - amlogic,meson-gxbb-scpi
38 - const: arm,scpi-pre-1.0
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/linux/arch/arm/boot/dts/allwinner/
H A Dsun5i.dtsi2 * Copyright 2012-2015 Maxime Ripard
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * This file is dual-licensed: you can use it either under the terms
45 #include <dt-bindings/clock/sun5i-ccu.h>
46 #include <dt-bindings/dma/sun4i-a10.h>
47 #include <dt-bindings/reset/sun5i-ccu.h>
50 interrupt-parent = <&intc>;
51 #address-cells = <1>;
52 #size-cells = <1>;
55 #address-cells = <1>;
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H A Dsun8i-h3.dtsi4 * This file is dual-licensed: you can use it either under the terms
43 #include "sunxi-h3-h5.dtsi"
44 #include <dt-bindings/thermal/thermal.h>
47 cpu0_opp_table: opp-table-cpu {
48 compatible = "operating-points-v2";
49 opp-shared;
51 opp-648000000 {
52 opp-hz = /bits/ 64 <648000000>;
53 opp-microvolt = <1040000 1040000 1300000>;
54 clock-latency-ns = <244144>; /* 8 32k periods */
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H A Dsun4i-a10.dtsi5 * This file is dual-licensed: you can use it either under the terms
44 #include <dt-bindings/thermal/thermal.h>
45 #include <dt-bindings/dma/sun4i-a10.h>
46 #include <dt-bindings/clock/sun4i-a10-ccu.h>
47 #include <dt-bindings/reset/sun4i-a10-ccu.h>
50 #address-cells = <1>;
51 #size-cells = <1>;
52 interrupt-parent = <&intc>;
59 #address-cells = <1>;
60 #size-cells = <1>;
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H A Dsun7i-a20.dtsi4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * This file is dual-licensed: you can use it either under the terms
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/thermal/thermal.h>
47 #include <dt-bindings/dma/sun4i-a10.h>
48 #include <dt-bindings/clock/sun7i-a20-ccu.h>
49 #include <dt-bindings/reset/sun4i-a10-ccu.h>
50 #include <dt-bindings/pinctrl/sun4i-a10.h>
53 interrupt-parent = <&gic>;
54 #address-cells = <1>;
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H A Dsun8i-a23-a33.dtsi2 * Copyright 2014 Chen-Yu Tsai
4 * Chen-Yu Tsai <wens@csie.org>
6 * This file is dual-licensed: you can use it either under the terms
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
47 #include <dt-bindings/clock/sun6i-rtc.h>
48 #include <dt-bindings/clock/sun8i-a23-a33-ccu.h>
49 #include <dt-bindings/reset/sun8i-a23-a33-ccu.h>
52 interrupt-parent = <&gic>;
53 #address-cells = <1>;
54 #size-cells = <1>;
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H A Dsun8i-r40.dtsi2 * Copyright 2017 Chen-Yu Tsai <wens@csie.org>
5 * This file is dual-licensed: you can use it either under the terms
44 #include <dt-bindings/interrupt-controller/arm-gic.h>
45 #include <dt-bindings/clock/sun6i-rtc.h>
46 #include <dt-bindings/clock/sun8i-de2.h>
47 #include <dt-bindings/clock/sun8i-r40-ccu.h>
48 #include <dt-bindings/clock/sun8i-tcon-top.h>
49 #include <dt-bindings/reset/sun8i-r40-ccu.h>
50 #include <dt-bindings/reset/sun8i-de2.h>
51 #include <dt-bindings/thermal/thermal.h>
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/linux/drivers/memory/
H A Dti-emif-pm.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * TI AM33XX SRAM EMIF Driver
5 * Copyright (C) 2016-2017 Texas Instruments Inc.
17 #include <linux/sram.h>
18 #include <linux/ti-emif-sram.h>
22 #define TI_EMIF_SRAM_SYMBOL_OFFSET(sym) ((unsigned long)(sym) - \
43 return (emif_data->ti_emif_sram_virt + in sram_suspend_address()
50 return ((unsigned long)emif_data->ti_emif_sram_phys + in sram_resume_address()
56 gen_pool_free(emif_data->sram_pool_code, emif_data->ti_emif_sram_virt, in ti_emif_free_sram()
58 gen_pool_free(emif_data->sram_pool_data, in ti_emif_free_sram()
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/linux/arch/arm64/boot/dts/allwinner/
H A Dsun50i-h5.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 #include <arm/allwinner/sunxi-h3-h5.dtsi>
6 #include <dt-bindings/thermal/thermal.h>
10 #address-cells = <1>;
11 #size-cells = <0>;
14 compatible = "arm,cortex-a53";
17 enable-method = "psci";
19 clock-latency-ns = <244144>; /* 8 32k periods */
20 #cooling-cells = <2>;
24 compatible = "arm,cortex-a53";
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H A Dsun50i-h6.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/clock/sun50i-h6-ccu.h>
6 #include <dt-bindings/clock/sun50i-h6-r-ccu.h>
7 #include <dt-bindings/clock/sun6i-rtc.h>
8 #include <dt-bindings/clock/sun8i-de2.h>
9 #include <dt-bindings/clock/sun8i-tcon-top.h>
10 #include <dt-bindings/reset/sun50i-h6-ccu.h>
11 #include <dt-bindings/reset/sun50i-h6-r-ccu.h>
12 #include <dt-bindings/reset/sun8i-de2.h>
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/linux/drivers/input/touchscreen/
H A Dgoodix_fwupload.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Copyright (c) 2010 - 2012 Goodix Technology.
54 if (fw->size != expected_size) { in goodix_firmware_verify()
56 expected_size, fw->size); in goodix_firmware_verify()
57 return -EINVAL; in goodix_firmware_verify()
60 data = fw->data + GOODIX_FW_HEADER_LENGTH; in goodix_firmware_verify()
64 return -EINVAL; in goodix_firmware_verify()
71 return -EINVAL; in goodix_firmware_verify()
74 fw_header = (const struct goodix_fw_header *)fw->data; in goodix_firmware_verify()
76 fw_header->hw_info[0], fw_header->hw_info[1], in goodix_firmware_verify()
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/linux/Documentation/driver-api/memory-devices/
H A Dti-gpmc.rst1 .. SPDX-License-Identifier: GPL-2.0
10 * Asynchronous SRAM like memories and application specific integrated
14 * Pseudo-SRAM devices
17 IP details: https://www.ti.com/lit/pdf/spruh73 section 7.1
85 4. read async non-muxed
107 6. read sync non-muxed
131 8. write async non-muxed
157 10. write sync non-muxed
/linux/arch/arm/mach-rockchip/
H A Dsleep.S1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Author: Tony Xie <tony.xie@rock-chips.com>
14 * ddr to sram for system resumeing.
15 * so it is ".data section".
64 .word . - rockchip_slp_cpu_resume
/linux/Documentation/devicetree/bindings/remoteproc/
H A Dxlnx,zynqmp-r5fss.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/xlnx,zynqmp-r5fss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ben Levinsky <ben.levinsky@amd.com>
11 - Tanmay Shah <tanmay.shah@amd.com>
14 The Xilinx platforms include a pair of Cortex-R5F processors (RPU) for
15 real-time processing based on the Cortex-R5F processor core from ARM.
16 The Cortex-R5F processor implements the Arm v7-R architecture and includes a
17 floating-point unit that implements the Arm VFPv3 instruction set.
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/linux/sound/soc/intel/catpt/
H A Ddsp.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/dma-mapping.h>
19 return param == chan->device->dev; in catpt_dma_filter()
39 chan = dma_request_channel(mask, catpt_dma_filter, cdev->dev); in catpt_dma_request_config_chan()
41 dev_err(cdev->dev, "request channel failed\n"); in catpt_dma_request_config_chan()
42 return ERR_PTR(-ENODEV); in catpt_dma_request_config_chan()
54 dev_err(cdev->dev, "slave config failed: %d\n", ret); in catpt_dma_request_config_chan()
73 dev_err(cdev->dev, "prep dma memcpy failed\n"); in catpt_dma_memcpy()
74 return -EIO; in catpt_dma_memcpy()
79 CATPT_HMDC_HDDA(CATPT_DMA_DEVID, chan->chan_id), in catpt_dma_memcpy()
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/linux/drivers/atm/
H A Dnicstar.h1 /* SPDX-License-Identifier: GPL-2.0 */
44 have 32K x 32bit SRAM, in which case
48 128K x 32bit SRAM will limit the maximum
56 #define NUM_HB 8 /* Pre-allocated huge buffers */
107 #define NS_MAX_IOVECS (2 + (65568 - NS_SMBUFSIZE) / \
108 (NS_LGBUFSIZE - (NS_LGBUFSIZE % 48)))
111 #define NS_SMBUFSIZE_USABLE (NS_SMBUFSIZE - NS_SMBUFSIZE % 48)
112 #define NS_LGBUFSIZE_USABLE (NS_LGBUFSIZE - NS_LGBUFSIZE % 48)
114 #define NS_AAL0_HEADER (ATM_AAL0_SDU - ATM_CELL_PAYLOAD) /* 4 bytes */
122 * RSQ - Receive Status Queue
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/linux/drivers/mtd/nand/raw/
H A Dmxc_nand.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
28 #define NFC_V1_V2_BUF_SIZE (host->regs + 0x00)
29 #define NFC_V1_V2_BUF_ADDR (host->regs + 0x04)
30 #define NFC_V1_V2_FLASH_ADDR (host->regs + 0x06)
31 #define NFC_V1_V2_FLASH_CMD (host->regs + 0x08)
32 #define NFC_V1_V2_CONFIG (host->regs + 0x0a)
33 #define NFC_V1_V2_ECC_STATUS_RESULT (host->regs + 0x0c)
34 #define NFC_V1_V2_RSLTMAIN_AREA (host->regs + 0x0e)
35 #define NFC_V21_RSLTSPARE_AREA (host->regs + 0x10)
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H A Dfsl_ifc_nand.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2011-2012 Freescale Semiconductor, Inc
51 unsigned int eccread; /* Non zero for a full-page ECC read */
67 .offs = 2, /* 0 on 8-bit small page */
77 .offs = 2, /* 0 on 8-bit small page */
84 static int fsl_ifc_ooblayout_ecc(struct mtd_info *mtd, int section, in fsl_ifc_ooblayout_ecc() argument
89 if (section) in fsl_ifc_ooblayout_ecc()
90 return -ERANGE; in fsl_ifc_ooblayout_ecc()
92 oobregion->offset = 8; in fsl_ifc_ooblayout_ecc()
93 oobregion->length = chip->ecc.total; in fsl_ifc_ooblayout_ecc()
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/linux/drivers/crypto/marvell/cesa/
H A Dcesa.h1 /* SPDX-License-Identifier: GPL-2.0 */
8 #include <linux/dma-direction.h>
70 * in Errata 4.12. It looks like that it was part of an IRQ-controller in FPGA
124 * /-----------\ 0
126 * |-----------| 0x20
128 * |-----------| 0x40
130 * |-----------| 0x40 (inplace)
132 * |-----------| 0x80
133 * | DATA IN | 16 * x (max ->max_req_size)
134 * |-----------| 0x80 (inplace operation)
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/linux/Documentation/driver-api/
H A Dmen-chameleon-bus.rst31 ----------------------
38 -----------------------------------------
44 - Multi-resource MCB devices like the VME Controller or M-Module carrier.
45 - MCB devices that need another MCB device, like SRAM for a DMA Controller's
47 - A per-carrier IRQ domain for carrier devices that have one (or more) IRQs
48 per MCB device like PCIe based carriers with MSI or MSI-X support.
55 - The MEN Chameleon Bus itself,
56 - drivers for MCB Carrier Devices and
57 - the parser for the Chameleon table.
60 -----------------
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/linux/arch/arm/mach-omap1/
H A Dsleep.S2 * linux/arch/arm/mach-omap1/sleep.S
4 * Low-level OMAP7XX/1510/1610 sleep/wakeUp support
56 * Note: This code get's copied to internal SRAM at boot. When the OMAP
69 stmfd sp!, {r0 - r12, lr}
86 @ prepare to put SDRAM into self-refresh manually
133 ldmfd sp!, {r0 - r12, pc}
136 .word . - omap1510_cpu_suspend
144 stmfd sp!, {r0 - r12, lr}
156 @ Prepare to put SDRAM into self-refresh manually
190 @ Errata (HEL3SU467, section 1.4.4) specifies nop-instructions
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/linux/drivers/net/wireless/intel/iwlegacy/
H A D4965.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
8 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
15 #include <linux/dma-mapping.h>
29 * il_verify_inst_sparse - verify runtime uCode image in card vs. host,
44 /* read data comes through single port, auto-incr addr */ in il4965_verify_inst_sparse()
50 ret = -EIO; in il4965_verify_inst_sparse()
61 * il4965_verify_inst_full - verify runtime uCode image in card vs. host,
77 for (; len > 0; len -= sizeof(u32), image++) { in il4965_verify_inst_full()
78 /* read data comes through single port, auto-incr addr */ in il4965_verify_inst_full()
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/linux/drivers/base/power/
H A Dtrace.c1 // SPDX-License-Identifier: GPL-2.0
12 #include <linux/pm-trace.h>
30 * other bank of an additional 128 bytes) of nice SRAM that is
31 * _designed_ to keep data - the POST will clear it. So we literally
45 * - year: 0-99
46 * - month: 0-11
47 * - day-of-month: 1-28
48 * - hour: 0-23
49 * - min: (0-30)*2
51 * Giving us a total range of 0-16128000 (0xf61800), ie less
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