Home
last modified time | relevance | path

Searched full:spread (Results 1 – 25 of 251) sorted by relevance

1234567891011

/linux/drivers/scsi/isci/
H A Dprobe_roms.h228 * Spread Spectrum Clocking (SSC) settings for SATA and SAS.
234 * NOTE: Max spread for SATA is +0 / -5000 PPM.
237 * SATA SSC Tx at +0 / -1419 PPM Spread = 0x2
238 * SATA SSC Tx at +0 / -2129 PPM Spread = 0x3
239 * SATA SSC Tx at +0 / -4257 PPM Spread = 0x6
240 * SATA SSC Tx at +0 / -4967 PPM Spread = 0x7
246 * NOTE: Max spread for SAS down-spreading +0 /
249 * SAS SSC Tx at +0 / -1419 PPM Spread = 0x2
250 * SAS SSC Tx at +0 / -2129 PPM Spread = 0x3
252 * NOTE: Max spread for SAS center-spreading +2300 /
[all …]
/linux/Documentation/devicetree/bindings/clock/ti/
H A Ddpll.txt43 "ssc-deltam" - DPLL supports spread spectrum clocking (SSC), contains
45 "ssc-modfreq" - DPLL supports spread spectrum clocking (SSC), contains
59 - ti,ssc-deltam : DPLL supports spread spectrum clocking, frequency
61 - ti,ssc-modfreq-hz : DPLL supports spread spectrum clocking, spread
63 - ti,ssc-downspread : DPLL supports spread spectrum clocking, boolean
/linux/Documentation/devicetree/bindings/clock/
H A Dti,cdce925.yaml57 optional child node can be used to specify spread
63 spread-spectrum:
67 spread-spectrum-center:
99 spread-spectrum = <4>;
100 spread-spectrum-center;
H A Dmediatek,mt8186-fhctl.yaml7 title: MediaTek frequency hopping and spread spectrum clocking control
15 Spread spectrum clocking (SSC) is another function provided by this hardware.
35 description: The percentage of spread spectrum clocking for one PLL.
H A Dnuvoton,ma35d1-clk.yaml43 - spread-spectrum
/linux/Documentation/ABI/testing/
H A Dsysfs-platform-dptf134 (RO) Presents SSC (spread spectrum clock) information for EMI
140 [7:0] Sets clock spectrum spread percentage:
142 1 LSB = 0.1% increase in spread (for
144 1 LSB = 0.2% increase in spread (for
146 [8] When set to 1, enables spread
153 (Spread spectrum clock) range
155 to spread waveform
/linux/Documentation/devicetree/bindings/regulator/
H A Dnvidia,tegra-regulators-coupling.txt40 regulator-coupled-max-spread = <170000 550000>;
50 regulator-coupled-max-spread = <170000 550000>;
60 regulator-coupled-max-spread = <550000 550000>;
/linux/drivers/clk/
H A Dclk-eyeq.c67 /* Spread amplitude (% = 0.1 * SPREAD[4:0]) */
70 /* Down-spread or center-spread */
226 unsigned long spread; in eqc_pll_parse_fracg() local
262 * Spread spectrum. in eqc_pll_parse_fracg()
264 * Spread is in 1/1024 parts of frequency. Clock accuracy in eqc_pll_parse_fracg()
265 * is half the spread value expressed in parts per billion. in eqc_pll_parse_fracg()
267 * accuracy = (spread * 1e9) / (1024 * 2) in eqc_pll_parse_fracg()
271 spread = FIELD_GET(FRACG_PCSR1_SPREAD, r1); in eqc_pll_parse_fracg()
272 *acc = DIV_ROUND_CLOSEST(spread * 1000000000, 1024 * 2); in eqc_pll_parse_fracg()
277 * spread lower. in eqc_pll_parse_fracg()
[all …]
H A Dclk-renesas-pcie.c229 /* Output clock spread spectrum */ in rs9_get_common_config()
230 ret = of_property_read_u32(np, "renesas,out-spread-spectrum", &ssc); in rs9_get_common_config()
232 if (ssc == 100000) /* 100% ... no spread (default) */ in rs9_get_common_config()
234 else if (ssc == 99750) /* -0.25% ... down spread */ in rs9_get_common_config()
236 else if (ssc == 99500) /* -0.50% ... down spread */ in rs9_get_common_config()
240 "Invalid renesas,out-spread-spectrum value\n"); in rs9_get_common_config()
H A Dclk-scmi-oem.c42 * extConfigValue[7:0] - spread percentage (%) in scmi_clk_imx_set_spread_spectrum()
56 "Failed to set spread spectrum(%u,%u,%u) for clock ID %d\n", in scmi_clk_imx_set_spread_spectrum()
/linux/Documentation/misc-devices/
H A Dics932s401.rst25 frequency. If spread spectrum mode is enabled, the driver also reports by what
26 percent the clock signal is being spread, which should be between 0 and -0.5%.
/linux/lib/zstd/common/
H A Dfse_decompress.c64 BYTE* spread = (BYTE*)(symbolNext + maxSymbolValue + 1); in FSE_buildDTable_internal() local
92 /* Spread symbols */ in FSE_buildDTable_internal()
109 MEM_write64(spread + pos, sv); in FSE_buildDTable_internal()
111 MEM_write64(spread + pos + i, sv); in FSE_buildDTable_internal()
115 /* Now we spread those positions across the table. in FSE_buildDTable_internal()
130 tableDecode[uPosition].symbol = spread[s + u]; in FSE_buildDTable_internal()
/linux/Documentation/sound/codecs/
H A Dtas675x.rst165 Spread Spectrum Mode
177 :Description: Frequency deviation range for Triangle spread spectrum.
182 :Note: Applies only when Spread Spectrum Mode includes Triangle.
187 :Description: Frequency deviation range for Random spread spectrum.
192 :Note: Applies only when Spread Spectrum Mode includes Random.
197 :Description: Dwell time range for Random spread spectrum (FSS = spread
203 :Note: Applies only when Spread Spectrum Mode includes Random.
208 :Description: Minimum dwell time at Triangle spread spectrum frequency extremes.
216 For FSS values at each PWM frequency refer to the "Spread
222 :Description: Maximum dwell time at Triangle spread spectrum frequency extremes.
/linux/Documentation/devicetree/bindings/ata/
H A Dimx-sata.yaml60 fsl,no-spread-spectrum:
62 description: if present, disable spread-spectrum clocking on the SATA link.
/linux/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/
H A Dsmu11_driver_if_sienna_cichlid.h906 // SECTION: Clock Spread Spectrum
908 // GFXCLK PLL Spread Spectrum
913 // GFXCLK DFLL Spread Spectrum
918 // UCLK Spread Spectrum
922 // FCLK Spread Spectrum
949 // UCLK Spread Spectrum
1267 // SECTION: Clock Spread Spectrum
1269 // GFXCLK PLL Spread Spectrum
1274 // GFXCLK DFLL Spread Spectrum
1279 // UCLK Spread Spectrum
[all …]
/linux/drivers/gpu/drm/nouveau/dispnv04/
H A Ddfp.c214 * It toggles spread spectrum PLL output and sets the bindings of PLLs in nv04_dfp_prepare_sel_clk()
223 * bit 0 NVClk spread spectrum on/off in nv04_dfp_prepare_sel_clk()
224 * bit 2 MemClk spread spectrum on/off in nv04_dfp_prepare_sel_clk()
225 * bit 4 PixClk1 spread spectrum on/off toggle in nv04_dfp_prepare_sel_clk()
226 * bit 6 PixClk2 spread spectrum on/off toggle in nv04_dfp_prepare_sel_clk()
231 * maybe a different spread mode in nv04_dfp_prepare_sel_clk()
233 * The logic behind turning spread spectrum on/off in the first place, in nv04_dfp_prepare_sel_clk()
/linux/drivers/phy/starfive/
H A Dphy-jh7110-pcie.c65 /* Configuare spread-spectrum mode: down-spread-spectrum */ in phy_usb3_mode_set()
/linux/lib/
H A Dgroup_cpus.c269 /* Spread allocated groups on CPUs of the current node */ in assign_cpus_to_groups()
422 * number of groups we just spread the groups across the nodes. in __group_cpus_evenly()
517 * spread can observe consistent 'cpu_present_mask' without holding in group_cpus_evenly()
524 * from API user viewpoint since 2-stage spread is sort of in group_cpus_evenly()
/linux/Documentation/admin-guide/device-mapper/
H A Dswitch.rst22 is created it is spread across multiple members. The details of the
44 spread with an address region size on the order of 10s of MBs, which
/linux/lib/zstd/compress/
H A Dfse_compress.c116 /* Spread symbols */ in FSE_buildCTable_wksp()
121 …BYTE* const spread = tableSymbol + tableSize; /* size = tableSize + 8 (may write beyond tableSize)… in FSE_buildCTable_wksp() local
129 MEM_write64(spread + pos, sv); in FSE_buildCTable_wksp()
131 MEM_write64(spread + pos + i, sv); in FSE_buildCTable_wksp()
137 /* Spread symbols across the table. Lack of lowprob symbols means that in FSE_buildCTable_wksp()
149 tableSymbol[uPosition] = spread[s + u]; in FSE_buildCTable_wksp()
/linux/fs/udf/
H A Dballoc.c569 uint32_t spread = 0xFFFFFFFF, nspread = 0xFFFFFFFF; in udf_table_new_block() local
601 while (spread) { in udf_table_new_block()
616 if (nspread < spread) { in udf_table_new_block()
617 spread = nspread; in udf_table_new_block()
632 if (ret < 0 || spread == 0xFFFFFFFF) { in udf_table_new_block()
/linux/arch/arm64/boot/dts/rockchip/
H A Drk3588-rock-5b-pcie-srns.dtso4 * mode in the SRNS (Separate Reference Clock No Spread) configuration.
H A Drk3588-rock-5b-pcie-ep.dtso4 * in the SRNS (Separate Reference Clock No Spread) configuration.
/linux/kernel/cgroup/
H A Dcpuset-v1.c207 * Update a task's spread flag if the cpuset's page spread flag is set.
225 * cpuset1_update_tasks_flags - update the page spread flag of cpuset tasks
226 * @cs: the cpuset whose tasks need their page spread flag updated
228 * Iterate through each task of @cs updating its page spread flag. As this
/linux/drivers/gpu/drm/radeon/
H A Datombios.h1905 …UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int.…
1915 …UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int.…
1927 …UCHAR ucSpreadSpectrumType; // Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int…
1938 UCHAR ucSpreadSpectrumType; // Bit[0]: 0-Down Spread,1-Center Spread.
1963 UCHAR ucSpreadSpectrumType; // Bit[0]: 0-Down Spread,1-Center Spread.
2685 … In DP Mode Uniphy Input clock from internal PPLL, otherwise Input clock from external Spread clock
2724 … In DP Mode Uniphy Input clock from internal PPLL, otherwise Input clock from external Spread clock
3636 /****************************Spread Spectrum Info Table Definitions **********************/
3643 …UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =…
3729 …UCHAR ucMaxDownSpread; //Bit0 = 0: No Down spread; Bit0 = 1: 0.5% (Subject to change acc…
[all …]

1234567891011