| /linux/drivers/spi/ |
| H A D | spi-loongson-core.c | 1 // SPDX-License-Identifier: GPL-2.0+
2 // Loongson SPI Support
14 #include <linux/spi/spi.h>
16 #include "spi-loongson.h"
18 static inline void loongson_spi_write_reg(struct loongson_spi *spi, unsigned char reg, in loongson_spi_write_reg() argument
21 writeb(data, spi->base + reg); in loongson_spi_write_reg()
24 static inline char loongson_spi_read_reg(struct loongson_spi *spi, unsigned char reg) in loongson_spi_read_reg() argument
26 return readb(spi->base + reg); in loongson_spi_read_reg()
29 static void loongson_spi_set_cs(struct spi_device *spi, bool en) in loongson_spi_set_cs() argument
32 unsigned char mask = (BIT(4) | BIT(0)) << spi_get_chipselect(spi, 0); in loongson_spi_set_cs()
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| H A D | spi-mux.c | 1 // SPDX-License-Identifier: GPL-2.0
3 // General Purpose SPI multiplexer
10 #include <linux/spi/spi.h>
12 #define SPI_MUX_NO_CS ((unsigned int)-1)
17 * This driver supports a MUX on an SPI bus. This can be useful when you need
21 * The driver will create an additional SPI controller. Devices added under the
22 * mux will be handled as 'chip selects' on this controller.
26 * struct spi_mux_priv - the basic spi_mux structure
27 * @spi: pointer to the device struct attached to the parent
28 * spi controller
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| H A D | spi-microchip-core.c | 1 // SPDX-License-Identifier: (GPL-2.0)
3 * Microchip CoreSPI SPI controller driver
5 * Copyright (c) 2018-2022 Microchip Technology Inc. and its subsidiaries
21 #include <linux/spi/spi.h>
107 u32 clk_gen; /* divider for spi output clock generated by the controller */
116 static inline u32 mchp_corespi_read(struct mchp_corespi *spi, unsigned int reg) in mchp_corespi_read() argument
118 return readl(spi->regs + reg); in mchp_corespi_read()
121 static inline void mchp_corespi_write(struct mchp_corespi *spi, unsigned int reg, u32 val) in mchp_corespi_write() argument
123 writel(val, spi->regs + reg); in mchp_corespi_write()
126 static inline void mchp_corespi_disable(struct mchp_corespi *spi) in mchp_corespi_disable() argument
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| H A D | spi-bitbang.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Polling/bitbanging SPI host controller controller driver utilities
16 #include <linux/spi/spi.h>
17 #include <linux/spi/spi_bitbang.h>
22 /*----------------------------------------------------------------------*/
25 * FIRST PART (OPTIONAL): word-at-a-time spi_transfer support.
26 * Use this for GPIO or shift-register level hardware APIs.
28 * spi_bitbang_cs is in spi_device->controller_state, which is unavailable
30 * used, though maybe they're called from controller-aware code.
32 * chipselect() and friends may use spi_device->controller_data and
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| H A D | spi-imx.c | 1 // SPDX-License-Identifier: GPL-2.0+
2 // Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
11 #include <linux/dma-mapping.h>
25 #include <linux/spi/spi.h>
30 #include <linux/dma/imx-dma.h>
78 int (*prepare_transfer)(struct spi_imx_data *spi_imx, struct spi_device *spi,
98 struct spi_controller *controller; member
138 return d->devtype_data->devtype == IMX27_CSPI; in is_imx27_cspi()
143 return d->devtype_data->devtype == IMX35_CSPI; in is_imx35_cspi()
148 return d->devtype_data->devtype == IMX51_ECSPI; in is_imx51_ecspi()
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| H A D | spi-davinci.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
16 #include <linux/dma-mapping.h>
18 #include <linux/spi/spi.h>
19 #include <linux/spi/spi_bitbang.h>
22 #include <linux/platform_data/spi-davinci.h>
88 /* SPI Controller registers */
103 /* SPI Controller driver's private data. */
136 if (dspi->rx) { in davinci_spi_rx_buf_u8()
137 u8 *rx = dspi->rx; in davinci_spi_rx_buf_u8()
139 dspi->rx = rx; in davinci_spi_rx_buf_u8()
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| H A D | spi-pxa2xx.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
27 #include <linux/spi/spi.h>
30 #include "spi-pxa2xx.h"
81 /* LPSS offset from drv_data->ioaddr */
83 /* Register offsets from drv_data->lpss_base or -1 */
106 .reg_capabilities = -1,
116 .reg_capabilities = -1,
126 .reg_capabilities = -1,
135 .reg_general = -1,
138 .reg_capabilities = -1,
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| H A D | spi-dw-mmio.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Memory-mapped interface driver for DW SPI Core
13 #include <linux/spi/spi.h>
24 #include "spi-dw.h"
61 * bit: |---3-------2-------1-------0
71 * The Designware SPI controller (referred to as master in the documentation)
74 * the SPI boot controller registers. the final chip select is an OR gate
75 * between the Designware SPI controller and the SPI boot controller.
77 static void dw_spi_mscc_set_cs(struct spi_device *spi, bool enable) in dw_spi_mscc_set_cs() argument
79 struct dw_spi *dws = spi_controller_get_devdata(spi->controller); in dw_spi_mscc_set_cs()
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| /linux/Documentation/devicetree/bindings/spi/ |
| H A D | snps,dw-apb-ssi.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/spi/snps,dw-apb-ssi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mark Brown <broonie@kernel.org>
13 - $ref: spi-controller.yaml#
14 - if:
19 - mscc,ocelot-spi
20 - mscc,jaguar2-spi
25 - if:
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| H A D | brcm,spi-bcm-qspi.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/spi/brcm,spi-bcm-qspi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom SPI controller
10 - Kamal Dasu <kdasu.kdev@gmail.com>
11 - Rafał Miłecki <rafal@milecki.pl>
14 The Broadcom SPI controller is a SPI master found on various SOCs, including
15 BRCMSTB (BCM7XXX), Cygnus, NSP and NS2. The Broadcom Master SPI hw IP consists
17 MSPI : SPI master controller can read and write to a SPI slave device
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| H A D | brcm,bcm63xx-spi.yaml | 1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/spi/brcm,bcm63xx-spi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom BCM6348/BCM6358 SPI controller
10 - Jonas Gorski <jonas.gorski@gmail.com>
13 Broadcom "Low Speed" SPI controller found in many older MIPS based Broadband
16 This controller has a limitation that can not keep the chip select line active
17 between the SPI transfers within the same SPI message. This can terminate the
18 transaction to some SPI devices prematurely. The issue can be worked around by
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| H A D | mediatek,spi-mtk-snfi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/mediatek,spi-mtk-snfi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SPI-NAND flash controller for MediaTek ARM SoCs
10 - Chuanhong Guo <gch981213@gmail.com>
13 The Mediatek SPI-NAND flash controller is an extended version of
14 the Mediatek NAND flash controller. It can perform standard SPI
15 instructions with one continuous write and one read for up-to 0xa0
16 bytes. It also supports typical SPI-NAND page cache operations
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| H A D | mediatek,spi-mt65xx.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/mediatek,spi-mt65xx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SPI Bus controller for MediaTek ARM SoCs
10 - Leilk Liu <leilk.liu@mediatek.com>
13 - $ref: /schemas/spi/spi-controller.yaml#
18 - items:
19 - enum:
20 - mediatek,mt7629-spi
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| H A D | mediatek,spi-mtk-nor.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/mediatek,spi-mtk-nor.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Serial NOR flash controller for MediaTek ARM SoCs
10 - Bayi Cheng <bayi.cheng@mediatek.com>
11 - Chuanhong Guo <gch981213@gmail.com>
14 This spi controller support single, dual, or quad mode transfer for
15 SPI NOR flash. There should be only one spi slave device following
16 generic spi bindings. It's not recommended to use this controller
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| H A D | spi-peripheral-props.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-peripheral-props.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Peripheral-specific properties for a SPI bus.
10 Many SPI controllers need to add properties to peripheral devices. They could
11 be common properties like spi-max-frequency, spi-cpha, etc. or they could be
12 controller specific like delay in clock or data lines, etc. These properties
13 need to be defined in the peripheral node because they are per-peripheral and
14 there can be multiple peripherals attached to a controller. All those
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| H A D | spi-rockchip.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-rockchip.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip SPI Controller
10 The Rockchip SPI controller is used to interface with various devices such
11 as flash and display controllers using the SPI communication interface.
14 - $ref: spi-controller.yaml#
17 - Heiko Stuebner <heiko@sntech.de>
23 - const: rockchip,rk3036-spi
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| H A D | adi,axi-spi-engine.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/adi,axi-spi-engine.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Analog Devices AXI SPI Engine Controller
10 The AXI SPI Engine controller is part of the SPI Engine framework[1] and
11 allows memory mapped access to the SPI Engine control bus. This allows it
12 to be used as a general purpose software driven SPI controller as well as
18 - Michael Hennerich <Michael.Hennerich@analog.com>
19 - Nuno Sá <nuno.sa@analog.com>
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| H A D | brcm,bcm63xx-hsspi.yaml | 1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/spi/brcm,bcm63xx-hsspi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom Broadband SoC High Speed SPI controller
10 - William Zhang <william.zhang@broadcom.com>
11 - Kursad Oney <kursad.oney@broadcom.com>
12 - Jonas Gorski <jonas.gorski@gmail.com>
15 Broadcom Broadband SoC supports High Speed SPI master controller since the
17 controller was carried over to recent ARM based chips, such as BCM63138,
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| H A D | fsl,dspi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/fsl,dspi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM Freescale DSPI controller
10 - Frank Li <Frank.Li@nxp.com>
15 - enum:
16 - fsl,vf610-dspi
17 - fsl,ls1021a-v1.0-dspi
18 - fsl,ls1012a-dspi
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| /linux/Documentation/spi/ |
| H A D | spi-summary.rst | 2 Overview of Linux kernel SPI support
5 02-Feb-2012
7 What is SPI?
8 ------------
9 The "Serial Peripheral Interface" (SPI) is a synchronous four wire serial
12 standardization body. SPI uses a host/target configuration.
17 clocking modes through which data is exchanged; mode-0 and mode-3 are most
22 SPI hosts use a fourth "chip select" line to activate a given SPI target
24 in parallel. All SPI targets support chipselects; they are usually active
29 SPI target functions are usually not interoperable between vendors
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| /linux/include/trace/events/ |
| H A D | spi.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 #define TRACE_SYSTEM spi
13 TP_PROTO(struct spi_controller *controller),
15 TP_ARGS(controller),
22 __entry->bus_num = controller->bus_num;
25 TP_printk("spi%d", (int)__entry->bus_num)
31 TP_PROTO(struct spi_controller *controller),
33 TP_ARGS(controller)
39 TP_PROTO(struct spi_controller *controller),
41 TP_ARGS(controller)
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| /linux/include/linux/spi/ |
| H A D | spi.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later
21 #include <uapi/linux/spi/spi.h>
23 /* Max no. of CS supported per spi device */
36 * INTERFACES between SPI master-side drivers and SPI slave protocol handlers,
37 * and SPI infrastructure.
42 * struct spi_statistics - statistics for spi transfers
43 * @syncp: seqcount to protect members in this struct for per-cpu update
44 * on 32-bit systems
46 * @messages: number of spi-messages handled
95 u64_stats_update_begin(&__lstats->syncp); \
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| /linux/drivers/gpu/drm/panel/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
13 depends on OF && SPI
17 Y030XX067A 320x480 3.0" panel as found in the YLM RG-280M, RG-300
18 and RG-99 handheld gaming consoles.
42 depends on SPI
46 as found in the YLM RS-97 handheld gaming console.
49 tristate "Boe BF060Y8M-AJ0 panel"
54 Say Y here if you want to enable support for Boe BF060Y8M-AJ0
66 TFT-LCD modules. The panel has a 1200x1920 resolution and uses
68 the host and has a built-in LED backlight.
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| /linux/Documentation/devicetree/bindings/net/ |
| H A D | asix,ax88796c.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ASIX AX88796C SPI Ethernet Adapter
10 - Łukasz Stelmach <l.stelmach@samsung.com>
13 ASIX AX88796C is an Ethernet controller with a built in PHY. This
14 describes SPI mode of the chip.
16 The node for this driver must be a child node of an SPI controller,
18 ../spi/spi-controller.yaml must be specified.
21 - $ref: ethernet-controller.yaml#
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| /linux/Documentation/devicetree/bindings/interrupt-controller/ |
| H A D | marvell,odmi-controller.txt | 4 Some Marvell SoCs have an On-Die Message Interrupt (ODMI) controller
5 which can be used by on-board peripheral for MSI interrupts.
9 - compatible : The value here should contain:
11 "marvell,ap806-odmi-controller", "marvell,odmi-controller".
13 - interrupt,controller : Identifies the node as an interrupt controller.
15 - msi-controller : Identifies the node as an MSI controller.
17 - marvell,odmi-frames : Number of ODMI frames available. Each frame
20 - reg : List of register definitions, one for each
23 - marvell,spi-base : List of GIC base SPI interrupts, one for each
24 ODMI frame. Those SPI interrupts are 0-based,
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