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/linux/drivers/spi/
H A Dspi-loongson-core.c1 // SPDX-License-Identifier: GPL-2.0+
2 // Loongson SPI Support
15 #include <linux/spi/spi.h>
17 #include "spi-loongson.h"
19 static inline void loongson_spi_write_reg(struct loongson_spi *spi, unsigned char reg, in loongson_spi_write_reg() argument
22 writeb(data, spi->base + reg); in loongson_spi_write_reg()
25 static inline char loongson_spi_read_reg(struct loongson_spi *spi, unsigned char reg) in loongson_spi_read_reg() argument
27 return readb(spi->base + reg); in loongson_spi_read_reg()
30 static void loongson_spi_set_cs(struct spi_device *spi, bool en) in loongson_spi_set_cs() argument
33 unsigned char mask = (BIT(4) | BIT(0)) << spi_get_chipselect(spi, 0); in loongson_spi_set_cs()
[all …]
H A Dspi-stm32.c1 // SPDX-License-Identifier: GPL-2.0
3 // STMicroelectronics STM32 SPI Controller driver
5 // Copyright (C) 2017, STMicroelectronics - All Rights Reserved
12 #include <linux/dma-mapping.h>
23 #include <linux/spi/spi.h>
27 /* STM32F4/7 SPI registers */
83 /* STM32F4 SPI Baud Rate min/max divisor */
87 /* STM32H7 SPI registers */
162 /* STM32MP25 SPI registers bit fields */
176 /* STM32H7 SPI Master Baud Rate min/max divisor */
[all …]
H A Dspi-cadence.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Cadence SPI controller driver (host and target mode)
5 * Copyright (C) 2008 - 2014 Xilinx, Inc.
7 * based on Blackfin On-Chip SPI Driver (spi_bfin5xx.c)
22 #include <linux/spi/spi.h>
25 #define CDNS_SPI_NAME "cdns-spi"
42 * SPI Configuration Register bit Masks
45 * of the SPI controller
63 * SPI Configuration Register - Baud rate and target select
77 * SPI Interrupt Registers bit Masks
[all …]
H A Dspi-bitbang.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Polling/bitbanging SPI host controller controller driver utilities
16 #include <linux/spi/spi.h>
17 #include <linux/spi/spi_bitbang.h>
22 /*----------------------------------------------------------------------*/
25 * FIRST PART (OPTIONAL): word-at-a-time spi_transfer support.
26 * Use this for GPIO or shift-register level hardware APIs.
28 * spi_bitbang_cs is in spi_device->controller_state, which is unavailable
30 * used, though maybe they're called from controller-aware code.
32 * chipselect() and friends may use spi_device->controller_data and
[all …]
H A Dspi-imx.c1 // SPDX-License-Identifier: GPL-2.0+
2 // Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
11 #include <linux/dma-mapping.h>
25 #include <linux/spi/spi.h>
30 #include <linux/dma/imx-dma.h>
78 int (*prepare_transfer)(struct spi_imx_data *spi_imx, struct spi_device *spi,
98 struct spi_controller *controller; member
138 return d->devtype_data->devtype == IMX27_CSPI; in is_imx27_cspi()
143 return d->devtype_data->devtype == IMX35_CSPI; in is_imx35_cspi()
148 return d->devtype_data->devtype == IMX51_ECSPI; in is_imx51_ecspi()
[all …]
H A Dspi-davinci.c1 // SPDX-License-Identifier: GPL-2.0-or-later
16 #include <linux/dma-mapping.h>
18 #include <linux/spi/spi.h>
19 #include <linux/spi/spi_bitbang.h>
22 #include <linux/platform_data/spi-davinci.h>
88 /* SPI Controller registers */
103 /* SPI Controller driver's private data. */
136 if (dspi->rx) { in davinci_spi_rx_buf_u8()
137 u8 *rx = dspi->rx; in davinci_spi_rx_buf_u8()
139 dspi->rx = rx; in davinci_spi_rx_buf_u8()
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H A Dspi-dw-bt1.c1 // SPDX-License-Identifier: GPL-2.0-only
9 // Baikal-T1 DW APB SPI and System Boot SPI driver
24 #include <linux/spi/spi-mem.h>
25 #include <linux/spi/spi.h>
27 #include "spi-dw.h"
52 struct dw_spi_bt1 *dwsbt1 = to_dw_spi_bt1(desc->mem->spi->controller); in dw_spi_bt1_dirmap_create()
54 if (!dwsbt1->map || in dw_spi_bt1_dirmap_create()
55 !dwsbt1->dws.mem_ops.supports_op(desc->mem, &desc->info.op_tmpl)) in dw_spi_bt1_dirmap_create()
56 return -EOPNOTSUPP; in dw_spi_bt1_dirmap_create()
58 if (desc->info.op_tmpl.data.dir != SPI_MEM_DATA_IN) in dw_spi_bt1_dirmap_create()
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/linux/Documentation/devicetree/bindings/spi/
H A Dsnps,dw-apb-ssi.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/spi/snps,dw-apb-ssi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mark Brown <broonie@kernel.org>
13 - $ref: spi-controller.yaml#
14 - if:
19 - mscc,ocelot-spi
20 - mscc,jaguar2-spi
25 - if:
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H A Dbrcm,spi-bcm-qspi.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/spi/brcm,spi-bcm-qspi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom SPI controller
10 - Kamal Dasu <kdasu.kdev@gmail.com>
11 - Rafał Miłecki <rafal@milecki.pl>
14 The Broadcom SPI controller is a SPI master found on various SOCs, including
15 BRCMSTB (BCM7XXX), Cygnus, NSP and NS2. The Broadcom Master SPI hw IP consists
17 MSPI : SPI master controller can read and write to a SPI slave device
[all …]
H A Dbrcm,bcm63xx-spi.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/spi/brcm,bcm63xx-spi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom BCM6348/BCM6358 SPI controller
10 - Jonas Gorski <jonas.gorski@gmail.com>
13 Broadcom "Low Speed" SPI controller found in many older MIPS based Broadband
16 This controller has a limitation that can not keep the chip select line active
17 between the SPI transfers within the same SPI message. This can terminate the
18 transaction to some SPI devices prematurely. The issue can be worked around by
[all …]
H A Dmediatek,spi-mtk-snfi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/mediatek,spi-mtk-snfi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SPI-NAND flash controller for MediaTek ARM SoCs
10 - Chuanhong Guo <gch981213@gmail.com>
13 The Mediatek SPI-NAND flash controller is an extended version of
14 the Mediatek NAND flash controller. It can perform standard SPI
15 instructions with one continuous write and one read for up-to 0xa0
16 bytes. It also supports typical SPI-NAND page cache operations
[all …]
H A Dmediatek,spi-mtk-nor.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/mediatek,spi-mtk-nor.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Serial NOR flash controller for MediaTek ARM SoCs
10 - Bayi Cheng <bayi.cheng@mediatek.com>
11 - Chuanhong Guo <gch981213@gmail.com>
14 This spi controller support single, dual, or quad mode transfer for
15 SPI NOR flash. There should be only one spi slave device following
16 generic spi bindings. It's not recommended to use this controller
[all …]
H A Dmediatek,spi-mt65xx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/mediatek,spi-mt65xx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SPI Bus controller for MediaTek ARM SoCs
10 - Leilk Liu <leilk.liu@mediatek.com>
13 - $ref: /schemas/spi/spi-controller.yaml#
18 - items:
19 - enum:
20 - mediatek,mt7629-spi
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H A Dspi-peripheral-props.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-peripheral-props.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Peripheral-specific properties for a SPI bus.
10 Many SPI controllers need to add properties to peripheral devices. They could
11 be common properties like spi-max-frequency, spi-cs-high, etc. or they could
12 be controller specific like delay in clock or data lines, etc. These
14 per-peripheral and there can be multiple peripherals attached to a
15 controller. All those properties are listed here. The controller specific
[all …]
H A Dbrcm,bcm63xx-hsspi.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/spi/brcm,bcm63xx-hsspi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom Broadband SoC High Speed SPI controller
10 - William Zhang <william.zhang@broadcom.com>
11 - Kursad Oney <kursad.oney@broadcom.com>
12 - Jonas Gorski <jonas.gorski@gmail.com>
15 Broadcom Broadband SoC supports High Speed SPI master controller since the
17 controller was carried over to recent ARM based chips, such as BCM63138,
[all …]
H A Dfsl,dspi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/fsl,dspi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM Freescale DSPI controller
10 - Frank Li <Frank.Li@nxp.com>
15 - enum:
16 - fsl,vf610-dspi
17 - fsl,ls1021a-v1.0-dspi
18 - fsl,ls1012a-dspi
[all …]
H A Dspi-davinci.txt1 Davinci SPI controller device bindings
4 Keystone 2 - https://www.ti.com/lit/ug/sprugp2a/sprugp2a.pdf
5 dm644x - https://www.ti.com/lit/ug/sprue32a/sprue32a.pdf
6 OMAP-L138/da830 - http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf
9 - #address-cells: number of cells required to define a chip select
10 address on the SPI bus. Should be set to 1.
11 - #size-cells: should be zero.
12 - compatible:
13 - "ti,dm6441-spi" for SPI used similar to that on DM644x SoC family
14 - "ti,da830-spi" for SPI used similar to that on DA8xx SoC family
[all …]
H A Damlogic,meson6-spifc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/spi/amlogic,meson6-spifc.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Amlogic Meson SPI Flash Controller
11 - Neil Armstrong <neil.armstrong@linaro.org>
14 - $ref: spi-controller.yaml#
17 The Meson SPIFC is a controller optimized for communication with SPI
18 NOR memories, without DMA support and a 64-byte unified transmit /
24 - amlogic,meson6-spifc # SPI Flash Controller on Meson6 and compatible SoCs
[all …]
/linux/Documentation/spi/
H A Dspi-summary.rst2 Overview of Linux kernel SPI support
5 02-Feb-2012
7 What is SPI?
8 ------------
9 The "Serial Peripheral Interface" (SPI) is a synchronous four wire serial
12 standardization body. SPI uses a host/target configuration.
17 clocking modes through which data is exchanged; mode-0 and mode-3 are most
22 SPI hosts use a fourth "chip select" line to activate a given SPI target
24 in parallel. All SPI targets support chipselects; they are usually active
29 SPI target functions are usually not interoperable between vendors
[all …]
/linux/include/trace/events/
H A Dspi.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 #define TRACE_SYSTEM spi
13 TP_PROTO(struct spi_controller *controller),
15 TP_ARGS(controller),
22 __entry->bus_num = controller->bus_num;
25 TP_printk("spi%d", (int)__entry->bus_num)
31 TP_PROTO(struct spi_controller *controller),
33 TP_ARGS(controller)
39 TP_PROTO(struct spi_controller *controller),
41 TP_ARGS(controller)
[all …]
/linux/include/linux/spi/
H A Dspi.h1 /* SPDX-License-Identifier: GPL-2.0-or-later
21 #include <uapi/linux/spi/spi.h>
23 /* Max no. of CS supported per spi device */
38 * INTERFACES between SPI controller
188 struct spi_controller *controller; global() member
260 spi_dev_get(struct spi_device * spi) spi_dev_get() argument
265 spi_dev_put(struct spi_device * spi) spi_dev_put() argument
272 spi_get_ctldata(const struct spi_device * spi) spi_get_ctldata() argument
277 spi_set_ctldata(struct spi_device * spi,void * state) spi_set_ctldata() argument
284 spi_set_drvdata(struct spi_device * spi,void * data) spi_set_drvdata() argument
289 spi_get_drvdata(const struct spi_device * spi) spi_get_drvdata() argument
294 spi_get_chipselect(const struct spi_device * spi,u8 idx) spi_get_chipselect() argument
299 spi_set_chipselect(struct spi_device * spi,u8 idx,u8 chipselect) spi_set_chipselect() argument
304 spi_get_csgpiod(const struct spi_device * spi,u8 idx) spi_get_csgpiod() argument
309 spi_set_csgpiod(struct spi_device * spi,u8 idx,struct gpio_desc * csgpiod) spi_set_csgpiod() argument
314 spi_is_csgpiod(struct spi_device * spi) spi_is_csgpiod() argument
1157 struct spi_device *spi; global() member
1297 spi_max_message_size(struct spi_device * spi) spi_max_message_size() argument
1307 spi_max_transfer_size(struct spi_device * spi) spi_max_transfer_size() argument
1330 spi_is_bpw_supported(struct spi_device * spi,u32 bpw) spi_is_bpw_supported() argument
1457 spi_sync_transfer(struct spi_device * spi,struct spi_transfer * xfers,unsigned int num_xfers) spi_sync_transfer() argument
1480 spi_write(struct spi_device * spi,const void * buf,size_t len) spi_write() argument
1503 spi_read(struct spi_device * spi,void * buf,size_t len) spi_read() argument
1529 spi_w8r8(struct spi_device * spi,u8 cmd) spi_w8r8() argument
1554 spi_w8r16(struct spi_device * spi,u8 cmd) spi_w8r16() argument
1579 spi_w8r16be(struct spi_device * spi,u8 cmd) spi_w8r16be() argument
[all...]
/linux/drivers/clk/qcom/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
23 tristate "GLYMUR Display Clock Controller"
33 tristate "GLYMUR Global Clock Controller"
37 Support for the global clock controller on GLYMUR devices.
38 Say Y if you want to use peripheral devices such as UART, SPI,
42 tristate "GLYMUR TCSR Clock Controller"
46 Support for the TCSR clock controller on GLYMUR devices.
50 tristate "X1E80100 Camera Clock Controller"
54 Support for the camera clock controller on X1E80100 devices.
58 tristate "X1E80100 Display Clock Controller"
[all …]
/linux/Documentation/devicetree/bindings/net/
H A Dasix,ax88796c.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ASIX AX88796C SPI Ethernet Adapter
10 - Łukasz Stelmach <l.stelmach@samsung.com>
13 ASIX AX88796C is an Ethernet controller with a built in PHY. This
14 describes SPI mode of the chip.
16 The node for this driver must be a child node of an SPI controller,
18 ../spi/spi-controller.yaml must be specified.
21 - $ref: ethernet-controller.yaml#
[all …]
/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dmarvell,odmi-controller.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/marvell,odmi-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Marvell ODMI controller
10 - Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
13 Some Marvell SoCs have an On-Die Message Interrupt (ODMI) controller which can
14 be used by on-board peripherals for MSI interrupts.
18 const: marvell,odmi-controller
23 msi-controller: true
[all …]
/linux/drivers/net/ieee802154/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
7 Say Y here to get to see options for IEEE 802.15.4 Low-Rate
27 depends on SPI
30 Say Y here to enable the at86rf230/231/233/212 SPI 802.15.4 wireless
31 controller.
39 depends on SPI
42 Say Y here to enable the MRF24J20 SPI 802.15.4 wireless
43 controller.
51 depends on SPI
53 Say Y here to enable the CC2520 SPI 802.15.4 wireless
[all …]

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