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Searched +full:spe +full:- +full:pmu (Results 1 – 19 of 19) sorted by relevance

/linux/Documentation/devicetree/bindings/perf/
H A Dspe-pmu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/perf/spe-pmu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARMv8.2 Statistical Profiling Extension (SPE) Performance Monitor Units (PMU)
10 - Will Deacon <will@kernel.org>
14 performance sample data using an in-memory trace buffer.
18 const: arm,statistical-profiling-extension-v1
23 The PPI to signal SPE events. For heterogeneous systems where SPE is only
24 supported on a subset of the CPUs, please consult the arm,gic-v3 binding
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/linux/arch/arm64/kvm/hyp/nvhe/
H A Dswitch.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2015 - ARM Ltd
8 #include <hyp/sysreg-sr.h>
10 #include <linux/arm-smccc.h>
26 #include <asm/debug-monitors.h>
31 /* Non-VHE specific context */
52 ___activate_traps(vcpu, vcpu->arch.hcr_el2); in __activate_traps()
59 struct kvm_cpu_context *ctxt = &vcpu->arch.ctxt; in __activate_traps()
98 write_sysreg_hcr(this_cpu_ptr(&kvm_init_params)->hcr_el2); in __deactivate_traps()
104 /* Save VGICv3 state on non-VHE systems */
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/linux/tools/perf/arch/arm/util/
H A Dpmu.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/coresight-pmu.h>
12 #include "arm-spe.h"
13 #include "hisi-ptt.h"
15 #include "../../../util/pmu.h"
16 #include "../../../util/cs-et
19 perf_pmu__arch_init(struct perf_pmu * pmu) perf_pmu__arch_init() argument
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H A Dauxtrace.c1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/coresight-pmu.h>
16 #include "../../../util/pmu.h"
18 #include "cs-etm.h"
19 #include "arm-spe.h"
20 #include "hisi-ptt.h"
32 *err = -ENOMEM; in find_all_arm_spe_pmus()
40 *err = -ENOMEM; in find_all_arm_spe_pmus()
48 arm_spe_pmus[*nr_spes]->type, in find_all_arm_spe_pmus()
49 arm_spe_pmus[*nr_spes]->name); in find_all_arm_spe_pmus()
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/linux/drivers/perf/
H A Darm_pmu_acpi.c1 // SPDX-License-Identifier: GPL-2.0-only
29 gsi = gicc->performance_interrupt; in arm_pmu_acpi_register_irq()
32 * Per the ACPI spec, the MADT cannot describe a PMU that doesn't in arm_pmu_acpi_register_irq()
41 if (gicc->flags & ACPI_MADT_PERFORMANCE_IRQ_MODE) in arm_pmu_acpi_register_irq()
67 gsi = gicc->performance_interrupt; in arm_pmu_acpi_unregister_irq()
83 if (pdev->num_resources != 1) in arm_acpi_register_pmu_device()
84 return -ENXIO; in arm_acpi_register_pmu_device()
86 if (pdev->resource[0].flags != IORESOURCE_IRQ) in arm_acpi_register_pmu_device()
87 return -ENXIO; in arm_acpi_register_pmu_device()
97 if (gicc->header.length < len) in arm_acpi_register_pmu_device()
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/linux/tools/perf/Documentation/
H A Dperf-mem.txt1 perf-mem(1)
5 ----
6 perf-mem - Profile memory accesses
9 --------
14 -----------
20 and stores are sampled. Use the -t option to limit to loads or stores.
22 Note that on Intel systems the memory latency reported is the use-latency,
26 On Arm64 this uses SPE to sample load and store operations, therefore hardware
27 and kernel support is required. See linkperf:perf-arm-spe[1] for a setup guide.
28 Due to the statistical nature of SPE sampling, not every memory operation will
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H A Dperf.txt5 ----
6 perf - Performance analysis tools for Linux
9 --------
11 'perf' [--version] [--help] [OPTIONS] COMMAND [ARGS]
14 -------
15 -h::
16 --help::
19 -v::
20 --version::
23 -vv::
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/linux/Documentation/trace/coresight/
H A Dcoresight-perf.rst1 .. SPDX-License-Identifier: GPL-2.0
4 CoreSight - Perf
15 perf record -e cs_etm//u testbinary
22 perf report --stdio --dump -i perf.data
26 …ERF_RECORD_AUXTRACE size: 0x11dd0 offset: 0 ref: 0x1b614fc1061b0ad1 idx: 0 tid: 531230 cpu: -1
48 for the support such as libopencsd and libopencsd-dev or download it
60 ------------------------
81 Fine-grained tracing with AUX pause and resume
82 ----------------------------------------------
87 provides AUX pause and resume functionality for fine-grained tracing.
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/linux/arch/arm64/include/asm/
H A Del2_setup.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2012,2013 - ARM Ltd
11 #error Assembly-only header
17 #include <linux/irqchip/arm-gic-v3.h>
23 * Compliant CPUs advertise their VHE-onlyness with
76 * Allow Non-secure EL1 and EL0 to access physical timer and counter.
99 b.eq .Lskip_pmu_\@ // Skip if no PMU present or IMP_DEF
103 csel x2, xzr, x0, eq // all PMU counters from EL1
107 cbz x0, .Lskip_spe_\@ // Skip if SPE not present
109 mrs_s x0, SYS_PMBIDR_EL1 // If SPE available at EL2,
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/linux/arch/arm64/boot/dts/arm/
H A Dfoundation-v8.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 /dts-v1/;
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 model = "Foundation-v8A";
16 compatible = "arm,foundation-aarch64", "arm,vexpress";
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
22 stdout-path = "serial0:115200n8";
33 #address-cells = <2>;
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H A Dmorello.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
3 * Copyright (c) 2020-2024, Arm Limited. All rights reserved.
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 interrupt-parent = <&gic>;
11 #address-cells = <2>;
12 #size-cells = <2>;
14 soc_refclk50mhz: clock-50000000 {
15 compatible = "fixed-clock";
16 #clock-cells = <0>;
17 clock-frequency = <50000000>;
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H A Dfvp-base-revc.dts1 // SPDX-License-Identifier: GPL-2.0
5 * Architecture Envelope Model (AEM) ARMv8-A
11 /dts-v1/;
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 #include "rtsm_ve-motherboard.dtsi"
18 #include "rtsm_ve-motherboard-rs2.dtsi"
22 compatible = "arm,fvp-base-revc", "arm,vexpress";
23 interrupt-parent = <&gic>;
24 #address-cells = <2>;
25 #size-cells = <2>;
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/linux/drivers/dma/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
80 depends on 440SPe || 440SP
97 tristate "Arm DMA-350 support"
102 Enable support for the Arm DMA-350 controller.
120 tristate "Analog Devices AXI-DMAC DMA support"
126 Enable support for the Analog Devices AXI-DMAC peripheral. This DMA
162 tristate "SA-11x0 DMA support"
167 Support the DMA engine found on Intel StrongARM SA-1100 and
168 SA-1110 SoCs. This DMA engine can only be used with on-chip
228 This module can be found on Freescale Vybrid and LS-1 SoCs.
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/linux/drivers/hwtracing/coresight/
H A Dcoresight-trbe.c1 // SPDX-License-Identifier: GPL-2.0
3 * This driver enables Trace Buffer Extension (TRBE) as a per-cpu coresight
4 * sink device could then pair with an appropriate per-cpu coresight source
8 * The AUX buffer handling is inspired from Arm SPE PMU driver.
23 #include "coresight-self-hosted-trace.h"
24 #include "coresight-trbe.h"
26 #define PERF_IDX2OFF(idx, buf) ((idx) % ((buf)->nr_pages << PAGE_SHIFT))
40 * A-Sync, Trace Info, Trace On, Address, Atom.
82 * a trace session. Thus we need a quicker access to per-CPU
91 * - Not duplicating the detection logic
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/linux/arch/arm64/kvm/
H A Dsys_regs.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2012,2013 - ARM Ltd
7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
20 #include <linux/irqchip/arm-gic-v3.h>
25 #include <asm/debug-monitors.h>
74 "sys_reg read to write-only register"); in read_from_write_only()
82 "sys_reg write to read-only register"); in write_to_read_only()
188 * If we have a non-VHE guest and that the sysreg in vcpu_read_sys_reg()
190 * in-memory copy instead. in vcpu_read_sys_reg()
228 * to reverse-translate virtual EL2 system registers for a in vcpu_write_sys_reg()
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/linux/arch/arm64/boot/dts/nvidia/
H A Dtegra194.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra194-clock.h>
3 #include <dt-bindings/gpio/tegra194-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
7 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
8 #include <dt-bindings/power/tegra194-powergate.h>
9 #include <dt-bindings/reset/tegra194-reset.h>
10 #include <dt-bindings/thermal/tegra194-bpmp-thermal.h>
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H A Dtegra234.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/clock/tegra234-clock.h>
4 #include <dt-bindings/gpio/tegra234-gpio.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/mailbox/tegra186-hsp.h>
7 #include <dt-bindings/memory/tegra234-mc.h>
8 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
9 #include <dt-bindings/power/tegra234-powergate.h>
10 #include <dt-bindings/reset/tegra234-reset.h>
11 #include <dt-bindings/thermal/tegra234-bpmp-thermal.h>
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/linux/
H A DMAINTAINERS5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-scsi@vger.kernel.org
88 F: drivers/scsi/3w-*
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/linux/Documentation/admin-guide/
H A Dkernel-parameters.txt16 force -- enable ACPI if default was off
17 on -- enable ACPI but allow fallback to DT [arm64,riscv64]
18 off -- disable ACPI if default was on
19 noirq -- do not use ACPI for IRQ routing
20 strict -- Be less tolerant of platforms that are not
22 rsdt -- prefer RSDT over (default) XSDT
23 copy_dsdt -- copy DSDT to memory
24 nocmcff -- Disable firmware first mode for corrected
28 nospcr -- disable console in ACPI SPCR table as
45 If set to vendor, prefer vendor-specific driver
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