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/linux/drivers/gpu/drm/tegra/
H A Dsor.c33 #include "sor.h"
401 int (*probe)(struct tegra_sor *sor);
402 void (*audio_enable)(struct tegra_sor *sor);
403 void (*audio_disable)(struct tegra_sor *sor);
486 static inline u32 tegra_sor_readl(struct tegra_sor *sor, unsigned int offset) in tegra_sor_readl() argument
488 u32 value = readl(sor->regs + (offset << 2)); in tegra_sor_readl()
490 trace_sor_readl(sor->dev, offset, value); in tegra_sor_readl()
495 static inline void tegra_sor_writel(struct tegra_sor *sor, u32 value, in tegra_sor_writel() argument
498 trace_sor_writel(sor->dev, offset, value); in tegra_sor_writel()
499 writel(value, sor->regs + (offset << 2)); in tegra_sor_writel()
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H A DMakefile21 sor.o \
/linux/Documentation/devicetree/bindings/display/tegra/
H A Dnvidia,tegra124-sor.yaml4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra124-sor.yaml#
7 title: NVIDIA Tegra SOR Output Encoder
14 The Serial Output Resource (SOR) can be used to drive HDMI, LVDS, eDP
19 pattern: "^sor@[0-9a-f]+$"
24 - nvidia,tegra124-sor
25 - nvidia,tegra210-sor
27 - nvidia,tegra186-sor
29 - nvidia,tegra194-sor
32 - const: nvidia,tegra132-sor
33 - const: nvidia,tegra124-sor
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/linux/drivers/gpu/drm/nouveau/nvkm/engine/disp/
H A Dg94.c34 g94_sor_dp_watermark(struct nvkm_ior *sor, int head, u8 watermark) in g94_sor_dp_watermark() argument
36 struct nvkm_device *device = sor->disp->engine.subdev.device; in g94_sor_dp_watermark()
37 const u32 loff = nv50_sor_link(sor); in g94_sor_dp_watermark()
43 g94_sor_dp_activesym(struct nvkm_ior *sor, int head, in g94_sor_dp_activesym() argument
46 struct nvkm_device *device = sor->disp->engine.subdev.device; in g94_sor_dp_activesym()
47 const u32 loff = nv50_sor_link(sor); in g94_sor_dp_activesym()
54 g94_sor_dp_audio_sym(struct nvkm_ior *sor, int head, u16 h, u32 v) in g94_sor_dp_audio_sym() argument
56 struct nvkm_device *device = sor->disp->engine.subdev.device; in g94_sor_dp_audio_sym()
57 const u32 soff = nv50_ior_base(sor); in g94_sor_dp_audio_sym()
64 g94_sor_dp_drive(struct nvkm_ior *sor, int ln, int pc, int dc, int pe, int pu) in g94_sor_dp_drive() argument
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H A Dga102.c33 ga102_sor_dp_links(struct nvkm_ior *sor, struct nvkm_i2c_aux *aux) in ga102_sor_dp_links() argument
35 struct nvkm_device *device = sor->disp->engine.subdev.device; in ga102_sor_dp_links()
36 const u32 soff = nv50_ior_base(sor); in ga102_sor_dp_links()
37 const u32 loff = nv50_sor_link(sor); in ga102_sor_dp_links()
41 switch (sor->dp.bw) { in ga102_sor_dp_links()
55 dpctrl |= ((1 << sor->dp.nr) - 1) << 16; in ga102_sor_dp_links()
56 if (sor->dp.mst) in ga102_sor_dp_links()
58 if (sor->dp.ef) in ga102_sor_dp_links()
86 ga102_sor_clock(struct nvkm_ior *sor) in ga102_sor_clock() argument
88 struct nvkm_device *device = sor->disp->engine.subdev.device; in ga102_sor_clock()
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H A Dgm200.c34 gm200_sor_dp_drive(struct nvkm_ior *sor, int ln, int pc, int dc, int pe, int pu) in gm200_sor_dp_drive() argument
36 struct nvkm_device *device = sor->disp->engine.subdev.device; in gm200_sor_dp_drive()
37 const u32 loff = nv50_sor_link(sor); in gm200_sor_dp_drive()
38 const u32 shift = sor->func->dp->lanes[ln] * 8; in gm200_sor_dp_drive()
103 const u32 sor = ior ? ior->id + 1 : 0; in gm200_sor_route_set() local
107 nvkm_mask(device, 0x612308 + moff, 0x0000001f, link << 4 | sor); in gm200_sor_route_set()
112 nvkm_mask(device, 0x612388 + moff, 0x0000001f, link << 4 | sor); in gm200_sor_route_set()
120 int lnk[2], sor[2], m, s; in gm200_sor_route_get() local
126 sor[s] = (data & 0x0000000f); in gm200_sor_route_get()
127 if (!sor[s]) in gm200_sor_route_get()
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H A Dtu102.c34 tu102_sor_dp_vcpi(struct nvkm_ior *sor, int head, u8 slot, u8 slot_nr, u16 pbn, u16 aligned) in tu102_sor_dp_vcpi() argument
36 struct nvkm_device *device = sor->disp->engine.subdev.device; in tu102_sor_dp_vcpi()
44 tu102_sor_dp_links(struct nvkm_ior *sor, struct nvkm_i2c_aux *aux) in tu102_sor_dp_links() argument
46 struct nvkm_device *device = sor->disp->engine.subdev.device; in tu102_sor_dp_links()
47 const u32 soff = nv50_ior_base(sor); in tu102_sor_dp_links()
48 const u32 loff = nv50_sor_link(sor); in tu102_sor_dp_links()
52 clksor |= sor->dp.bw << 18; in tu102_sor_dp_links()
53 dpctrl |= ((1 << sor->dp.nr) - 1) << 16; in tu102_sor_dp_links()
54 if (sor->dp.mst) in tu102_sor_dp_links()
56 if (sor->dp.ef) in tu102_sor_dp_links()
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H A Dr535.c263 r535_sor_bl_set(struct nvkm_ior *sor, int lvl) in r535_sor_bl_set() argument
265 struct nvkm_disp *disp = sor->disp; in r535_sor_bl_set()
274 ctrl->displayId = BIT(sor->asy.outp->index); in r535_sor_bl_set()
281 r535_sor_bl_get(struct nvkm_ior *sor) in r535_sor_bl_get() argument
283 struct nvkm_disp *disp = sor->disp; in r535_sor_bl_get()
293 ctrl->displayId = BIT(sor->asy.outp->index); in r535_sor_bl_get()
313 r535_sor_hda_eld(struct nvkm_ior *sor, int head, u8 *data, u8 size) in r535_sor_hda_eld() argument
315 struct nvkm_disp *disp = sor->disp; in r535_sor_hda_eld()
326 ctrl->displayId = BIT(sor->asy.outp->index); in r535_sor_hda_eld()
338 r535_sor_hda_hpd(struct nvkm_ior *sor, int head, bool present) in r535_sor_hda_hpd() argument
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H A Dgf119.c85 gf119_sor_dp_watermark(struct nvkm_ior *sor, int head, u8 watermark) in gf119_sor_dp_watermark() argument
87 struct nvkm_device *device = sor->disp->engine.subdev.device; in gf119_sor_dp_watermark()
94 gf119_sor_dp_audio_sym(struct nvkm_ior *sor, int head, u16 h, u32 v) in gf119_sor_dp_audio_sym() argument
96 struct nvkm_device *device = sor->disp->engine.subdev.device; in gf119_sor_dp_audio_sym()
104 gf119_sor_dp_audio(struct nvkm_ior *sor, int head, bool enable) in gf119_sor_dp_audio() argument
106 struct nvkm_device *device = sor->disp->engine.subdev.device; in gf119_sor_dp_audio()
119 gf119_sor_dp_vcpi(struct nvkm_ior *sor, int head, u8 slot, u8 slot_nr, u16 pbn, u16 aligned) in gf119_sor_dp_vcpi() argument
121 struct nvkm_device *device = sor->disp->engine.subdev.device; in gf119_sor_dp_vcpi()
129 gf119_sor_dp_drive(struct nvkm_ior *sor, int ln, int pc, int dc, int pe, int pu) in gf119_sor_dp_drive() argument
131 struct nvkm_device *device = sor->disp->engine.subdev.device; in gf119_sor_dp_drive()
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H A Dgm107.c32 gm107_sor_dp_pattern(struct nvkm_ior *sor, int pattern) in gm107_sor_dp_pattern() argument
34 struct nvkm_device *device = sor->disp->engine.subdev.device; in gm107_sor_dp_pattern()
35 const u32 soff = nv50_ior_base(sor); in gm107_sor_dp_pattern()
49 if (sor->asy.link & 1) in gm107_sor_dp_pattern()
82 return nvkm_ior_new_(&gm107_sor, disp, SOR, id, true); in gm107_sor_new()
96 .sor = { .cnt = gf119_sor_cnt, .new = gm107_sor_new },
H A Dnv50.c193 nv50_sor_clock(struct nvkm_ior *sor) in nv50_sor_clock() argument
195 struct nvkm_device *device = sor->disp->engine.subdev.device; in nv50_sor_clock()
196 const int div = sor->asy.link == 3; in nv50_sor_clock()
197 const u32 soff = nv50_ior_base(sor); in nv50_sor_clock()
212 nv50_sor_power(struct nvkm_ior *sor, bool normal, bool pu, bool data, bool vsync, bool hsync) in nv50_sor_power() argument
214 struct nvkm_device *device = sor->disp->engine.subdev.device; in nv50_sor_power()
215 const u32 soff = nv50_ior_base(sor); in nv50_sor_power()
231 nv50_sor_state(struct nvkm_ior *sor, struct nvkm_ior_state *state) in nv50_sor_state() argument
233 struct nvkm_device *device = sor->disp->engine.subdev.device; in nv50_sor_state()
234 const u32 coff = sor->id * 8 + (state == &sor->arm) * 4; in nv50_sor_state()
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H A Doutp.c69 case DCB_OUTPUT_TMDS : *type = SOR; return TMDS; in nvkm_outp_xlat()
70 case DCB_OUTPUT_LVDS : *type = SOR; return LVDS; in nvkm_outp_xlat()
71 case DCB_OUTPUT_DP : *type = SOR; return DP; in nvkm_outp_xlat()
160 /* Deal with panels requiring identity-mapped SOR assignment. */ in nvkm_outp_acquire_or()
162 ior = nvkm_ior_find(outp->disp, SOR, ffs(outp->info.or) - 1); in nvkm_outp_acquire_or()
196 /* Use a HDA-supporting SOR anyway. */ in nvkm_outp_acquire_or()
318 link = (ior->type == SOR) ? outp->info.sorconf.link : 0; in nvkm_outp_inherit()
H A Dgt215.c68 gt215_sor_dp_audio(struct nvkm_ior *sor, int head, bool enable) in gt215_sor_dp_audio() argument
70 struct nvkm_device *device = sor->disp->engine.subdev.device; in gt215_sor_dp_audio()
71 const u32 soff = nv50_ior_base(sor); in gt215_sor_dp_audio()
236 return nvkm_ior_new_(&gt215_sor, disp, SOR, id, true); in gt215_sor_new()
249 .sor = { .cnt = g94_sor_cnt, .new = gt215_sor_new },
H A Dgv100.c54 gv100_sor_dp_watermark(struct nvkm_ior *sor, int head, u8 watermark) in gv100_sor_dp_watermark() argument
56 struct nvkm_device *device = sor->disp->engine.subdev.device; in gv100_sor_dp_watermark()
63 gv100_sor_dp_audio_sym(struct nvkm_ior *sor, int head, u16 h, u32 v) in gv100_sor_dp_audio_sym() argument
65 struct nvkm_device *device = sor->disp->engine.subdev.device; in gv100_sor_dp_audio_sym()
73 gv100_sor_dp_audio(struct nvkm_ior *sor, int head, bool enable) in gv100_sor_dp_audio() argument
75 struct nvkm_device *device = sor->disp->engine.subdev.device; in gv100_sor_dp_audio()
184 gv100_sor_state(struct nvkm_ior *sor, struct nvkm_ior_state *state) in gv100_sor_state() argument
186 struct nvkm_device *device = sor->disp->engine.subdev.device; in gv100_sor_state()
187 const u32 coff = (state == &sor->arm) * 0x8000 + sor->id * 0x20; in gv100_sor_state()
230 return nvkm_ior_new_(&gv100_sor, disp, SOR, id, hda & BIT(id)); in gv100_sor_new()
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H A Dior.c29 [SOR] = "SOR",
H A Dmcp77.c41 return nvkm_ior_new_(&mcp77_sor, disp, SOR, id, false); in mcp77_sor_new()
54 .sor = { .cnt = g94_sor_cnt, .new = mcp77_sor_new },
H A Dmcp89.c56 return nvkm_ior_new_(&mcp89_sor, disp, SOR, id, true); in mcp89_sor_new()
69 .sor = { .cnt = g94_sor_cnt, .new = mcp89_sor_new },
H A Dgp100.c55 return nvkm_ior_new_(&gp100_sor, disp, SOR, id, hda & BIT(id)); in gp100_sor_new()
68 .sor = { .cnt = gf119_sor_cnt, .new = gp100_sor_new },
H A Dg84.c134 return nvkm_ior_new_(&g84_sor, disp, SOR, id, false); in g84_sor_new()
306 { "SOR", 2, &nv50_disp_core_mthd_sor },
331 .sor = { .cnt = nv50_sor_cnt, .new = g84_sor_new },
H A Dgk104.c127 return nvkm_ior_new_(&gk104_sor, disp, SOR, id, true); in gk104_sor_new()
290 { "SOR", 8, &gf119_disp_core_mthd_sor },
316 .sor = { .cnt = gf119_sor_cnt, .new = gk104_sor_new },
/linux/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/
H A Ddcb.h38 struct sor_conf sor; member
47 struct sor_conf sor; member
52 struct sor_conf sor; member
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/bios/
H A Dmxm.c49 /* These map MXM v2.x digital connection values to the appropriate SOR/link,
94 nvkm_warn(subdev, "unknown sor map v%02x\n", ver); in mxm_sor_map()
107 nvkm_warn(subdev, "missing sor map\n"); in mxm_sor_map()
/linux/Documentation/gpu/
H A Dtegra.rst80 controllers can drive both DSI outputs and both SOR outputs, the third cannot
117 by the versatile SOR output, which supports eDP, DP and HDMI. The SOR is able
/linux/drivers/gpu/drm/nouveau/
H A Dnouveau_led.c60 u32 input_clk = 27e6; /* PDISPLAY.SOR[1].PWM is connected to the crystal */ in nouveau_led_set_brightness()
69 * than PDISPLAY.SOR[1].PWM. in nouveau_led_set_brightness()
/linux/arch/powerpc/sysdev/
H A Dcpm2.c314 u32 dir, par, sor, odr, dat; member
336 setbits32(&iop[port].sor, pin); in cpm2_set_pin()
338 clrbits32(&iop[port].sor, pin); in cpm2_set_pin()

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