| /freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/ |
| H A D | fsl,imx8qxp-dc-intc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/fsl,imx8qxp-dc-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The Display Controller has a built-in interrupt controller with the following
18 Each interrupt can be connected as IRQ (maskable) and/or NMI (non-maskable).
19 Alternatively the un-masked trigger signals for all HW events are provided,
26 - Liu Ying <victor.liu@nxp.com>
30 const: fsl,imx8qxp-dc-intc
38 interrupt-controller: true
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| /freebsd/lib/libpmc/ |
| H A D | pmc.sandybridgeuc.3 | 13 .\" THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS ``AS IS'' AND
22 .\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
45 .Bl -tag -width "Li PMC_CLASS_UCP"
47 Fixed-function counters that count only one hardware event per counter.
49 Programmable counters that may be configured to count one of a defined
59 .%B "Intel(R) 64 and IA-32 Architectures Software Developers Manual"
61 .%N "Order Number: 253669-039US"
68 Not all CPUs in this family implement fixed-function counters.
69 .Ss SANDYBRIDGE UNCORE PROGRAMMABLE PMCS
70 The programmable PMCs support the following capabilities:
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| H A D | pmc.haswelluc.3 | 13 .\" THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS ``AS IS'' AND
22 .\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
45 .Bl -tag -width "Li PMC_CLASS_UCP"
47 Fixed-function counters that count only one hardware event per counter.
49 Programmable counters that may be configured to count one of a defined
59 .%B "Intel(R) 64 and IA-32 Architectures Software Developers Manual"
61 .%N "Order Number: 325462-045US"
68 Not all CPUs in this family implement fixed-function counters.
69 .Ss HASWELL UNCORE PROGRAMMABLE PMCS
70 The programmable PMCs support the following capabilities:
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| H A D | pmc.atomsilvermont.3 | 13 .\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
22 .\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
45 .Bl -tag -width "Li PMC_CLASS_IAP"
47 Fixed-function counters that count only one hardware event per counter.
49 Programmable counters that may be configured to count one of a defined
59 .%B "Intel 64 and IA-32 Intel(R) Architecture Software Developer's Manual"
61 .%N "Order Number 325462-050US"
68 .Ss ATOM SILVERMONT PROGRAMMABLE PMCS
69 The programmable PMCs support the following capabilities:
70 .Bl -column "PMC_CAP_INTERRUPT" "Support"
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| H A D | pmc.3 | 1 .\" Copyright (c) 2003-2008 Joseph Koshy. All rights reserved.
12 .\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
21 .\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
40 The library is implemented using the lower-level facilities offered by
46 using a software abstraction.
50 .Bl -bullet
53 These PMCs measure events in a whole-system manner, i.e., independent
57 Non-privileged process are allowed to allocate system scope PMCs if the
61 is non-zero.
72 .Bl -bullet
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| /freebsd/sys/dev/hwpmc/ |
| H A D | hwpmc_core.h | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
46 * Programmable PMCs.
73 * Fixed-function counters.
86 * 63 - 45 Reserved (do not touch)
88 * 43 - 41 Reserved (do not touch)
90 * 39 - 37 Reserved (do not touch)
92 * 35 - 33 Reserved (do not touch)
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| H A D | hwpmc_uncore.h | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 * Fixed-function PMCs.
43 * Programmable PMCs.
62 * Fixed-function counters.
74 * Programmable counters.
|
| H A D | hwpmc_power8.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
97 * - PMAO=0: clear alerts in power8_pcpu_init()
98 * - FCPC=0, FCP=0: don't freeze counters in problem state in power8_pcpu_init()
99 * - FCECE: Freeze Counters on Enabled Condition or Event in power8_pcpu_init()
100 * - PMC1CE/PMCNCE: PMC1/N Condition Enable in power8_pcpu_init()
110 /* Disable events in PMCs 1-4 */ in power8_pcpu_init()
144 /* Unfreeze counters and re-enable PERF exceptions if requested. */ in power8_resume_pmc()
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| /freebsd/share/man/man4/ |
| H A D | apic.4 | 13 .\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
22 .\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 .Nd Advanced Programmable Interrupt Controller (APIC) driver
36 .Bd -ragged -offset indent
42 .Bl -ohang
57 In addition, they are able to accept and generate inter-processor interrupts
63 Each local APIC includes one 32-bit programmable timer.
65 Event timer provided by the driver supports both one-shot and periodic modes.
66 Because of local APIC nature it is per-CPU.
|
| H A D | attimer.4 | 13 .\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
22 .\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 .Nd i8254 Programmable Interval Timer (AT Timer) driver
36 .Bl -ohang
53 The same value is also available at run-time via the
58 This driver uses i8254 Programmable Interval Timer (AT Timer) hardware
63 platform-dependent frequency.
65 one-shot.
66 The output of each channel has platform-defined wiring: one channel is wired
76 As a result, the one-shot event timer mode is supported only when time counter
|
| H A D | ow_temp.4 | 1 .\"-
2 .\" SPDX-License-Identifier: BSD-2-Clause
12 .\" derived from this software without specific prior written permission.
14 .\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
23 .\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 .Nd Dallas Semiconductor 1-Wire Temperature sensor
37 module supports many of the 1-Wire temperature sensors.
47 .Bl -column "DS18S20" "Econo 1-Wire Digital Thermometer" -compact
48 .It DS1820 Ta 1-Wire Digital Thermometer
49 .It DS18S20 Ta High-Precision 1-Wire Digital Thermometer
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| /freebsd/sys/dev/isci/scil/ |
| H A D | scic_sgpio.h | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause OR GPL-2.0
9 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
11 * This program is free software; you can redistribute it and/or modify
13 * published by the Free Software Foundation.
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
28 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
42 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
52 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| /freebsd/sys/contrib/edk2/Include/Protocol/ |
| H A D | Timer.h | 6 Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
7 SPDX-License-Identifier: BSD-2-Clause-Patent
85 the timer hardware is not programmable, then EFI_UNSUPPORTED is returned.
96 the timer hardware is not programmable, then EFI_UNSUPPORTED is
97 returned. If the timer is programmable, then the timer period
141 registered handler should not be able to distinguish a hardware-generated timer
142 interrupt from a software-generated timer interrupt.
|
| /freebsd/sys/contrib/device-tree/Bindings/sound/ |
| H A D | ti,pcm6240.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2022 - 2024 Texas Instruments Incorporated
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Shenghao Ding <shenghao-ding@ti.com>
24 https://www.ti.com/lit/gpn/pcm3120-q1
25 https://www.ti.com/lit/gpn/pcm3140-q1
26 https://www.ti.com/lit/gpn/pcm5120-q1
27 https://www.ti.com/lit/gpn/pcm6120-q1
28 https://www.ti.com/lit/gpn/pcm6260-q1
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| /freebsd/usr.sbin/service/ |
| H A D | service.8 | 13 .\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
22 .\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
76 .Bl -tag -width F1
143 .Ex -std
150 .Bd -literal -offset indent
156 .Bd -literal -offset indent
162 .Bd -literal -offset indent
167 .Bd -literal -offset indent
172 .Bd -literal -offset indent
173 service -j dns named restart
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| /freebsd/sys/i386/include/ |
| H A D | pmc_mdep.h | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2003-2005,2008 Joseph Koshy
8 * Portions of this software were developed by A. Joseph Koshy under
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
46 * IAP Intel Core/Core2/Atom programmable PMCs.
47 * IAF Intel fixed-function PMCs.
48 * UCP Intel Uncore programmable PMCs.
49 * UCF Intel Uncore fixed-function PMCs.
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| H A D | elan_mmcr.h | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
16 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 * bytes. Ignore fields with the 'pad' prefix - they are only present for
125 /* Programmable Input/Output */
144 /* Software Timer */
150 /* General-Purpose Timers */
191 /* Programmable Interrupt Controller */
|
| /freebsd/sys/contrib/device-tree/Bindings/mfd/ |
| H A D | max77620.txt | 4 -------------------
5 - compatible: Must be one of
9 - reg: I2C device address.
12 -------------------
13 - interrupts: The interrupt on the parent the controller is
15 - interrupt-controller: Marks the device node as an interrupt controller.
16 - #interrupt-cells: is <2> and their usage is compliant to the 2 cells
17 variant of <../interrupt-controller/interrupts.txt>
19 are defined at dt-bindings/mfd/max77620.h.
21 - system-power-controller: Indicates that this PMIC is controlling the
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| /freebsd/sys/arm/freescale/ |
| H A D | fsl_ocotp.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * Access to the Freescale i.MX6 On-Chip One-Time-Programmable Memory
72 if ((root = OF_finddevice("/")) == -1) in fsl_ocotp_devmap()
74 if ((child = fdt_depth_search_compatible(root, "fsl,imx6q-ocotp", 0)) == 0) in fsl_ocotp_devmap()
101 return (bus_read_4(sc->mem_res, off)); in RD4()
119 sc->dev = dev; in ocotp_attach()
123 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, in ocotp_attach()
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| /freebsd/lib/libpmc/pmu-events/arch/x86/emeraldrapids/ |
| H A D | pipeline.json | 16 …y executing divide or square root operations. Accounts for integer and floating-point operations.",
152 "BriefDescription": "Mispredicted non-taken conditional branch instructions retired.",
170 …"BriefDescription": "Miss-predicted near indirect branch instructions retired (excluding returns)",
174 …"PublicDescription": "Counts miss-predicted near indirect branch instructions retired excluding re…
201 …"PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that…
206 …"BriefDescription": "Core clocks when the thread is in the C0.1 light-weight slower wakeup time bu…
209 …"PublicDescription": "Counts core clocks when the thread is in the C0.1 light-weight slower wakeup…
214 …"BriefDescription": "Core clocks when the thread is in the C0.2 light-weight faster wakeup time bu…
217 …"PublicDescription": "Counts core clocks when the thread is in the C0.2 light-weight faster wakeup…
265 …stal clock cycle counts between active hyperthreads, i.e., those in C0 sleep-state. A hyperthread …
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| /freebsd/sys/contrib/device-tree/Bindings/net/ |
| H A D | ti,dp83867.yaml | 1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - $ref: ethernet-controller.yaml#
14 - Andrew Davis <afd@ti.com>
18 transceiver with integrated PMD sublayers to support 10BASE-Te, 100BASE-TX
19 and 1000BASE-T Ethernet protocols.
34 nvmem-cells:
40 nvmem-cell-names:
42 - const: io_impedance_ctrl
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| /freebsd/sys/contrib/device-tree/Bindings/timer/ |
| H A D | jcore,pit.txt | 1 J-Core Programmable Interval Timer and Clocksource
5 - compatible: Must be "jcore,pit".
7 - reg: Memory region(s) for timer/clocksource registers. For SMP,
9 zero-based hardware cpu number.
11 - interrupts: An interrupt to assign for the timer. The actual pit
13 assignment to be programmed by software, but this property is
|
| /freebsd/usr.sbin/acpi/acpidump/ |
| H A D | acpidump.8 | 18 .\" THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
27 .\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
101 .Bl -tag -offset indent -width 12345 -compact
132 Describes all the Advanced Programmable Interrupt Controllers and
133 Intel Streamlined Advanced Programmable Interrupt Controller present
135 .It MCFG PCI Express Memory-mapped Configuration
168 the DSDT consists of free-formatted AML data.
172 .Bl -tag -width indent
207 .Bl -tag -width /dev/mem
213 .Bd -literal -offset indent
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| /freebsd/release/packages/ucl/ |
| H A D | csh-all.ucl | 2 * SPDX-License-Identifier: BSD-3-Clause
16 * may be used to endorse or promote products derived from this software
19 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
38 a command-line editor, programmable word completion, spelling correction,
39 a history mechanism, job control, and a C-lik
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| /freebsd/sys/contrib/device-tree/Bindings/arm/ |
| H A D | arm,coresight-cti.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 ---
5 $id: http://devicetree.org/schemas/arm/arm,coresight-ct
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