1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/pci/mediatek-pcie.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: PCIe controller on MediaTek SoCs 8 9maintainers: 10 - Christian Marangi <ansuelsmth@gmail.com> 11 12properties: 13 compatible: 14 oneOf: 15 - enum: 16 - airoha,an7583-pcie 17 - econet,en7528-pcie 18 - mediatek,mt2712-pcie 19 - mediatek,mt7622-pcie 20 - mediatek,mt7629-pcie 21 - items: 22 - const: airoha,en7523-pcie 23 - const: mediatek,mt7622-pcie 24 25 reg: 26 maxItems: 1 27 28 reg-names: 29 enum: [ port0, port1 ] 30 31 clocks: 32 minItems: 1 33 maxItems: 6 34 35 clock-names: 36 minItems: 1 37 items: 38 - enum: [ sys_ck0, sys_ck1 ] 39 - enum: [ ahb_ck0, ahb_ck1 ] 40 - enum: [ aux_ck0, aux_ck1 ] 41 - enum: [ axi_ck0, axi_ck1 ] 42 - enum: [ obff_ck0, obff_ck1 ] 43 - enum: [ pipe_ck0, pipe_ck1 ] 44 45 resets: 46 maxItems: 1 47 48 reset-names: 49 const: pcie-rst1 50 51 interrupts: 52 maxItems: 1 53 54 interrupt-names: 55 const: pcie_irq 56 57 phys: 58 maxItems: 1 59 60 phy-names: 61 enum: [ pcie-phy0, pcie-phy1 ] 62 63 power-domains: 64 maxItems: 1 65 66 mediatek,pbus-csr: 67 $ref: /schemas/types.yaml#/definitions/phandle-array 68 items: 69 - items: 70 - description: phandle to pbus-csr syscon 71 - description: offset of pbus-csr base address register 72 - description: offset of pbus-csr base address mask register 73 description: 74 Phandle with two arguments to the syscon node used to detect if 75 a given address is accessible on PCIe controller. 76 77 '#interrupt-cells': 78 const: 1 79 80 interrupt-controller: 81 description: Interrupt controller node for handling legacy PCI interrupts. 82 type: object 83 properties: 84 '#address-cells': 85 const: 0 86 '#interrupt-cells': 87 const: 1 88 interrupt-controller: true 89 90 required: 91 - '#address-cells' 92 - '#interrupt-cells' 93 - interrupt-controller 94 95 additionalProperties: false 96 97required: 98 - compatible 99 - reg 100 - reg-names 101 - ranges 102 - clocks 103 - clock-names 104 - '#interrupt-cells' 105 - interrupts 106 - interrupt-names 107 - interrupt-controller 108 109allOf: 110 - $ref: /schemas/pci/pci-host-bridge.yaml# 111 112 - if: 113 properties: 114 compatible: 115 const: airoha,an7583-pcie 116 then: 117 properties: 118 reg-names: 119 const: port1 120 121 clocks: 122 maxItems: 1 123 124 clock-names: 125 const: sys_ck1 126 127 phy-names: 128 const: pcie-phy1 129 130 power-domain: false 131 132 required: 133 - resets 134 - reset-names 135 - phys 136 - phy-names 137 - mediatek,pbus-csr 138 139 - if: 140 properties: 141 compatible: 142 const: mediatek,mt2712-pcie 143 then: 144 properties: 145 clocks: 146 minItems: 2 147 maxItems: 2 148 149 clock-names: 150 minItems: 2 151 maxItems: 2 152 153 reset: false 154 155 reset-names: false 156 157 power-domains: false 158 159 mediatek,pbus-csr: false 160 161 required: 162 - phys 163 - phy-names 164 165 - if: 166 properties: 167 compatible: 168 const: mediatek,mt7622-pcie 169 then: 170 properties: 171 clocks: 172 minItems: 6 173 174 reset: false 175 176 reset-names: false 177 178 phys: false 179 180 phy-names: false 181 182 mediatek,pbus-csr: false 183 184 required: 185 - power-domains 186 187 - if: 188 properties: 189 compatible: 190 const: mediatek,mt7629-pcie 191 then: 192 properties: 193 clocks: 194 minItems: 6 195 196 reset: false 197 198 reset-names: false 199 200 mediatek,pbus-csr: false 201 202 required: 203 - power-domains 204 205 - if: 206 properties: 207 compatible: 208 contains: 209 const: airoha,en7523-pcie 210 then: 211 properties: 212 clocks: 213 maxItems: 1 214 215 clock-names: 216 maxItems: 1 217 218 reset: false 219 220 reset-names: false 221 222 phys: false 223 224 phy-names: false 225 226 power-domain: false 227 228 mediatek,pbus-csr: false 229 230 - if: 231 properties: 232 compatible: 233 contains: 234 const: econet,en7528-pcie 235 then: 236 properties: 237 clocks: 238 maxItems: 1 239 240 clock-names: 241 maxItems: 1 242 243 resets: false 244 245 reset-names: false 246 247 power-domains: false 248 249 mediatek,pbus-csr: false 250 251 required: 252 - phys 253 - phy-names 254 255unevaluatedProperties: false 256 257examples: 258 # MT2712 259 - | 260 #include <dt-bindings/interrupt-controller/arm-gic.h> 261 #include <dt-bindings/interrupt-controller/irq.h> 262 #include <dt-bindings/phy/phy.h> 263 264 soc_1 { 265 #address-cells = <2>; 266 #size-cells = <2>; 267 268 pcie@112ff000 { 269 compatible = "mediatek,mt2712-pcie"; 270 device_type = "pci"; 271 reg = <0 0x112ff000 0 0x1000>; 272 reg-names = "port1"; 273 linux,pci-domain = <1>; 274 #address-cells = <3>; 275 #size-cells = <2>; 276 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 277 interrupt-names = "pcie_irq"; 278 clocks = <&topckgen>, /* CLK_TOP_PE2_MAC_P1_SEL */ 279 <&pericfg>; /* CLK_PERI_PCIE1 */ 280 clock-names = "sys_ck1", "ahb_ck1"; 281 phys = <&u3port1 PHY_TYPE_PCIE>; 282 phy-names = "pcie-phy1"; 283 bus-range = <0x00 0xff>; 284 ranges = <0x82000000 0 0x11400000 0x0 0x11400000 0 0x300000>; 285 286 #interrupt-cells = <1>; 287 interrupt-map-mask = <0 0 0 7>; 288 interrupt-map = <0 0 0 1 &pcie_intc1 0>, 289 <0 0 0 2 &pcie_intc1 1>, 290 <0 0 0 3 &pcie_intc1 2>, 291 <0 0 0 4 &pcie_intc1 3>; 292 pcie_intc1: interrupt-controller { 293 interrupt-controller; 294 #address-cells = <0>; 295 #interrupt-cells = <1>; 296 }; 297 }; 298 299 pcie@11700000 { 300 compatible = "mediatek,mt2712-pcie"; 301 device_type = "pci"; 302 reg = <0 0x11700000 0 0x1000>; 303 reg-names = "port0"; 304 linux,pci-domain = <0>; 305 #address-cells = <3>; 306 #size-cells = <2>; 307 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 308 interrupt-names = "pcie_irq"; 309 clocks = <&topckgen>, /* CLK_TOP_PE2_MAC_P0_SEL */ 310 <&pericfg>; /* CLK_PERI_PCIE0 */ 311 clock-names = "sys_ck0", "ahb_ck0"; 312 phys = <&u3port0 PHY_TYPE_PCIE>; 313 phy-names = "pcie-phy0"; 314 bus-range = <0x00 0xff>; 315 ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>; 316 317 #interrupt-cells = <1>; 318 interrupt-map-mask = <0 0 0 7>; 319 interrupt-map = <0 0 0 1 &pcie_intc0 0>, 320 <0 0 0 2 &pcie_intc0 1>, 321 <0 0 0 3 &pcie_intc0 2>, 322 <0 0 0 4 &pcie_intc0 3>; 323 pcie_intc0: interrupt-controller { 324 interrupt-controller; 325 #address-cells = <0>; 326 #interrupt-cells = <1>; 327 }; 328 }; 329 }; 330 331 # MT7622 332 - | 333 #include <dt-bindings/interrupt-controller/arm-gic.h> 334 #include <dt-bindings/interrupt-controller/irq.h> 335 #include <dt-bindings/power/mt7622-power.h> 336 337 soc_2 { 338 #address-cells = <2>; 339 #size-cells = <2>; 340 341 pcie@1a143000 { 342 compatible = "mediatek,mt7622-pcie"; 343 device_type = "pci"; 344 reg = <0 0x1a143000 0 0x1000>; 345 reg-names = "port0"; 346 linux,pci-domain = <0>; 347 #address-cells = <3>; 348 #size-cells = <2>; 349 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>; 350 interrupt-names = "pcie_irq"; 351 clocks = <&pciesys>, /* CLK_PCIE_P0_MAC_EN */ 352 <&pciesys>, /* CLK_PCIE_P0_AHB_EN */ 353 <&pciesys>, /* CLK_PCIE_P0_AUX_EN */ 354 <&pciesys>, /* CLK_PCIE_P0_AXI_EN */ 355 <&pciesys>, /* CLK_PCIE_P0_OBFF_EN */ 356 <&pciesys>; /* CLK_PCIE_P0_PIPE_EN */ 357 clock-names = "sys_ck0", "ahb_ck0", "aux_ck0", 358 "axi_ck0", "obff_ck0", "pipe_ck0"; 359 360 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>; 361 bus-range = <0x00 0xff>; 362 ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x8000000>; 363 364 #interrupt-cells = <1>; 365 interrupt-map-mask = <0 0 0 7>; 366 interrupt-map = <0 0 0 1 &pcie_intc0_1 0>, 367 <0 0 0 2 &pcie_intc0_1 1>, 368 <0 0 0 3 &pcie_intc0_1 2>, 369 <0 0 0 4 &pcie_intc0_1 3>; 370 pcie_intc0_1: interrupt-controller { 371 interrupt-controller; 372 #address-cells = <0>; 373 #interrupt-cells = <1>; 374 }; 375 }; 376 377 pcie@1a145000 { 378 compatible = "mediatek,mt7622-pcie"; 379 device_type = "pci"; 380 reg = <0 0x1a145000 0 0x1000>; 381 reg-names = "port1"; 382 linux,pci-domain = <1>; 383 #address-cells = <3>; 384 #size-cells = <2>; 385 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>; 386 interrupt-names = "pcie_irq"; 387 clocks = <&pciesys>, /* CLK_PCIE_P1_MAC_EN */ 388 /* designer has connect RC1 with p0_ahb clock */ 389 <&pciesys>, /* CLK_PCIE_P0_AHB_EN */ 390 <&pciesys>, /* CLK_PCIE_P1_AUX_EN */ 391 <&pciesys>, /* CLK_PCIE_P1_AXI_EN */ 392 <&pciesys>, /* CLK_PCIE_P1_OBFF_EN */ 393 <&pciesys>; /* CLK_PCIE_P1_PIPE_EN */ 394 clock-names = "sys_ck1", "ahb_ck1", "aux_ck1", 395 "axi_ck1", "obff_ck1", "pipe_ck1"; 396 397 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>; 398 bus-range = <0x00 0xff>; 399 ranges = <0x82000000 0 0x28000000 0x0 0x28000000 0 0x8000000>; 400 401 #interrupt-cells = <1>; 402 interrupt-map-mask = <0 0 0 7>; 403 interrupt-map = <0 0 0 1 &pcie_intc1_1 0>, 404 <0 0 0 2 &pcie_intc1_1 1>, 405 <0 0 0 3 &pcie_intc1_1 2>, 406 <0 0 0 4 &pcie_intc1_1 3>; 407 pcie_intc1_1: interrupt-controller { 408 interrupt-controller; 409 #address-cells = <0>; 410 #interrupt-cells = <1>; 411 }; 412 }; 413 }; 414 415 # AN7583 416 - | 417 #include <dt-bindings/interrupt-controller/irq.h> 418 #include <dt-bindings/interrupt-controller/arm-gic.h> 419 #include <dt-bindings/clock/en7523-clk.h> 420 421 soc_3 { 422 #address-cells = <2>; 423 #size-cells = <2>; 424 425 pcie@1fa92000 { 426 compatible = "airoha,an7583-pcie"; 427 device_type = "pci"; 428 linux,pci-domain = <1>; 429 #address-cells = <3>; 430 #size-cells = <2>; 431 432 reg = <0x0 0x1fa92000 0x0 0x1670>; 433 reg-names = "port1"; 434 435 clocks = <&scuclk EN7523_CLK_PCIE>; 436 clock-names = "sys_ck1"; 437 438 phys = <&pciephy>; 439 phy-names = "pcie-phy1"; 440 441 ranges = <0x02000000 0 0x24000000 0x0 0x24000000 0 0x4000000>; 442 443 resets = <&scuclk>; /* AN7583_PCIE1_RST */ 444 reset-names = "pcie-rst1"; 445 446 mediatek,pbus-csr = <&pbus_csr 0x8 0xc>; 447 448 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 449 interrupt-names = "pcie_irq"; 450 bus-range = <0x00 0xff>; 451 #interrupt-cells = <1>; 452 interrupt-map-mask = <0 0 0 7>; 453 interrupt-map = <0 0 0 1 &pcie_intc1 0>, 454 <0 0 0 2 &pcie_intc1 1>, 455 <0 0 0 3 &pcie_intc1 2>, 456 <0 0 0 4 &pcie_intc1 3>; 457 458 pcie_intc1_4: interrupt-controller { 459 interrupt-controller; 460 #address-cells = <0>; 461 #interrupt-cells = <1>; 462 }; 463 }; 464 }; 465