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/linux/arch/arm/boot/dts/qcom/
H A Dqcom-ipq4019-ap.dk07.1.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 #include "qcom-ipq4019.dtsi"
5 #include <dt-bindings/input/input.h>
6 #include <dt-bindings/gpio/gpio.h>
9 model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK07.1";
22 stdout-path = "serial0:115200n8";
25 soc {
27 serial_0_pins: serial0-state {
30 bias-disable;
33 i2c_0_pins: i2c-0-state {
[all …]
H A Dqcom-ipq4019-ap.dk04.1.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 #include "qcom-ipq4019.dtsi"
5 #include <dt-bindings/input/input.h>
6 #include <dt-bindings/gpio/gpio.h>
9 model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK04.1";
17 stdout-path = "serial0:115200n8";
25 soc {
27 serial_0_pins: serial0-state {
30 bias-disable;
33 serial_1_pins: serial1-state {
[all …]
H A Dqcom-ipq8064.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mfd/qcom-rpm.h>
6 #include <dt-bindings/clock/qcom,rpmcc.h>
7 #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
8 #include <dt-bindings/clock/qcom,lcc-ipq806x.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/reset/qcom,gcc-ipq806x.h>
11 #include <dt-bindings/soc/qcom,gsbi.h>
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H A Dqcom-msm8974.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/interconnect/qcom,msm8974.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/clock/qcom,gcc-msm8974.h>
7 #include <dt-bindings/clock/qcom,mmcc-msm8974.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/reset/qcom,gcc-msm8974.h>
10 #include <dt-bindings/gpio/gpio.h>
13 #address-cells = <1>;
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/linux/Documentation/devicetree/bindings/pinctrl/
H A Dbitmain,bm1880-pinctrl.txt3 This binding describes the pin controller found in the BM1880 SoC.
7 - compatible: Should be "bitmain,bm1880-pinctrl"
8 - reg: Offset and length of pinctrl space in SCTRL.
10 Please refer to pinctrl-bindings.txt in this directory for details of the
16 pin, a group, or a list of pins or groups. This configuration for BM1880 SoC
17 includes pinmux and various pin configuration parameters, such as pull-up,
24 The following generic properties as defined in pinctrl-bindings.txt are valid
29 - pins: An array of strings, each string containing the name of a pin.
32 MIO0 - MIO111
34 - groups: An array of strings, each string containing the name of a pin
[all …]
H A Dqcom,sc7180-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,sc7180-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <andersson@kernel.org>
11 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
14 Top Level Mode Multiplexer pin controller in Qualcomm SC7180 SoC.
18 const: qcom,sc7180-pinctrl
23 reg-names:
25 - const: west
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/linux/Documentation/devicetree/bindings/arm/tegra/
H A Dnvidia,tegra186-pmc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra186-pmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
16 - nvidia,tegra186-pmc
17 - nvidia,tegra194-pmc
18 - nvidia,tegra234-pmc
24 reg-names:
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/linux/drivers/pinctrl/
H A Dpinctrl-lantiq.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/drivers/pinctrl/pinctrl-lantiq.h
4 * based on linux/drivers/pinctrl/pinctrl-pxa3xx.h
102 /* soc specific callback used to apply muxing */
160 GPIO53, enumerator
H A Dpinctrl-bm1880.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Bitmain BM1880 SoC Pinctrl driver
14 #include <linux/pinctrl/pinconf-generic.h>
20 #include "pinctrl-utils.h"
25 * struct bm1880_pinctrl - driver data
45 * struct bm1880_pctrl_group - pinctrl group
57 * struct bm1880_pinmux_function - a pinmux function
75 * struct bm1880_pinconf_data - pinconf data
488 BM1880_PINCTRL_GRP(gpio53),
776 BM1880_PINMUX_FUNCTION(gpio53, 0),
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H A Dpinctrl-keembay.c1 // SPDX-License-Identifier: GPL-2.0
12 #include <linux/pinctrl/pinconf-generic.h>
61 * struct keembay_mux_desc - Mux properties of each GPIO pin
83 * struct keembay_gpio_irq - Config of each GPIO Interrupt sources
84 * @source: Interrupt source number (0 - 7)
99 * struct keembay_pinctrl - Intel Keembay pinctrl structure
105 * @soc: Pin control configuration data based on SoC
120 const struct keembay_pin_soc *soc; member
131 * struct keembay_pin_soc - Pin control config data based on SoC
616 KEEMBAY_PIN_DESC(53, "GPIO53",
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/linux/arch/arm/boot/dts/broadcom/
H A Dbcm2711.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/soc/bcm2835-pm.h>
10 #address-cells = <2>;
11 #size-cells = <1>;
13 interrupt-parent = <&gicv2>;
16 compatible = "brcm,bcm2711-vc5";
20 clk_27MHz: clk-27M {
21 #clock-cells = <0>;
22 compatible = "fixed-clock";
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/linux/drivers/pinctrl/nomadik/
H A Dpinctrl-ab8505.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) ST-Ericsson SA 2012
5 * Author: Patrice Chotard <patrice.chotard@stericsson.com> for ST-Ericsson.
13 #include "pinctrl-abx500.h"
250 * ALTERNATFUNC register. We need to specifies these values as SOC
338 ALTERNATE_FUNCTIONS(53, 4, UNUSED, UNUSED, 0, 0, 0), /* GPIO53, altA controlled by bit 4 */
349 * GPIO52 to GPIO53
377 abx500_pinctrl_ab8505_init(struct abx500_pinctrl_soc_data **soc) in abx500_pinctrl_ab8505_init() argument
379 *soc = &ab8505_soc; in abx500_pinctrl_ab8505_init()
/linux/arch/arm/mach-pxa/
H A Dmfp-pxa2xx.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 #include <linux/soc/pxa/mfp.h>
8 * the following MFP_xxx bit definitions in mfp.h are re-used for pxa2xx:
19 * bit 23 - Input/Output (PXA2xx specific)
20 * bit 24 - Wakeup Enable(PXA2xx specific)
21 * bit 25 - Keep Output (PXA2xx specific)
107 #define GPIO53_GPIO MFP_CFG_IN(GPIO53, AF0)
H A Dmfp-pxa3xx.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 #include <linux/soc/pxa/mfp.h>
9 /* PXA3xx common MFP configurations - processor specific ones defined
10 * in mfp-pxa300.h and mfp-pxa320.h
62 #define GPIO53_GPIO MFP_CFG(GPIO53, AF0)
/linux/arch/arm64/boot/dts/bitmain/
H A Dbm1880-sophon-edge.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
19 * Line names are taken from the schematic "sophon-edge-schematics"
29 * lines i.e. "[FOO]", the GPIO named lines "GPIO-A" thru "GPIO-L"
34 compatible = "bitmain,sophon-edge", "bitmain,bm1880";
44 stdout-path = "serial0:115200n8";
52 soc {
54 porta: gpio-controller@0 {
55 gpio-line-names =
56 "GPIO-A", /* GPIO0, LSEC pin 23 */
[all …]
/linux/arch/arm/boot/dts/ti/keystone/
H A Dkeystone-k2l.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Keystone 2 Lamarr SoC specific device tree
5 * Copyright (C) 2014-2017 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/reset/ti-syscon.h>
12 model = "Texas Instruments Keystone 2 Lamarr SoC";
15 #address-cells = <1>;
16 #size-cells = <0>;
18 interrupt-parent = <&gic>;
21 compatible = "arm,cortex-a15";
27 compatible = "arm,cortex-a15";
[all …]
/linux/drivers/pinctrl/starfive/
H A Dpinctrl-starfive-jh7110-sys.c1 // SPDX-License-Identifier: GPL-2.0
3 * Pinctrl / GPIO driver for StarFive JH7110 SoC sys controller
23 #include <dt-bindings/pinctrl/starfive,jh7110-pinctrl.h>
26 #include "../pinctrl-utils.h"
29 #include "pinctrl-starfive-jh7110.h"
115 PINCTRL_PIN(PAD_GPIO53, "GPIO53"),
298 if (!fs->offset) in jh7110_set_function()
301 if (func > fs->max) in jh7110_set_function()
304 reg = sfp->base + fs->offset; in jh7110_set_function()
305 func = func << fs->shift; in jh7110_set_function()
[all …]
/linux/drivers/soc/tegra/
H A Dpmc.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/soc/tegra/pmc.c
6 * Copyright (c) 2018-2024, NVIDIA CORPORATION. All rights reserved.
12 #define pr_fmt(fmt) "tegra-pmc: " fmt
14 #include <linux/arm-smccc.h>
16 #include <linux/clk-provider.h>
18 #include <linux/clk/clk-conf.h>
37 #include <linux/pinctrl/pinconf-generic.h>
52 #include <soc/tegra/common.h>
53 #include <soc/tegra/fuse.h>
[all …]
/linux/drivers/pinctrl/berlin/
H A Dpinctrl-as370.c1 // SPDX-License-Identifier: GPL-2.0
276 BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO53 */
326 .compatible = "syna,as370-soc-pinctrl",
335 device_get_match_data(&pdev->dev); in as370_pinctrl_probe()
341 rmconfig = devm_kzalloc(&pdev->dev, sizeof(*rmconfig), GFP_KERNEL); in as370_pinctrl_probe()
343 return -ENOMEM; in as370_pinctrl_probe()
349 rmconfig->reg_bits = 32, in as370_pinctrl_probe()
350 rmconfig->val_bits = 32, in as370_pinctrl_probe()
351 rmconfig->reg_stride = 4, in as370_pinctrl_probe()
352 rmconfig->max_register = resource_size(res); in as370_pinctrl_probe()
[all …]
/linux/arch/arm64/boot/dts/qcom/
H A Dmsm8998.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/clock/qcom,gcc-msm8998.h>
6 #include <dt-bindings/clock/qcom,gpucc-msm8998.h>
7 #include <dt-bindings/clock/qcom,mmcc-msm8998.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/firmware/qcom,scm.h>
10 #include <dt-bindings/power/qcom-rpmpd.h>
11 #include <dt-bindings/gpio/gpio.h>
14 interrupt-parent = <&intc>;
[all …]
H A Dsdm845.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * SDM845 SoC device tree source
8 #include <dt-bindings/clock/qcom,camcc-sdm845.h>
9 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
10 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
11 #include <dt-bindings/clock/qcom,gpucc-sdm845.h>
12 #include <dt-bindings/clock/qcom,lpass-sdm845.h>
13 #include <dt-bindings/clock/qcom,rpmh.h>
14 #include <dt-bindings/clock/qcom,videocc-sdm845.h>
15 #include <dt-bindings/dma/qcom-gpi.h>
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H A Dx1e80100.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,rpmh.h>
7 #include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h>
8 #include <dt-bindings/clock/qcom,x1e80100-dispcc.h>
9 #include <dt-bindings/clock/qcom,x1e80100-gcc.h>
10 #include <dt-bindings/clock/qcom,x1e80100-gpucc.h>
11 #include <dt-bindings/clock/qcom,x1e80100-tcsr.h>
12 #include <dt-bindings/dma/qcom-gpi.h>
13 #include <dt-bindings/interconnect/qcom,icc.h>
14 #include <dt-bindings/interconnect/qcom,x1e80100-rpmh.h>
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