1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * sc7280 SoC device tree source 4 * 5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. 6 */ 7#include <dt-bindings/clock/qcom,camcc-sc7280.h> 8#include <dt-bindings/clock/qcom,dispcc-sc7280.h> 9#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> 10#include <dt-bindings/clock/qcom,gcc-sc7280.h> 11#include <dt-bindings/clock/qcom,gpucc-sc7280.h> 12#include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h> 13#include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h> 14#include <dt-bindings/clock/qcom,rpmh.h> 15#include <dt-bindings/clock/qcom,videocc-sc7280.h> 16#include <dt-bindings/dma/qcom-gpi.h> 17#include <dt-bindings/firmware/qcom,scm.h> 18#include <dt-bindings/gpio/gpio.h> 19#include <dt-bindings/interconnect/qcom,icc.h> 20#include <dt-bindings/interconnect/qcom,osm-l3.h> 21#include <dt-bindings/interconnect/qcom,sc7280.h> 22#include <dt-bindings/interrupt-controller/arm-gic.h> 23#include <dt-bindings/mailbox/qcom-ipcc.h> 24#include <dt-bindings/phy/phy-qcom-qmp.h> 25#include <dt-bindings/power/qcom-rpmpd.h> 26#include <dt-bindings/reset/qcom,sdm845-aoss.h> 27#include <dt-bindings/reset/qcom,sdm845-pdc.h> 28#include <dt-bindings/soc/qcom,apr.h> 29#include <dt-bindings/soc/qcom,rpmh-rsc.h> 30#include <dt-bindings/sound/qcom,lpass.h> 31#include <dt-bindings/sound/qcom,q6afe.h> 32#include <dt-bindings/sound/qcom,q6asm.h> 33#include <dt-bindings/thermal/thermal.h> 34 35/ { 36 interrupt-parent = <&intc>; 37 38 #address-cells = <2>; 39 #size-cells = <2>; 40 41 chosen { }; 42 43 aliases { 44 i2c0 = &i2c0; 45 i2c1 = &i2c1; 46 i2c2 = &i2c2; 47 i2c3 = &i2c3; 48 i2c4 = &i2c4; 49 i2c5 = &i2c5; 50 i2c6 = &i2c6; 51 i2c7 = &i2c7; 52 i2c8 = &i2c8; 53 i2c9 = &i2c9; 54 i2c10 = &i2c10; 55 i2c11 = &i2c11; 56 i2c12 = &i2c12; 57 i2c13 = &i2c13; 58 i2c14 = &i2c14; 59 i2c15 = &i2c15; 60 mmc1 = &sdhc_1; 61 mmc2 = &sdhc_2; 62 spi0 = &spi0; 63 spi1 = &spi1; 64 spi2 = &spi2; 65 spi3 = &spi3; 66 spi4 = &spi4; 67 spi5 = &spi5; 68 spi6 = &spi6; 69 spi7 = &spi7; 70 spi8 = &spi8; 71 spi9 = &spi9; 72 spi10 = &spi10; 73 spi11 = &spi11; 74 spi12 = &spi12; 75 spi13 = &spi13; 76 spi14 = &spi14; 77 spi15 = &spi15; 78 }; 79 80 clocks { 81 xo_board: xo-board { 82 compatible = "fixed-clock"; 83 clock-frequency = <76800000>; 84 #clock-cells = <0>; 85 }; 86 87 sleep_clk: sleep-clk { 88 compatible = "fixed-clock"; 89 clock-frequency = <32764>; 90 #clock-cells = <0>; 91 }; 92 }; 93 94 reserved-memory { 95 #address-cells = <2>; 96 #size-cells = <2>; 97 ranges; 98 99 wlan_ce_mem: wlan-ce@4cd000 { 100 no-map; 101 reg = <0x0 0x004cd000 0x0 0x1000>; 102 }; 103 104 hyp_mem: hyp@80000000 { 105 reg = <0x0 0x80000000 0x0 0x600000>; 106 no-map; 107 }; 108 109 xbl_mem: xbl@80600000 { 110 reg = <0x0 0x80600000 0x0 0x200000>; 111 no-map; 112 }; 113 114 aop_mem: aop@80800000 { 115 reg = <0x0 0x80800000 0x0 0x60000>; 116 no-map; 117 }; 118 119 aop_cmd_db_mem: aop-cmd-db@80860000 { 120 reg = <0x0 0x80860000 0x0 0x20000>; 121 compatible = "qcom,cmd-db"; 122 no-map; 123 }; 124 125 reserved_xbl_uefi_log: xbl-uefi-res@80880000 { 126 reg = <0x0 0x80884000 0x0 0x10000>; 127 no-map; 128 }; 129 130 sec_apps_mem: sec-apps@808ff000 { 131 reg = <0x0 0x808ff000 0x0 0x1000>; 132 no-map; 133 }; 134 135 smem_mem: smem@80900000 { 136 reg = <0x0 0x80900000 0x0 0x200000>; 137 no-map; 138 }; 139 140 cpucp_mem: cpucp@80b00000 { 141 no-map; 142 reg = <0x0 0x80b00000 0x0 0x100000>; 143 }; 144 145 wlan_fw_mem: wlan-fw@80c00000 { 146 reg = <0x0 0x80c00000 0x0 0xc00000>; 147 no-map; 148 }; 149 150 adsp_mem: adsp@86700000 { 151 reg = <0x0 0x86700000 0x0 0x2800000>; 152 no-map; 153 }; 154 155 video_mem: video@8b200000 { 156 reg = <0x0 0x8b200000 0x0 0x500000>; 157 no-map; 158 }; 159 160 cdsp_mem: cdsp@88f00000 { 161 reg = <0x0 0x88f00000 0x0 0x1e00000>; 162 no-map; 163 }; 164 165 ipa_fw_mem: ipa-fw@8b700000 { 166 reg = <0 0x8b700000 0 0x10000>; 167 no-map; 168 }; 169 170 gpu_zap_mem: zap@8b71a000 { 171 reg = <0 0x8b71a000 0 0x2000>; 172 no-map; 173 }; 174 175 mpss_mem: mpss@8b800000 { 176 reg = <0x0 0x8b800000 0x0 0xf600000>; 177 no-map; 178 }; 179 180 wpss_mem: wpss@9ae00000 { 181 reg = <0x0 0x9ae00000 0x0 0x1900000>; 182 no-map; 183 }; 184 185 rmtfs_mem: rmtfs@9c900000 { 186 compatible = "qcom,rmtfs-mem"; 187 reg = <0x0 0x9c900000 0x0 0x280000>; 188 no-map; 189 190 qcom,client-id = <1>; 191 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; 192 }; 193 }; 194 195 cpus { 196 #address-cells = <2>; 197 #size-cells = <0>; 198 199 cpu0: cpu@0 { 200 device_type = "cpu"; 201 compatible = "qcom,kryo"; 202 reg = <0x0 0x0>; 203 clocks = <&cpufreq_hw 0>; 204 enable-method = "psci"; 205 power-domains = <&cpu_pd0>; 206 power-domain-names = "psci"; 207 next-level-cache = <&l2_0>; 208 operating-points-v2 = <&cpu0_opp_table>; 209 capacity-dmips-mhz = <1024>; 210 dynamic-power-coefficient = <100>; 211 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 212 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 213 qcom,freq-domain = <&cpufreq_hw 0>; 214 #cooling-cells = <2>; 215 l2_0: l2-cache { 216 compatible = "cache"; 217 cache-level = <2>; 218 cache-unified; 219 next-level-cache = <&l3_0>; 220 l3_0: l3-cache { 221 compatible = "cache"; 222 cache-level = <3>; 223 cache-unified; 224 }; 225 }; 226 }; 227 228 cpu1: cpu@100 { 229 device_type = "cpu"; 230 compatible = "qcom,kryo"; 231 reg = <0x0 0x100>; 232 clocks = <&cpufreq_hw 0>; 233 enable-method = "psci"; 234 power-domains = <&cpu_pd1>; 235 power-domain-names = "psci"; 236 next-level-cache = <&l2_100>; 237 operating-points-v2 = <&cpu0_opp_table>; 238 capacity-dmips-mhz = <1024>; 239 dynamic-power-coefficient = <100>; 240 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 241 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 242 qcom,freq-domain = <&cpufreq_hw 0>; 243 #cooling-cells = <2>; 244 l2_100: l2-cache { 245 compatible = "cache"; 246 cache-level = <2>; 247 cache-unified; 248 next-level-cache = <&l3_0>; 249 }; 250 }; 251 252 cpu2: cpu@200 { 253 device_type = "cpu"; 254 compatible = "qcom,kryo"; 255 reg = <0x0 0x200>; 256 clocks = <&cpufreq_hw 0>; 257 enable-method = "psci"; 258 power-domains = <&cpu_pd2>; 259 power-domain-names = "psci"; 260 next-level-cache = <&l2_200>; 261 operating-points-v2 = <&cpu0_opp_table>; 262 capacity-dmips-mhz = <1024>; 263 dynamic-power-coefficient = <100>; 264 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 265 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 266 qcom,freq-domain = <&cpufreq_hw 0>; 267 #cooling-cells = <2>; 268 l2_200: l2-cache { 269 compatible = "cache"; 270 cache-level = <2>; 271 cache-unified; 272 next-level-cache = <&l3_0>; 273 }; 274 }; 275 276 cpu3: cpu@300 { 277 device_type = "cpu"; 278 compatible = "qcom,kryo"; 279 reg = <0x0 0x300>; 280 clocks = <&cpufreq_hw 0>; 281 enable-method = "psci"; 282 power-domains = <&cpu_pd3>; 283 power-domain-names = "psci"; 284 next-level-cache = <&l2_300>; 285 operating-points-v2 = <&cpu0_opp_table>; 286 capacity-dmips-mhz = <1024>; 287 dynamic-power-coefficient = <100>; 288 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 289 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 290 qcom,freq-domain = <&cpufreq_hw 0>; 291 #cooling-cells = <2>; 292 l2_300: l2-cache { 293 compatible = "cache"; 294 cache-level = <2>; 295 cache-unified; 296 next-level-cache = <&l3_0>; 297 }; 298 }; 299 300 cpu4: cpu@400 { 301 device_type = "cpu"; 302 compatible = "qcom,kryo"; 303 reg = <0x0 0x400>; 304 clocks = <&cpufreq_hw 1>; 305 enable-method = "psci"; 306 power-domains = <&cpu_pd4>; 307 power-domain-names = "psci"; 308 next-level-cache = <&l2_400>; 309 operating-points-v2 = <&cpu4_opp_table>; 310 capacity-dmips-mhz = <1946>; 311 dynamic-power-coefficient = <520>; 312 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 313 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 314 qcom,freq-domain = <&cpufreq_hw 1>; 315 #cooling-cells = <2>; 316 l2_400: l2-cache { 317 compatible = "cache"; 318 cache-level = <2>; 319 cache-unified; 320 next-level-cache = <&l3_0>; 321 }; 322 }; 323 324 cpu5: cpu@500 { 325 device_type = "cpu"; 326 compatible = "qcom,kryo"; 327 reg = <0x0 0x500>; 328 clocks = <&cpufreq_hw 1>; 329 enable-method = "psci"; 330 power-domains = <&cpu_pd5>; 331 power-domain-names = "psci"; 332 next-level-cache = <&l2_500>; 333 operating-points-v2 = <&cpu4_opp_table>; 334 capacity-dmips-mhz = <1946>; 335 dynamic-power-coefficient = <520>; 336 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 337 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 338 qcom,freq-domain = <&cpufreq_hw 1>; 339 #cooling-cells = <2>; 340 l2_500: l2-cache { 341 compatible = "cache"; 342 cache-level = <2>; 343 cache-unified; 344 next-level-cache = <&l3_0>; 345 }; 346 }; 347 348 cpu6: cpu@600 { 349 device_type = "cpu"; 350 compatible = "qcom,kryo"; 351 reg = <0x0 0x600>; 352 clocks = <&cpufreq_hw 1>; 353 enable-method = "psci"; 354 power-domains = <&cpu_pd6>; 355 power-domain-names = "psci"; 356 next-level-cache = <&l2_600>; 357 operating-points-v2 = <&cpu4_opp_table>; 358 capacity-dmips-mhz = <1946>; 359 dynamic-power-coefficient = <520>; 360 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 361 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 362 qcom,freq-domain = <&cpufreq_hw 1>; 363 #cooling-cells = <2>; 364 l2_600: l2-cache { 365 compatible = "cache"; 366 cache-level = <2>; 367 cache-unified; 368 next-level-cache = <&l3_0>; 369 }; 370 }; 371 372 cpu7: cpu@700 { 373 device_type = "cpu"; 374 compatible = "qcom,kryo"; 375 reg = <0x0 0x700>; 376 clocks = <&cpufreq_hw 2>; 377 enable-method = "psci"; 378 power-domains = <&cpu_pd7>; 379 power-domain-names = "psci"; 380 next-level-cache = <&l2_700>; 381 operating-points-v2 = <&cpu7_opp_table>; 382 capacity-dmips-mhz = <1985>; 383 dynamic-power-coefficient = <552>; 384 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 385 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 386 qcom,freq-domain = <&cpufreq_hw 2>; 387 #cooling-cells = <2>; 388 l2_700: l2-cache { 389 compatible = "cache"; 390 cache-level = <2>; 391 cache-unified; 392 next-level-cache = <&l3_0>; 393 }; 394 }; 395 396 cpu-map { 397 cluster0 { 398 core0 { 399 cpu = <&cpu0>; 400 }; 401 402 core1 { 403 cpu = <&cpu1>; 404 }; 405 406 core2 { 407 cpu = <&cpu2>; 408 }; 409 410 core3 { 411 cpu = <&cpu3>; 412 }; 413 414 core4 { 415 cpu = <&cpu4>; 416 }; 417 418 core5 { 419 cpu = <&cpu5>; 420 }; 421 422 core6 { 423 cpu = <&cpu6>; 424 }; 425 426 core7 { 427 cpu = <&cpu7>; 428 }; 429 }; 430 }; 431 432 idle-states { 433 entry-method = "psci"; 434 435 little_cpu_sleep_0: cpu-sleep-0-0 { 436 compatible = "arm,idle-state"; 437 idle-state-name = "little-power-down"; 438 arm,psci-suspend-param = <0x40000003>; 439 entry-latency-us = <549>; 440 exit-latency-us = <901>; 441 min-residency-us = <1774>; 442 local-timer-stop; 443 }; 444 445 little_cpu_sleep_1: cpu-sleep-0-1 { 446 compatible = "arm,idle-state"; 447 idle-state-name = "little-rail-power-down"; 448 arm,psci-suspend-param = <0x40000004>; 449 entry-latency-us = <702>; 450 exit-latency-us = <915>; 451 min-residency-us = <4001>; 452 local-timer-stop; 453 }; 454 455 big_cpu_sleep_0: cpu-sleep-1-0 { 456 compatible = "arm,idle-state"; 457 idle-state-name = "big-power-down"; 458 arm,psci-suspend-param = <0x40000003>; 459 entry-latency-us = <523>; 460 exit-latency-us = <1244>; 461 min-residency-us = <2207>; 462 local-timer-stop; 463 }; 464 465 big_cpu_sleep_1: cpu-sleep-1-1 { 466 compatible = "arm,idle-state"; 467 idle-state-name = "big-rail-power-down"; 468 arm,psci-suspend-param = <0x40000004>; 469 entry-latency-us = <526>; 470 exit-latency-us = <1854>; 471 min-residency-us = <5555>; 472 local-timer-stop; 473 }; 474 }; 475 476 domain_idle_states: domain-idle-states { 477 cluster_sleep_apss_off: cluster-sleep-0 { 478 compatible = "domain-idle-state"; 479 arm,psci-suspend-param = <0x41000044>; 480 entry-latency-us = <2752>; 481 exit-latency-us = <3048>; 482 min-residency-us = <6118>; 483 }; 484 485 cluster_sleep_cx_ret: cluster-sleep-1 { 486 compatible = "domain-idle-state"; 487 arm,psci-suspend-param = <0x41001344>; 488 entry-latency-us = <3263>; 489 exit-latency-us = <4562>; 490 min-residency-us = <8467>; 491 }; 492 493 cluster_sleep_llcc_off: cluster-sleep-2 { 494 compatible = "domain-idle-state"; 495 arm,psci-suspend-param = <0x4100b344>; 496 entry-latency-us = <3638>; 497 exit-latency-us = <6562>; 498 min-residency-us = <9826>; 499 }; 500 }; 501 }; 502 503 cpu0_opp_table: opp-table-cpu0 { 504 compatible = "operating-points-v2"; 505 opp-shared; 506 507 cpu0_opp_300mhz: opp-300000000 { 508 opp-hz = /bits/ 64 <300000000>; 509 opp-peak-kBps = <800000 9600000>; 510 }; 511 512 cpu0_opp_691mhz: opp-691200000 { 513 opp-hz = /bits/ 64 <691200000>; 514 opp-peak-kBps = <800000 17817600>; 515 }; 516 517 cpu0_opp_806mhz: opp-806400000 { 518 opp-hz = /bits/ 64 <806400000>; 519 opp-peak-kBps = <800000 20889600>; 520 }; 521 522 cpu0_opp_941mhz: opp-940800000 { 523 opp-hz = /bits/ 64 <940800000>; 524 opp-peak-kBps = <1804000 24576000>; 525 }; 526 527 cpu0_opp_1152mhz: opp-1152000000 { 528 opp-hz = /bits/ 64 <1152000000>; 529 opp-peak-kBps = <2188000 27033600>; 530 }; 531 532 cpu0_opp_1325mhz: opp-1324800000 { 533 opp-hz = /bits/ 64 <1324800000>; 534 opp-peak-kBps = <2188000 33792000>; 535 }; 536 537 cpu0_opp_1517mhz: opp-1516800000 { 538 opp-hz = /bits/ 64 <1516800000>; 539 opp-peak-kBps = <3072000 38092800>; 540 }; 541 542 cpu0_opp_1651mhz: opp-1651200000 { 543 opp-hz = /bits/ 64 <1651200000>; 544 opp-peak-kBps = <3072000 41779200>; 545 }; 546 547 cpu0_opp_1805mhz: opp-1804800000 { 548 opp-hz = /bits/ 64 <1804800000>; 549 opp-peak-kBps = <4068000 48537600>; 550 }; 551 552 cpu0_opp_1958mhz: opp-1958400000 { 553 opp-hz = /bits/ 64 <1958400000>; 554 opp-peak-kBps = <4068000 48537600>; 555 }; 556 557 cpu0_opp_2016mhz: opp-2016000000 { 558 opp-hz = /bits/ 64 <2016000000>; 559 opp-peak-kBps = <6220000 48537600>; 560 }; 561 }; 562 563 cpu4_opp_table: opp-table-cpu4 { 564 compatible = "operating-points-v2"; 565 opp-shared; 566 567 cpu4_opp_691mhz: opp-691200000 { 568 opp-hz = /bits/ 64 <691200000>; 569 opp-peak-kBps = <1804000 9600000>; 570 }; 571 572 cpu4_opp_941mhz: opp-940800000 { 573 opp-hz = /bits/ 64 <940800000>; 574 opp-peak-kBps = <2188000 17817600>; 575 }; 576 577 cpu4_opp_1229mhz: opp-1228800000 { 578 opp-hz = /bits/ 64 <1228800000>; 579 opp-peak-kBps = <4068000 24576000>; 580 }; 581 582 cpu4_opp_1344mhz: opp-1344000000 { 583 opp-hz = /bits/ 64 <1344000000>; 584 opp-peak-kBps = <4068000 24576000>; 585 }; 586 587 cpu4_opp_1517mhz: opp-1516800000 { 588 opp-hz = /bits/ 64 <1516800000>; 589 opp-peak-kBps = <4068000 24576000>; 590 }; 591 592 cpu4_opp_1651mhz: opp-1651200000 { 593 opp-hz = /bits/ 64 <1651200000>; 594 opp-peak-kBps = <6220000 38092800>; 595 }; 596 597 cpu4_opp_1901mhz: opp-1900800000 { 598 opp-hz = /bits/ 64 <1900800000>; 599 opp-peak-kBps = <6220000 44851200>; 600 }; 601 602 cpu4_opp_2054mhz: opp-2054400000 { 603 opp-hz = /bits/ 64 <2054400000>; 604 opp-peak-kBps = <6220000 44851200>; 605 }; 606 607 cpu4_opp_2112mhz: opp-2112000000 { 608 opp-hz = /bits/ 64 <2112000000>; 609 opp-peak-kBps = <6220000 44851200>; 610 }; 611 612 cpu4_opp_2131mhz: opp-2131200000 { 613 opp-hz = /bits/ 64 <2131200000>; 614 opp-peak-kBps = <6220000 44851200>; 615 }; 616 617 cpu4_opp_2208mhz: opp-2208000000 { 618 opp-hz = /bits/ 64 <2208000000>; 619 opp-peak-kBps = <6220000 44851200>; 620 }; 621 622 cpu4_opp_2400mhz: opp-2400000000 { 623 opp-hz = /bits/ 64 <2400000000>; 624 opp-peak-kBps = <12787200 48537600>; 625 }; 626 627 cpu4_opp_2611mhz: opp-2611200000 { 628 opp-hz = /bits/ 64 <2611200000>; 629 opp-peak-kBps = <12787200 48537600>; 630 }; 631 }; 632 633 cpu7_opp_table: opp-table-cpu7 { 634 compatible = "operating-points-v2"; 635 opp-shared; 636 637 cpu7_opp_806mhz: opp-806400000 { 638 opp-hz = /bits/ 64 <806400000>; 639 opp-peak-kBps = <1804000 9600000>; 640 }; 641 642 cpu7_opp_1056mhz: opp-1056000000 { 643 opp-hz = /bits/ 64 <1056000000>; 644 opp-peak-kBps = <2188000 17817600>; 645 }; 646 647 cpu7_opp_1325mhz: opp-1324800000 { 648 opp-hz = /bits/ 64 <1324800000>; 649 opp-peak-kBps = <4068000 24576000>; 650 }; 651 652 cpu7_opp_1517mhz: opp-1516800000 { 653 opp-hz = /bits/ 64 <1516800000>; 654 opp-peak-kBps = <4068000 24576000>; 655 }; 656 657 cpu7_opp_1766mhz: opp-1766400000 { 658 opp-hz = /bits/ 64 <1766400000>; 659 opp-peak-kBps = <6220000 38092800>; 660 }; 661 662 cpu7_opp_1862mhz: opp-1862400000 { 663 opp-hz = /bits/ 64 <1862400000>; 664 opp-peak-kBps = <6220000 38092800>; 665 }; 666 667 cpu7_opp_2035mhz: opp-2035200000 { 668 opp-hz = /bits/ 64 <2035200000>; 669 opp-peak-kBps = <6220000 38092800>; 670 }; 671 672 cpu7_opp_2112mhz: opp-2112000000 { 673 opp-hz = /bits/ 64 <2112000000>; 674 opp-peak-kBps = <6220000 44851200>; 675 }; 676 677 cpu7_opp_2208mhz: opp-2208000000 { 678 opp-hz = /bits/ 64 <2208000000>; 679 opp-peak-kBps = <6220000 44851200>; 680 }; 681 682 cpu7_opp_2381mhz: opp-2380800000 { 683 opp-hz = /bits/ 64 <2380800000>; 684 opp-peak-kBps = <6832000 44851200>; 685 }; 686 687 cpu7_opp_2400mhz: opp-2400000000 { 688 opp-hz = /bits/ 64 <2400000000>; 689 opp-peak-kBps = <12787200 48537600>; 690 }; 691 692 cpu7_opp_2515mhz: opp-2515200000 { 693 opp-hz = /bits/ 64 <2515200000>; 694 opp-peak-kBps = <12787200 48537600>; 695 }; 696 697 cpu7_opp_2707mhz: opp-2707200000 { 698 opp-hz = /bits/ 64 <2707200000>; 699 opp-peak-kBps = <12787200 48537600>; 700 }; 701 702 cpu7_opp_3014mhz: opp-3014400000 { 703 opp-hz = /bits/ 64 <3014400000>; 704 opp-peak-kBps = <12787200 48537600>; 705 }; 706 }; 707 708 memory@80000000 { 709 device_type = "memory"; 710 /* We expect the bootloader to fill in the size */ 711 reg = <0 0x80000000 0 0>; 712 }; 713 714 firmware { 715 scm: scm { 716 compatible = "qcom,scm-sc7280", "qcom,scm"; 717 qcom,dload-mode = <&tcsr_2 0x13000>; 718 }; 719 }; 720 721 clk_virt: interconnect { 722 compatible = "qcom,sc7280-clk-virt"; 723 #interconnect-cells = <2>; 724 qcom,bcm-voters = <&apps_bcm_voter>; 725 }; 726 727 smem { 728 compatible = "qcom,smem"; 729 memory-region = <&smem_mem>; 730 hwlocks = <&tcsr_mutex 3>; 731 }; 732 733 smp2p-adsp { 734 compatible = "qcom,smp2p"; 735 qcom,smem = <443>, <429>; 736 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 737 IPCC_MPROC_SIGNAL_SMP2P 738 IRQ_TYPE_EDGE_RISING>; 739 mboxes = <&ipcc IPCC_CLIENT_LPASS 740 IPCC_MPROC_SIGNAL_SMP2P>; 741 742 qcom,local-pid = <0>; 743 qcom,remote-pid = <2>; 744 745 adsp_smp2p_out: master-kernel { 746 qcom,entry-name = "master-kernel"; 747 #qcom,smem-state-cells = <1>; 748 }; 749 750 adsp_smp2p_in: slave-kernel { 751 qcom,entry-name = "slave-kernel"; 752 interrupt-controller; 753 #interrupt-cells = <2>; 754 }; 755 }; 756 757 smp2p-cdsp { 758 compatible = "qcom,smp2p"; 759 qcom,smem = <94>, <432>; 760 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 761 IPCC_MPROC_SIGNAL_SMP2P 762 IRQ_TYPE_EDGE_RISING>; 763 mboxes = <&ipcc IPCC_CLIENT_CDSP 764 IPCC_MPROC_SIGNAL_SMP2P>; 765 766 qcom,local-pid = <0>; 767 qcom,remote-pid = <5>; 768 769 cdsp_smp2p_out: master-kernel { 770 qcom,entry-name = "master-kernel"; 771 #qcom,smem-state-cells = <1>; 772 }; 773 774 cdsp_smp2p_in: slave-kernel { 775 qcom,entry-name = "slave-kernel"; 776 interrupt-controller; 777 #interrupt-cells = <2>; 778 }; 779 }; 780 781 smp2p-mpss { 782 compatible = "qcom,smp2p"; 783 qcom,smem = <435>, <428>; 784 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 785 IPCC_MPROC_SIGNAL_SMP2P 786 IRQ_TYPE_EDGE_RISING>; 787 mboxes = <&ipcc IPCC_CLIENT_MPSS 788 IPCC_MPROC_SIGNAL_SMP2P>; 789 790 qcom,local-pid = <0>; 791 qcom,remote-pid = <1>; 792 793 modem_smp2p_out: master-kernel { 794 qcom,entry-name = "master-kernel"; 795 #qcom,smem-state-cells = <1>; 796 }; 797 798 modem_smp2p_in: slave-kernel { 799 qcom,entry-name = "slave-kernel"; 800 interrupt-controller; 801 #interrupt-cells = <2>; 802 }; 803 804 ipa_smp2p_out: ipa-ap-to-modem { 805 qcom,entry-name = "ipa"; 806 #qcom,smem-state-cells = <1>; 807 }; 808 809 ipa_smp2p_in: ipa-modem-to-ap { 810 qcom,entry-name = "ipa"; 811 interrupt-controller; 812 #interrupt-cells = <2>; 813 }; 814 }; 815 816 smp2p-wpss { 817 compatible = "qcom,smp2p"; 818 qcom,smem = <617>, <616>; 819 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 820 IPCC_MPROC_SIGNAL_SMP2P 821 IRQ_TYPE_EDGE_RISING>; 822 mboxes = <&ipcc IPCC_CLIENT_WPSS 823 IPCC_MPROC_SIGNAL_SMP2P>; 824 825 qcom,local-pid = <0>; 826 qcom,remote-pid = <13>; 827 828 wpss_smp2p_out: master-kernel { 829 qcom,entry-name = "master-kernel"; 830 #qcom,smem-state-cells = <1>; 831 }; 832 833 wpss_smp2p_in: slave-kernel { 834 qcom,entry-name = "slave-kernel"; 835 interrupt-controller; 836 #interrupt-cells = <2>; 837 }; 838 839 wlan_smp2p_out: wlan-ap-to-wpss { 840 qcom,entry-name = "wlan"; 841 #qcom,smem-state-cells = <1>; 842 }; 843 844 wlan_smp2p_in: wlan-wpss-to-ap { 845 qcom,entry-name = "wlan"; 846 interrupt-controller; 847 #interrupt-cells = <2>; 848 }; 849 }; 850 851 pmu-a55 { 852 compatible = "arm,cortex-a55-pmu"; 853 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 854 }; 855 856 pmu-a78 { 857 compatible = "arm,cortex-a78-pmu"; 858 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 859 }; 860 861 psci { 862 compatible = "arm,psci-1.0"; 863 method = "smc"; 864 865 cpu_pd0: power-domain-cpu0 { 866 #power-domain-cells = <0>; 867 power-domains = <&cluster_pd>; 868 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 869 }; 870 871 cpu_pd1: power-domain-cpu1 { 872 #power-domain-cells = <0>; 873 power-domains = <&cluster_pd>; 874 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 875 }; 876 877 cpu_pd2: power-domain-cpu2 { 878 #power-domain-cells = <0>; 879 power-domains = <&cluster_pd>; 880 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 881 }; 882 883 cpu_pd3: power-domain-cpu3 { 884 #power-domain-cells = <0>; 885 power-domains = <&cluster_pd>; 886 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 887 }; 888 889 cpu_pd4: power-domain-cpu4 { 890 #power-domain-cells = <0>; 891 power-domains = <&cluster_pd>; 892 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 893 }; 894 895 cpu_pd5: power-domain-cpu5 { 896 #power-domain-cells = <0>; 897 power-domains = <&cluster_pd>; 898 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 899 }; 900 901 cpu_pd6: power-domain-cpu6 { 902 #power-domain-cells = <0>; 903 power-domains = <&cluster_pd>; 904 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 905 }; 906 907 cpu_pd7: power-domain-cpu7 { 908 #power-domain-cells = <0>; 909 power-domains = <&cluster_pd>; 910 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 911 }; 912 913 cluster_pd: power-domain-cluster { 914 #power-domain-cells = <0>; 915 domain-idle-states = <&cluster_sleep_apss_off &cluster_sleep_cx_ret &cluster_sleep_llcc_off>; 916 }; 917 }; 918 919 qspi_opp_table: opp-table-qspi { 920 compatible = "operating-points-v2"; 921 922 opp-75000000 { 923 opp-hz = /bits/ 64 <75000000>; 924 required-opps = <&rpmhpd_opp_low_svs>; 925 }; 926 927 opp-150000000 { 928 opp-hz = /bits/ 64 <150000000>; 929 required-opps = <&rpmhpd_opp_svs>; 930 }; 931 932 opp-200000000 { 933 opp-hz = /bits/ 64 <200000000>; 934 required-opps = <&rpmhpd_opp_svs_l1>; 935 }; 936 937 opp-300000000 { 938 opp-hz = /bits/ 64 <300000000>; 939 required-opps = <&rpmhpd_opp_nom>; 940 }; 941 }; 942 943 qup_opp_table: opp-table-qup { 944 compatible = "operating-points-v2"; 945 946 opp-75000000 { 947 opp-hz = /bits/ 64 <75000000>; 948 required-opps = <&rpmhpd_opp_low_svs>; 949 }; 950 951 opp-100000000 { 952 opp-hz = /bits/ 64 <100000000>; 953 required-opps = <&rpmhpd_opp_svs>; 954 }; 955 956 opp-128000000 { 957 opp-hz = /bits/ 64 <128000000>; 958 required-opps = <&rpmhpd_opp_nom>; 959 }; 960 }; 961 962 soc: soc@0 { 963 #address-cells = <2>; 964 #size-cells = <2>; 965 ranges = <0 0 0 0 0x10 0>; 966 dma-ranges = <0 0 0 0 0x10 0>; 967 compatible = "simple-bus"; 968 969 gcc: clock-controller@100000 { 970 compatible = "qcom,gcc-sc7280"; 971 reg = <0 0x00100000 0 0x1f0000>; 972 clocks = <&rpmhcc RPMH_CXO_CLK>, 973 <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, 974 <0>, <&pcie1_phy>, 975 <&ufs_mem_phy 0>, <&ufs_mem_phy 1>, <&ufs_mem_phy 2>, 976 <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; 977 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", 978 "pcie_0_pipe_clk", "pcie_1_pipe_clk", 979 "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk", 980 "ufs_phy_tx_symbol_0_clk", 981 "usb3_phy_wrapper_gcc_usb30_pipe_clk"; 982 #clock-cells = <1>; 983 #reset-cells = <1>; 984 #power-domain-cells = <1>; 985 power-domains = <&rpmhpd SC7280_CX>; 986 }; 987 988 ipcc: mailbox@408000 { 989 compatible = "qcom,sc7280-ipcc", "qcom,ipcc"; 990 reg = <0 0x00408000 0 0x1000>; 991 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 992 interrupt-controller; 993 #interrupt-cells = <3>; 994 #mbox-cells = <2>; 995 }; 996 997 qfprom: efuse@784000 { 998 compatible = "qcom,sc7280-qfprom", "qcom,qfprom"; 999 reg = <0 0x00784000 0 0xa20>, 1000 <0 0x00780000 0 0xa20>, 1001 <0 0x00782000 0 0x120>, 1002 <0 0x00786000 0 0x1fff>; 1003 clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>; 1004 clock-names = "core"; 1005 power-domains = <&rpmhpd SC7280_MX>; 1006 #address-cells = <1>; 1007 #size-cells = <1>; 1008 1009 gpu_speed_bin: gpu-speed-bin@1e9 { 1010 reg = <0x1e9 0x2>; 1011 bits = <5 8>; 1012 }; 1013 }; 1014 1015 sdhc_1: mmc@7c4000 { 1016 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 1017 pinctrl-names = "default", "sleep"; 1018 pinctrl-0 = <&sdc1_clk>, <&sdc1_cmd>, <&sdc1_data>, <&sdc1_rclk>; 1019 pinctrl-1 = <&sdc1_clk_sleep>, <&sdc1_cmd_sleep>, <&sdc1_data_sleep>, <&sdc1_rclk_sleep>; 1020 status = "disabled"; 1021 1022 reg = <0 0x007c4000 0 0x1000>, 1023 <0 0x007c5000 0 0x1000>; 1024 reg-names = "hc", "cqhci"; 1025 1026 iommus = <&apps_smmu 0xc0 0x0>; 1027 interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>, 1028 <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>; 1029 interrupt-names = "hc_irq", "pwr_irq"; 1030 1031 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 1032 <&gcc GCC_SDCC1_APPS_CLK>, 1033 <&rpmhcc RPMH_CXO_CLK>; 1034 clock-names = "iface", "core", "xo"; 1035 interconnects = <&aggre1_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>, 1036 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_1 0>; 1037 interconnect-names = "sdhc-ddr","cpu-sdhc"; 1038 power-domains = <&rpmhpd SC7280_CX>; 1039 operating-points-v2 = <&sdhc1_opp_table>; 1040 1041 bus-width = <8>; 1042 supports-cqe; 1043 dma-coherent; 1044 1045 qcom,dll-config = <0x0007642c>; 1046 qcom,ddr-config = <0x80040868>; 1047 1048 mmc-ddr-1_8v; 1049 mmc-hs200-1_8v; 1050 mmc-hs400-1_8v; 1051 mmc-hs400-enhanced-strobe; 1052 1053 resets = <&gcc GCC_SDCC1_BCR>; 1054 1055 sdhc1_opp_table: opp-table { 1056 compatible = "operating-points-v2"; 1057 1058 opp-100000000 { 1059 opp-hz = /bits/ 64 <100000000>; 1060 required-opps = <&rpmhpd_opp_low_svs>; 1061 opp-peak-kBps = <1800000 400000>; 1062 opp-avg-kBps = <100000 0>; 1063 }; 1064 1065 opp-384000000 { 1066 opp-hz = /bits/ 64 <384000000>; 1067 required-opps = <&rpmhpd_opp_nom>; 1068 opp-peak-kBps = <5400000 1600000>; 1069 opp-avg-kBps = <390000 0>; 1070 }; 1071 }; 1072 }; 1073 1074 gpi_dma0: dma-controller@900000 { 1075 #dma-cells = <3>; 1076 compatible = "qcom,sc7280-gpi-dma", "qcom,sm6350-gpi-dma"; 1077 reg = <0 0x00900000 0 0x60000>; 1078 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 1079 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 1080 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 1081 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 1082 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 1083 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 1084 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 1085 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 1086 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 1087 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 1088 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 1089 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 1090 dma-channels = <12>; 1091 dma-channel-mask = <0x7f>; 1092 iommus = <&apps_smmu 0x0136 0x0>; 1093 status = "disabled"; 1094 }; 1095 1096 qupv3_id_0: geniqup@9c0000 { 1097 compatible = "qcom,geni-se-qup"; 1098 reg = <0 0x009c0000 0 0x2000>; 1099 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1100 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1101 clock-names = "m-ahb", "s-ahb"; 1102 #address-cells = <2>; 1103 #size-cells = <2>; 1104 ranges; 1105 iommus = <&apps_smmu 0x123 0x0>; 1106 status = "disabled"; 1107 1108 i2c0: i2c@980000 { 1109 compatible = "qcom,geni-i2c"; 1110 reg = <0 0x00980000 0 0x4000>; 1111 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1112 clock-names = "se"; 1113 pinctrl-names = "default"; 1114 pinctrl-0 = <&qup_i2c0_data_clk>; 1115 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1116 #address-cells = <1>; 1117 #size-cells = <0>; 1118 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1119 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1120 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1121 interconnect-names = "qup-core", "qup-config", 1122 "qup-memory"; 1123 power-domains = <&rpmhpd SC7280_CX>; 1124 required-opps = <&rpmhpd_opp_low_svs>; 1125 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1126 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1127 dma-names = "tx", "rx"; 1128 status = "disabled"; 1129 }; 1130 1131 spi0: spi@980000 { 1132 compatible = "qcom,geni-spi"; 1133 reg = <0 0x00980000 0 0x4000>; 1134 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1135 clock-names = "se"; 1136 pinctrl-names = "default"; 1137 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 1138 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1139 #address-cells = <1>; 1140 #size-cells = <0>; 1141 power-domains = <&rpmhpd SC7280_CX>; 1142 operating-points-v2 = <&qup_opp_table>; 1143 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1144 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1145 interconnect-names = "qup-core", "qup-config"; 1146 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1147 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1148 dma-names = "tx", "rx"; 1149 status = "disabled"; 1150 }; 1151 1152 uart0: serial@980000 { 1153 compatible = "qcom,geni-uart"; 1154 reg = <0 0x00980000 0 0x4000>; 1155 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1156 clock-names = "se"; 1157 pinctrl-names = "default"; 1158 pinctrl-0 = <&qup_uart0_cts>, <&qup_uart0_rts>, <&qup_uart0_tx>, <&qup_uart0_rx>; 1159 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1160 power-domains = <&rpmhpd SC7280_CX>; 1161 operating-points-v2 = <&qup_opp_table>; 1162 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1163 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1164 interconnect-names = "qup-core", "qup-config"; 1165 status = "disabled"; 1166 }; 1167 1168 i2c1: i2c@984000 { 1169 compatible = "qcom,geni-i2c"; 1170 reg = <0 0x00984000 0 0x4000>; 1171 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1172 clock-names = "se"; 1173 pinctrl-names = "default"; 1174 pinctrl-0 = <&qup_i2c1_data_clk>; 1175 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1176 #address-cells = <1>; 1177 #size-cells = <0>; 1178 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1179 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1180 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1181 interconnect-names = "qup-core", "qup-config", 1182 "qup-memory"; 1183 power-domains = <&rpmhpd SC7280_CX>; 1184 required-opps = <&rpmhpd_opp_low_svs>; 1185 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1186 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1187 dma-names = "tx", "rx"; 1188 status = "disabled"; 1189 }; 1190 1191 spi1: spi@984000 { 1192 compatible = "qcom,geni-spi"; 1193 reg = <0 0x00984000 0 0x4000>; 1194 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1195 clock-names = "se"; 1196 pinctrl-names = "default"; 1197 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 1198 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1199 #address-cells = <1>; 1200 #size-cells = <0>; 1201 power-domains = <&rpmhpd SC7280_CX>; 1202 operating-points-v2 = <&qup_opp_table>; 1203 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1204 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1205 interconnect-names = "qup-core", "qup-config"; 1206 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1207 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1208 dma-names = "tx", "rx"; 1209 status = "disabled"; 1210 }; 1211 1212 uart1: serial@984000 { 1213 compatible = "qcom,geni-uart"; 1214 reg = <0 0x00984000 0 0x4000>; 1215 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1216 clock-names = "se"; 1217 pinctrl-names = "default"; 1218 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>; 1219 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1220 power-domains = <&rpmhpd SC7280_CX>; 1221 operating-points-v2 = <&qup_opp_table>; 1222 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1223 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1224 interconnect-names = "qup-core", "qup-config"; 1225 status = "disabled"; 1226 }; 1227 1228 i2c2: i2c@988000 { 1229 compatible = "qcom,geni-i2c"; 1230 reg = <0 0x00988000 0 0x4000>; 1231 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1232 clock-names = "se"; 1233 pinctrl-names = "default"; 1234 pinctrl-0 = <&qup_i2c2_data_clk>; 1235 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1236 #address-cells = <1>; 1237 #size-cells = <0>; 1238 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1239 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1240 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1241 interconnect-names = "qup-core", "qup-config", 1242 "qup-memory"; 1243 power-domains = <&rpmhpd SC7280_CX>; 1244 required-opps = <&rpmhpd_opp_low_svs>; 1245 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1246 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1247 dma-names = "tx", "rx"; 1248 status = "disabled"; 1249 }; 1250 1251 spi2: spi@988000 { 1252 compatible = "qcom,geni-spi"; 1253 reg = <0 0x00988000 0 0x4000>; 1254 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1255 clock-names = "se"; 1256 pinctrl-names = "default"; 1257 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 1258 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1259 #address-cells = <1>; 1260 #size-cells = <0>; 1261 power-domains = <&rpmhpd SC7280_CX>; 1262 operating-points-v2 = <&qup_opp_table>; 1263 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1264 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1265 interconnect-names = "qup-core", "qup-config"; 1266 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1267 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1268 dma-names = "tx", "rx"; 1269 status = "disabled"; 1270 }; 1271 1272 uart2: serial@988000 { 1273 compatible = "qcom,geni-uart"; 1274 reg = <0 0x00988000 0 0x4000>; 1275 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1276 clock-names = "se"; 1277 pinctrl-names = "default"; 1278 pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, <&qup_uart2_tx>, <&qup_uart2_rx>; 1279 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1280 power-domains = <&rpmhpd SC7280_CX>; 1281 operating-points-v2 = <&qup_opp_table>; 1282 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1283 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1284 interconnect-names = "qup-core", "qup-config"; 1285 status = "disabled"; 1286 }; 1287 1288 i2c3: i2c@98c000 { 1289 compatible = "qcom,geni-i2c"; 1290 reg = <0 0x0098c000 0 0x4000>; 1291 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1292 clock-names = "se"; 1293 pinctrl-names = "default"; 1294 pinctrl-0 = <&qup_i2c3_data_clk>; 1295 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1296 #address-cells = <1>; 1297 #size-cells = <0>; 1298 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1299 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1300 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1301 interconnect-names = "qup-core", "qup-config", 1302 "qup-memory"; 1303 power-domains = <&rpmhpd SC7280_CX>; 1304 required-opps = <&rpmhpd_opp_low_svs>; 1305 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1306 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1307 dma-names = "tx", "rx"; 1308 status = "disabled"; 1309 }; 1310 1311 spi3: spi@98c000 { 1312 compatible = "qcom,geni-spi"; 1313 reg = <0 0x0098c000 0 0x4000>; 1314 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1315 clock-names = "se"; 1316 pinctrl-names = "default"; 1317 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 1318 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1319 #address-cells = <1>; 1320 #size-cells = <0>; 1321 power-domains = <&rpmhpd SC7280_CX>; 1322 operating-points-v2 = <&qup_opp_table>; 1323 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1324 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1325 interconnect-names = "qup-core", "qup-config"; 1326 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1327 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1328 dma-names = "tx", "rx"; 1329 status = "disabled"; 1330 }; 1331 1332 uart3: serial@98c000 { 1333 compatible = "qcom,geni-uart"; 1334 reg = <0 0x0098c000 0 0x4000>; 1335 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1336 clock-names = "se"; 1337 pinctrl-names = "default"; 1338 pinctrl-0 = <&qup_uart3_cts>, <&qup_uart3_rts>, <&qup_uart3_tx>, <&qup_uart3_rx>; 1339 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1340 power-domains = <&rpmhpd SC7280_CX>; 1341 operating-points-v2 = <&qup_opp_table>; 1342 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1343 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1344 interconnect-names = "qup-core", "qup-config"; 1345 status = "disabled"; 1346 }; 1347 1348 i2c4: i2c@990000 { 1349 compatible = "qcom,geni-i2c"; 1350 reg = <0 0x00990000 0 0x4000>; 1351 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1352 clock-names = "se"; 1353 pinctrl-names = "default"; 1354 pinctrl-0 = <&qup_i2c4_data_clk>; 1355 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1356 #address-cells = <1>; 1357 #size-cells = <0>; 1358 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1359 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1360 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1361 interconnect-names = "qup-core", "qup-config", 1362 "qup-memory"; 1363 power-domains = <&rpmhpd SC7280_CX>; 1364 required-opps = <&rpmhpd_opp_low_svs>; 1365 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1366 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1367 dma-names = "tx", "rx"; 1368 status = "disabled"; 1369 }; 1370 1371 spi4: spi@990000 { 1372 compatible = "qcom,geni-spi"; 1373 reg = <0 0x00990000 0 0x4000>; 1374 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1375 clock-names = "se"; 1376 pinctrl-names = "default"; 1377 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 1378 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1379 #address-cells = <1>; 1380 #size-cells = <0>; 1381 power-domains = <&rpmhpd SC7280_CX>; 1382 operating-points-v2 = <&qup_opp_table>; 1383 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1384 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1385 interconnect-names = "qup-core", "qup-config"; 1386 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1387 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1388 dma-names = "tx", "rx"; 1389 status = "disabled"; 1390 }; 1391 1392 uart4: serial@990000 { 1393 compatible = "qcom,geni-uart"; 1394 reg = <0 0x00990000 0 0x4000>; 1395 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1396 clock-names = "se"; 1397 pinctrl-names = "default"; 1398 pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, <&qup_uart4_tx>, <&qup_uart4_rx>; 1399 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1400 power-domains = <&rpmhpd SC7280_CX>; 1401 operating-points-v2 = <&qup_opp_table>; 1402 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1403 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1404 interconnect-names = "qup-core", "qup-config"; 1405 status = "disabled"; 1406 }; 1407 1408 i2c5: i2c@994000 { 1409 compatible = "qcom,geni-i2c"; 1410 reg = <0 0x00994000 0 0x4000>; 1411 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1412 clock-names = "se"; 1413 pinctrl-names = "default"; 1414 pinctrl-0 = <&qup_i2c5_data_clk>; 1415 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1416 #address-cells = <1>; 1417 #size-cells = <0>; 1418 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1419 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1420 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1421 interconnect-names = "qup-core", "qup-config", 1422 "qup-memory"; 1423 power-domains = <&rpmhpd SC7280_CX>; 1424 required-opps = <&rpmhpd_opp_low_svs>; 1425 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1426 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1427 dma-names = "tx", "rx"; 1428 status = "disabled"; 1429 }; 1430 1431 spi5: spi@994000 { 1432 compatible = "qcom,geni-spi"; 1433 reg = <0 0x00994000 0 0x4000>; 1434 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1435 clock-names = "se"; 1436 pinctrl-names = "default"; 1437 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 1438 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1439 #address-cells = <1>; 1440 #size-cells = <0>; 1441 power-domains = <&rpmhpd SC7280_CX>; 1442 operating-points-v2 = <&qup_opp_table>; 1443 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1444 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1445 interconnect-names = "qup-core", "qup-config"; 1446 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1447 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1448 dma-names = "tx", "rx"; 1449 status = "disabled"; 1450 }; 1451 1452 uart5: serial@994000 { 1453 compatible = "qcom,geni-debug-uart"; 1454 reg = <0 0x00994000 0 0x4000>; 1455 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1456 clock-names = "se"; 1457 pinctrl-names = "default"; 1458 pinctrl-0 = <&qup_uart5_tx>, <&qup_uart5_rx>; 1459 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1460 power-domains = <&rpmhpd SC7280_CX>; 1461 operating-points-v2 = <&qup_opp_table>; 1462 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1463 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1464 interconnect-names = "qup-core", "qup-config"; 1465 status = "disabled"; 1466 }; 1467 1468 i2c6: i2c@998000 { 1469 compatible = "qcom,geni-i2c"; 1470 reg = <0 0x00998000 0 0x4000>; 1471 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1472 clock-names = "se"; 1473 pinctrl-names = "default"; 1474 pinctrl-0 = <&qup_i2c6_data_clk>; 1475 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1476 #address-cells = <1>; 1477 #size-cells = <0>; 1478 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1479 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1480 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1481 interconnect-names = "qup-core", "qup-config", 1482 "qup-memory"; 1483 power-domains = <&rpmhpd SC7280_CX>; 1484 required-opps = <&rpmhpd_opp_low_svs>; 1485 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1486 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1487 dma-names = "tx", "rx"; 1488 status = "disabled"; 1489 }; 1490 1491 spi6: spi@998000 { 1492 compatible = "qcom,geni-spi"; 1493 reg = <0 0x00998000 0 0x4000>; 1494 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1495 clock-names = "se"; 1496 pinctrl-names = "default"; 1497 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1498 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1499 #address-cells = <1>; 1500 #size-cells = <0>; 1501 power-domains = <&rpmhpd SC7280_CX>; 1502 operating-points-v2 = <&qup_opp_table>; 1503 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1504 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1505 interconnect-names = "qup-core", "qup-config"; 1506 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1507 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1508 dma-names = "tx", "rx"; 1509 status = "disabled"; 1510 }; 1511 1512 uart6: serial@998000 { 1513 compatible = "qcom,geni-uart"; 1514 reg = <0 0x00998000 0 0x4000>; 1515 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1516 clock-names = "se"; 1517 pinctrl-names = "default"; 1518 pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, <&qup_uart6_tx>, <&qup_uart6_rx>; 1519 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1520 power-domains = <&rpmhpd SC7280_CX>; 1521 operating-points-v2 = <&qup_opp_table>; 1522 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1523 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1524 interconnect-names = "qup-core", "qup-config"; 1525 status = "disabled"; 1526 }; 1527 1528 i2c7: i2c@99c000 { 1529 compatible = "qcom,geni-i2c"; 1530 reg = <0 0x0099c000 0 0x4000>; 1531 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1532 clock-names = "se"; 1533 pinctrl-names = "default"; 1534 pinctrl-0 = <&qup_i2c7_data_clk>; 1535 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1536 #address-cells = <1>; 1537 #size-cells = <0>; 1538 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1539 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1540 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1541 interconnect-names = "qup-core", "qup-config", 1542 "qup-memory"; 1543 power-domains = <&rpmhpd SC7280_CX>; 1544 required-opps = <&rpmhpd_opp_low_svs>; 1545 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 1546 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 1547 dma-names = "tx", "rx"; 1548 status = "disabled"; 1549 }; 1550 1551 spi7: spi@99c000 { 1552 compatible = "qcom,geni-spi"; 1553 reg = <0 0x0099c000 0 0x4000>; 1554 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1555 clock-names = "se"; 1556 pinctrl-names = "default"; 1557 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; 1558 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1559 #address-cells = <1>; 1560 #size-cells = <0>; 1561 power-domains = <&rpmhpd SC7280_CX>; 1562 operating-points-v2 = <&qup_opp_table>; 1563 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1564 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1565 interconnect-names = "qup-core", "qup-config"; 1566 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1567 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1568 dma-names = "tx", "rx"; 1569 status = "disabled"; 1570 }; 1571 1572 uart7: serial@99c000 { 1573 compatible = "qcom,geni-uart"; 1574 reg = <0 0x0099c000 0 0x4000>; 1575 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1576 clock-names = "se"; 1577 pinctrl-names = "default"; 1578 pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, <&qup_uart7_tx>, <&qup_uart7_rx>; 1579 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1580 power-domains = <&rpmhpd SC7280_CX>; 1581 operating-points-v2 = <&qup_opp_table>; 1582 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1583 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1584 interconnect-names = "qup-core", "qup-config"; 1585 status = "disabled"; 1586 }; 1587 }; 1588 1589 gpi_dma1: dma-controller@a00000 { 1590 #dma-cells = <3>; 1591 compatible = "qcom,sc7280-gpi-dma", "qcom,sm6350-gpi-dma"; 1592 reg = <0 0x00a00000 0 0x60000>; 1593 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1594 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1595 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1596 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1597 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1598 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1599 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1600 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1601 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1602 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1603 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1604 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1605 dma-channels = <12>; 1606 dma-channel-mask = <0x1e>; 1607 iommus = <&apps_smmu 0x56 0x0>; 1608 status = "disabled"; 1609 }; 1610 1611 qupv3_id_1: geniqup@ac0000 { 1612 compatible = "qcom,geni-se-qup"; 1613 reg = <0 0x00ac0000 0 0x2000>; 1614 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1615 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1616 clock-names = "m-ahb", "s-ahb"; 1617 #address-cells = <2>; 1618 #size-cells = <2>; 1619 ranges; 1620 iommus = <&apps_smmu 0x43 0x0>; 1621 status = "disabled"; 1622 1623 i2c8: i2c@a80000 { 1624 compatible = "qcom,geni-i2c"; 1625 reg = <0 0x00a80000 0 0x4000>; 1626 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1627 clock-names = "se"; 1628 pinctrl-names = "default"; 1629 pinctrl-0 = <&qup_i2c8_data_clk>; 1630 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1631 #address-cells = <1>; 1632 #size-cells = <0>; 1633 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1634 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1635 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1636 interconnect-names = "qup-core", "qup-config", 1637 "qup-memory"; 1638 power-domains = <&rpmhpd SC7280_CX>; 1639 required-opps = <&rpmhpd_opp_low_svs>; 1640 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1641 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1642 dma-names = "tx", "rx"; 1643 status = "disabled"; 1644 }; 1645 1646 spi8: spi@a80000 { 1647 compatible = "qcom,geni-spi"; 1648 reg = <0 0x00a80000 0 0x4000>; 1649 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1650 clock-names = "se"; 1651 pinctrl-names = "default"; 1652 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1653 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1654 #address-cells = <1>; 1655 #size-cells = <0>; 1656 power-domains = <&rpmhpd SC7280_CX>; 1657 operating-points-v2 = <&qup_opp_table>; 1658 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1659 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1660 interconnect-names = "qup-core", "qup-config"; 1661 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1662 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1663 dma-names = "tx", "rx"; 1664 status = "disabled"; 1665 }; 1666 1667 uart8: serial@a80000 { 1668 compatible = "qcom,geni-uart"; 1669 reg = <0 0x00a80000 0 0x4000>; 1670 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1671 clock-names = "se"; 1672 pinctrl-names = "default"; 1673 pinctrl-0 = <&qup_uart8_cts>, <&qup_uart8_rts>, <&qup_uart8_tx>, <&qup_uart8_rx>; 1674 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1675 power-domains = <&rpmhpd SC7280_CX>; 1676 operating-points-v2 = <&qup_opp_table>; 1677 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1678 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1679 interconnect-names = "qup-core", "qup-config"; 1680 status = "disabled"; 1681 }; 1682 1683 i2c9: i2c@a84000 { 1684 compatible = "qcom,geni-i2c"; 1685 reg = <0 0x00a84000 0 0x4000>; 1686 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1687 clock-names = "se"; 1688 pinctrl-names = "default"; 1689 pinctrl-0 = <&qup_i2c9_data_clk>; 1690 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1691 #address-cells = <1>; 1692 #size-cells = <0>; 1693 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1694 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1695 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1696 interconnect-names = "qup-core", "qup-config", 1697 "qup-memory"; 1698 power-domains = <&rpmhpd SC7280_CX>; 1699 required-opps = <&rpmhpd_opp_low_svs>; 1700 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1701 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1702 dma-names = "tx", "rx"; 1703 status = "disabled"; 1704 }; 1705 1706 spi9: spi@a84000 { 1707 compatible = "qcom,geni-spi"; 1708 reg = <0 0x00a84000 0 0x4000>; 1709 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1710 clock-names = "se"; 1711 pinctrl-names = "default"; 1712 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1713 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1714 #address-cells = <1>; 1715 #size-cells = <0>; 1716 power-domains = <&rpmhpd SC7280_CX>; 1717 operating-points-v2 = <&qup_opp_table>; 1718 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1719 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1720 interconnect-names = "qup-core", "qup-config"; 1721 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1722 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1723 dma-names = "tx", "rx"; 1724 status = "disabled"; 1725 }; 1726 1727 uart9: serial@a84000 { 1728 compatible = "qcom,geni-uart"; 1729 reg = <0 0x00a84000 0 0x4000>; 1730 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1731 clock-names = "se"; 1732 pinctrl-names = "default"; 1733 pinctrl-0 = <&qup_uart9_cts>, <&qup_uart9_rts>, <&qup_uart9_tx>, <&qup_uart9_rx>; 1734 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1735 power-domains = <&rpmhpd SC7280_CX>; 1736 operating-points-v2 = <&qup_opp_table>; 1737 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1738 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1739 interconnect-names = "qup-core", "qup-config"; 1740 status = "disabled"; 1741 }; 1742 1743 i2c10: i2c@a88000 { 1744 compatible = "qcom,geni-i2c"; 1745 reg = <0 0x00a88000 0 0x4000>; 1746 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1747 clock-names = "se"; 1748 pinctrl-names = "default"; 1749 pinctrl-0 = <&qup_i2c10_data_clk>; 1750 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1751 #address-cells = <1>; 1752 #size-cells = <0>; 1753 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1754 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1755 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1756 interconnect-names = "qup-core", "qup-config", 1757 "qup-memory"; 1758 power-domains = <&rpmhpd SC7280_CX>; 1759 required-opps = <&rpmhpd_opp_low_svs>; 1760 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1761 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1762 dma-names = "tx", "rx"; 1763 status = "disabled"; 1764 }; 1765 1766 spi10: spi@a88000 { 1767 compatible = "qcom,geni-spi"; 1768 reg = <0 0x00a88000 0 0x4000>; 1769 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1770 clock-names = "se"; 1771 pinctrl-names = "default"; 1772 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1773 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1774 #address-cells = <1>; 1775 #size-cells = <0>; 1776 power-domains = <&rpmhpd SC7280_CX>; 1777 operating-points-v2 = <&qup_opp_table>; 1778 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1779 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1780 interconnect-names = "qup-core", "qup-config"; 1781 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1782 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1783 dma-names = "tx", "rx"; 1784 status = "disabled"; 1785 }; 1786 1787 uart10: serial@a88000 { 1788 compatible = "qcom,geni-uart"; 1789 reg = <0 0x00a88000 0 0x4000>; 1790 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1791 clock-names = "se"; 1792 pinctrl-names = "default"; 1793 pinctrl-0 = <&qup_uart10_cts>, <&qup_uart10_rts>, <&qup_uart10_tx>, <&qup_uart10_rx>; 1794 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1795 power-domains = <&rpmhpd SC7280_CX>; 1796 operating-points-v2 = <&qup_opp_table>; 1797 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1798 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1799 interconnect-names = "qup-core", "qup-config"; 1800 status = "disabled"; 1801 }; 1802 1803 i2c11: i2c@a8c000 { 1804 compatible = "qcom,geni-i2c"; 1805 reg = <0 0x00a8c000 0 0x4000>; 1806 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1807 clock-names = "se"; 1808 pinctrl-names = "default"; 1809 pinctrl-0 = <&qup_i2c11_data_clk>; 1810 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1811 #address-cells = <1>; 1812 #size-cells = <0>; 1813 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1814 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1815 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1816 interconnect-names = "qup-core", "qup-config", 1817 "qup-memory"; 1818 power-domains = <&rpmhpd SC7280_CX>; 1819 required-opps = <&rpmhpd_opp_low_svs>; 1820 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1821 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1822 dma-names = "tx", "rx"; 1823 status = "disabled"; 1824 }; 1825 1826 spi11: spi@a8c000 { 1827 compatible = "qcom,geni-spi"; 1828 reg = <0 0x00a8c000 0 0x4000>; 1829 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1830 clock-names = "se"; 1831 pinctrl-names = "default"; 1832 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1833 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1834 #address-cells = <1>; 1835 #size-cells = <0>; 1836 power-domains = <&rpmhpd SC7280_CX>; 1837 operating-points-v2 = <&qup_opp_table>; 1838 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1839 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1840 interconnect-names = "qup-core", "qup-config"; 1841 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1842 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1843 dma-names = "tx", "rx"; 1844 status = "disabled"; 1845 }; 1846 1847 uart11: serial@a8c000 { 1848 compatible = "qcom,geni-uart"; 1849 reg = <0 0x00a8c000 0 0x4000>; 1850 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1851 clock-names = "se"; 1852 pinctrl-names = "default"; 1853 pinctrl-0 = <&qup_uart11_cts>, <&qup_uart11_rts>, <&qup_uart11_tx>, <&qup_uart11_rx>; 1854 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1855 power-domains = <&rpmhpd SC7280_CX>; 1856 operating-points-v2 = <&qup_opp_table>; 1857 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1858 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1859 interconnect-names = "qup-core", "qup-config"; 1860 status = "disabled"; 1861 }; 1862 1863 i2c12: i2c@a90000 { 1864 compatible = "qcom,geni-i2c"; 1865 reg = <0 0x00a90000 0 0x4000>; 1866 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1867 clock-names = "se"; 1868 pinctrl-names = "default"; 1869 pinctrl-0 = <&qup_i2c12_data_clk>; 1870 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1871 #address-cells = <1>; 1872 #size-cells = <0>; 1873 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1874 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1875 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1876 interconnect-names = "qup-core", "qup-config", 1877 "qup-memory"; 1878 power-domains = <&rpmhpd SC7280_CX>; 1879 required-opps = <&rpmhpd_opp_low_svs>; 1880 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1881 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1882 dma-names = "tx", "rx"; 1883 status = "disabled"; 1884 }; 1885 1886 spi12: spi@a90000 { 1887 compatible = "qcom,geni-spi"; 1888 reg = <0 0x00a90000 0 0x4000>; 1889 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1890 clock-names = "se"; 1891 pinctrl-names = "default"; 1892 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1893 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1894 #address-cells = <1>; 1895 #size-cells = <0>; 1896 power-domains = <&rpmhpd SC7280_CX>; 1897 operating-points-v2 = <&qup_opp_table>; 1898 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1899 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1900 interconnect-names = "qup-core", "qup-config"; 1901 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1902 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1903 dma-names = "tx", "rx"; 1904 status = "disabled"; 1905 }; 1906 1907 uart12: serial@a90000 { 1908 compatible = "qcom,geni-uart"; 1909 reg = <0 0x00a90000 0 0x4000>; 1910 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1911 clock-names = "se"; 1912 pinctrl-names = "default"; 1913 pinctrl-0 = <&qup_uart12_cts>, <&qup_uart12_rts>, <&qup_uart12_tx>, <&qup_uart12_rx>; 1914 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1915 power-domains = <&rpmhpd SC7280_CX>; 1916 operating-points-v2 = <&qup_opp_table>; 1917 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1918 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1919 interconnect-names = "qup-core", "qup-config"; 1920 status = "disabled"; 1921 }; 1922 1923 i2c13: i2c@a94000 { 1924 compatible = "qcom,geni-i2c"; 1925 reg = <0 0x00a94000 0 0x4000>; 1926 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1927 clock-names = "se"; 1928 pinctrl-names = "default"; 1929 pinctrl-0 = <&qup_i2c13_data_clk>; 1930 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1931 #address-cells = <1>; 1932 #size-cells = <0>; 1933 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1934 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1935 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1936 interconnect-names = "qup-core", "qup-config", 1937 "qup-memory"; 1938 power-domains = <&rpmhpd SC7280_CX>; 1939 required-opps = <&rpmhpd_opp_low_svs>; 1940 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1941 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1942 dma-names = "tx", "rx"; 1943 status = "disabled"; 1944 }; 1945 1946 spi13: spi@a94000 { 1947 compatible = "qcom,geni-spi"; 1948 reg = <0 0x00a94000 0 0x4000>; 1949 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1950 clock-names = "se"; 1951 pinctrl-names = "default"; 1952 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1953 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1954 #address-cells = <1>; 1955 #size-cells = <0>; 1956 power-domains = <&rpmhpd SC7280_CX>; 1957 operating-points-v2 = <&qup_opp_table>; 1958 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1959 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1960 interconnect-names = "qup-core", "qup-config"; 1961 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1962 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1963 dma-names = "tx", "rx"; 1964 status = "disabled"; 1965 }; 1966 1967 uart13: serial@a94000 { 1968 compatible = "qcom,geni-uart"; 1969 reg = <0 0x00a94000 0 0x4000>; 1970 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1971 clock-names = "se"; 1972 pinctrl-names = "default"; 1973 pinctrl-0 = <&qup_uart13_cts>, <&qup_uart13_rts>, <&qup_uart13_tx>, <&qup_uart13_rx>; 1974 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1975 power-domains = <&rpmhpd SC7280_CX>; 1976 operating-points-v2 = <&qup_opp_table>; 1977 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1978 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1979 interconnect-names = "qup-core", "qup-config"; 1980 status = "disabled"; 1981 }; 1982 1983 i2c14: i2c@a98000 { 1984 compatible = "qcom,geni-i2c"; 1985 reg = <0 0x00a98000 0 0x4000>; 1986 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1987 clock-names = "se"; 1988 pinctrl-names = "default"; 1989 pinctrl-0 = <&qup_i2c14_data_clk>; 1990 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1991 #address-cells = <1>; 1992 #size-cells = <0>; 1993 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1994 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1995 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1996 interconnect-names = "qup-core", "qup-config", 1997 "qup-memory"; 1998 power-domains = <&rpmhpd SC7280_CX>; 1999 required-opps = <&rpmhpd_opp_low_svs>; 2000 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 2001 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 2002 dma-names = "tx", "rx"; 2003 status = "disabled"; 2004 }; 2005 2006 spi14: spi@a98000 { 2007 compatible = "qcom,geni-spi"; 2008 reg = <0 0x00a98000 0 0x4000>; 2009 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 2010 clock-names = "se"; 2011 pinctrl-names = "default"; 2012 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 2013 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 2014 #address-cells = <1>; 2015 #size-cells = <0>; 2016 power-domains = <&rpmhpd SC7280_CX>; 2017 operating-points-v2 = <&qup_opp_table>; 2018 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 2019 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 2020 interconnect-names = "qup-core", "qup-config"; 2021 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 2022 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 2023 dma-names = "tx", "rx"; 2024 status = "disabled"; 2025 }; 2026 2027 uart14: serial@a98000 { 2028 compatible = "qcom,geni-uart"; 2029 reg = <0 0x00a98000 0 0x4000>; 2030 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 2031 clock-names = "se"; 2032 pinctrl-names = "default"; 2033 pinctrl-0 = <&qup_uart14_cts>, <&qup_uart14_rts>, <&qup_uart14_tx>, <&qup_uart14_rx>; 2034 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 2035 power-domains = <&rpmhpd SC7280_CX>; 2036 operating-points-v2 = <&qup_opp_table>; 2037 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 2038 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 2039 interconnect-names = "qup-core", "qup-config"; 2040 status = "disabled"; 2041 }; 2042 2043 i2c15: i2c@a9c000 { 2044 compatible = "qcom,geni-i2c"; 2045 reg = <0 0x00a9c000 0 0x4000>; 2046 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2047 clock-names = "se"; 2048 pinctrl-names = "default"; 2049 pinctrl-0 = <&qup_i2c15_data_clk>; 2050 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 2051 #address-cells = <1>; 2052 #size-cells = <0>; 2053 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 2054 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 2055 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 2056 interconnect-names = "qup-core", "qup-config", 2057 "qup-memory"; 2058 power-domains = <&rpmhpd SC7280_CX>; 2059 required-opps = <&rpmhpd_opp_low_svs>; 2060 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, 2061 <&gpi_dma1 1 7 QCOM_GPI_I2C>; 2062 dma-names = "tx", "rx"; 2063 status = "disabled"; 2064 }; 2065 2066 spi15: spi@a9c000 { 2067 compatible = "qcom,geni-spi"; 2068 reg = <0 0x00a9c000 0 0x4000>; 2069 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2070 clock-names = "se"; 2071 pinctrl-names = "default"; 2072 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 2073 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 2074 #address-cells = <1>; 2075 #size-cells = <0>; 2076 power-domains = <&rpmhpd SC7280_CX>; 2077 operating-points-v2 = <&qup_opp_table>; 2078 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 2079 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 2080 interconnect-names = "qup-core", "qup-config"; 2081 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, 2082 <&gpi_dma1 1 7 QCOM_GPI_SPI>; 2083 dma-names = "tx", "rx"; 2084 status = "disabled"; 2085 }; 2086 2087 uart15: serial@a9c000 { 2088 compatible = "qcom,geni-uart"; 2089 reg = <0 0x00a9c000 0 0x4000>; 2090 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2091 clock-names = "se"; 2092 pinctrl-names = "default"; 2093 pinctrl-0 = <&qup_uart15_cts>, <&qup_uart15_rts>, <&qup_uart15_tx>, <&qup_uart15_rx>; 2094 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 2095 power-domains = <&rpmhpd SC7280_CX>; 2096 operating-points-v2 = <&qup_opp_table>; 2097 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 2098 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 2099 interconnect-names = "qup-core", "qup-config"; 2100 status = "disabled"; 2101 }; 2102 }; 2103 2104 rng: rng@10d3000 { 2105 compatible = "qcom,sc7280-trng", "qcom,trng"; 2106 reg = <0 0x010d3000 0 0x1000>; 2107 }; 2108 2109 cnoc2: interconnect@1500000 { 2110 reg = <0 0x01500000 0 0x1000>; 2111 compatible = "qcom,sc7280-cnoc2"; 2112 #interconnect-cells = <2>; 2113 qcom,bcm-voters = <&apps_bcm_voter>; 2114 }; 2115 2116 cnoc3: interconnect@1502000 { 2117 reg = <0 0x01502000 0 0x1000>; 2118 compatible = "qcom,sc7280-cnoc3"; 2119 #interconnect-cells = <2>; 2120 qcom,bcm-voters = <&apps_bcm_voter>; 2121 }; 2122 2123 mc_virt: interconnect@1580000 { 2124 reg = <0 0x01580000 0 0x4>; 2125 compatible = "qcom,sc7280-mc-virt"; 2126 #interconnect-cells = <2>; 2127 qcom,bcm-voters = <&apps_bcm_voter>; 2128 }; 2129 2130 system_noc: interconnect@1680000 { 2131 reg = <0 0x01680000 0 0x15480>; 2132 compatible = "qcom,sc7280-system-noc"; 2133 #interconnect-cells = <2>; 2134 qcom,bcm-voters = <&apps_bcm_voter>; 2135 }; 2136 2137 aggre1_noc: interconnect@16e0000 { 2138 compatible = "qcom,sc7280-aggre1-noc"; 2139 reg = <0 0x016e0000 0 0x1c080>; 2140 #interconnect-cells = <2>; 2141 qcom,bcm-voters = <&apps_bcm_voter>; 2142 clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2143 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; 2144 }; 2145 2146 aggre2_noc: interconnect@1700000 { 2147 reg = <0 0x01700000 0 0x2b080>; 2148 compatible = "qcom,sc7280-aggre2-noc"; 2149 #interconnect-cells = <2>; 2150 qcom,bcm-voters = <&apps_bcm_voter>; 2151 clocks = <&rpmhcc RPMH_IPA_CLK>; 2152 }; 2153 2154 mmss_noc: interconnect@1740000 { 2155 reg = <0 0x01740000 0 0x1e080>; 2156 compatible = "qcom,sc7280-mmss-noc"; 2157 #interconnect-cells = <2>; 2158 qcom,bcm-voters = <&apps_bcm_voter>; 2159 }; 2160 2161 wifi: wifi@17a10040 { 2162 compatible = "qcom,wcn6750-wifi"; 2163 reg = <0 0x17a10040 0 0x0>; 2164 iommus = <&apps_smmu 0x1c00 0x1>; 2165 interrupts = <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>, 2166 <GIC_SPI 769 IRQ_TYPE_EDGE_RISING>, 2167 <GIC_SPI 770 IRQ_TYPE_EDGE_RISING>, 2168 <GIC_SPI 771 IRQ_TYPE_EDGE_RISING>, 2169 <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>, 2170 <GIC_SPI 773 IRQ_TYPE_EDGE_RISING>, 2171 <GIC_SPI 774 IRQ_TYPE_EDGE_RISING>, 2172 <GIC_SPI 775 IRQ_TYPE_EDGE_RISING>, 2173 <GIC_SPI 776 IRQ_TYPE_EDGE_RISING>, 2174 <GIC_SPI 777 IRQ_TYPE_EDGE_RISING>, 2175 <GIC_SPI 778 IRQ_TYPE_EDGE_RISING>, 2176 <GIC_SPI 779 IRQ_TYPE_EDGE_RISING>, 2177 <GIC_SPI 780 IRQ_TYPE_EDGE_RISING>, 2178 <GIC_SPI 781 IRQ_TYPE_EDGE_RISING>, 2179 <GIC_SPI 782 IRQ_TYPE_EDGE_RISING>, 2180 <GIC_SPI 783 IRQ_TYPE_EDGE_RISING>, 2181 <GIC_SPI 784 IRQ_TYPE_EDGE_RISING>, 2182 <GIC_SPI 785 IRQ_TYPE_EDGE_RISING>, 2183 <GIC_SPI 786 IRQ_TYPE_EDGE_RISING>, 2184 <GIC_SPI 787 IRQ_TYPE_EDGE_RISING>, 2185 <GIC_SPI 788 IRQ_TYPE_EDGE_RISING>, 2186 <GIC_SPI 789 IRQ_TYPE_EDGE_RISING>, 2187 <GIC_SPI 790 IRQ_TYPE_EDGE_RISING>, 2188 <GIC_SPI 791 IRQ_TYPE_EDGE_RISING>, 2189 <GIC_SPI 792 IRQ_TYPE_EDGE_RISING>, 2190 <GIC_SPI 793 IRQ_TYPE_EDGE_RISING>, 2191 <GIC_SPI 794 IRQ_TYPE_EDGE_RISING>, 2192 <GIC_SPI 795 IRQ_TYPE_EDGE_RISING>, 2193 <GIC_SPI 796 IRQ_TYPE_EDGE_RISING>, 2194 <GIC_SPI 797 IRQ_TYPE_EDGE_RISING>, 2195 <GIC_SPI 798 IRQ_TYPE_EDGE_RISING>, 2196 <GIC_SPI 799 IRQ_TYPE_EDGE_RISING>; 2197 qcom,rproc = <&remoteproc_wpss>; 2198 memory-region = <&wlan_fw_mem>, <&wlan_ce_mem>; 2199 status = "disabled"; 2200 qcom,smem-states = <&wlan_smp2p_out 0>; 2201 qcom,smem-state-names = "wlan-smp2p-out"; 2202 }; 2203 2204 pcie0: pcie@1c00000 { 2205 compatible = "qcom,pcie-sc7280"; 2206 reg = <0 0x01c00000 0 0x3000>, 2207 <0 0x60000000 0 0xf1d>, 2208 <0 0x60000f20 0 0xa8>, 2209 <0 0x60001000 0 0x1000>, 2210 <0 0x60100000 0 0x100000>, 2211 <0 0x01c03000 0 0x1000>; 2212 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 2213 device_type = "pci"; 2214 linux,pci-domain = <0>; 2215 bus-range = <0x00 0xff>; 2216 num-lanes = <1>; 2217 2218 #address-cells = <3>; 2219 #size-cells = <2>; 2220 2221 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 2222 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; 2223 2224 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 2225 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 2226 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 2227 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 2228 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 2229 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 2230 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 2231 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 2232 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 2233 interrupt-names = "msi0", 2234 "msi1", 2235 "msi2", 2236 "msi3", 2237 "msi4", 2238 "msi5", 2239 "msi6", 2240 "msi7", 2241 "global"; 2242 #interrupt-cells = <1>; 2243 interrupt-map-mask = <0 0 0 0x7>; 2244 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 2245 <0 0 0 2 &intc 0 0 GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 2246 <0 0 0 3 &intc 0 0 GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 2247 <0 0 0 4 &intc 0 0 GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 2248 2249 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 2250 <&gcc GCC_PCIE_0_PIPE_CLK_SRC>, 2251 <&pcie0_phy>, 2252 <&rpmhcc RPMH_CXO_CLK>, 2253 <&gcc GCC_PCIE_0_AUX_CLK>, 2254 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 2255 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 2256 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 2257 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 2258 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 2259 <&gcc GCC_DDRSS_PCIE_SF_CLK>, 2260 <&gcc GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK>, 2261 <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>; 2262 clock-names = "pipe", 2263 "pipe_mux", 2264 "phy_pipe", 2265 "ref", 2266 "aux", 2267 "cfg", 2268 "bus_master", 2269 "bus_slave", 2270 "slave_q2a", 2271 "tbu", 2272 "ddrss_sf_tbu", 2273 "aggre0", 2274 "aggre1"; 2275 2276 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, 2277 <0x100 &apps_smmu 0x1c01 0x1>; 2278 2279 resets = <&gcc GCC_PCIE_0_BCR>; 2280 reset-names = "pci"; 2281 2282 power-domains = <&gcc GCC_PCIE_0_GDSC>; 2283 2284 phys = <&pcie0_phy>; 2285 phy-names = "pciephy"; 2286 2287 pinctrl-names = "default"; 2288 pinctrl-0 = <&pcie0_clkreq_n>; 2289 dma-coherent; 2290 2291 status = "disabled"; 2292 2293 pcie0_port: pcie@0 { 2294 device_type = "pci"; 2295 reg = <0x0 0x0 0x0 0x0 0x0>; 2296 bus-range = <0x01 0xff>; 2297 2298 #address-cells = <3>; 2299 #size-cells = <2>; 2300 ranges; 2301 }; 2302 }; 2303 2304 pcie0_phy: phy@1c06000 { 2305 compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy"; 2306 reg = <0 0x01c06000 0 0x1000>; 2307 2308 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 2309 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 2310 <&gcc GCC_PCIE_CLKREF_EN>, 2311 <&gcc GCC_PCIE0_PHY_RCHNG_CLK>, 2312 <&gcc GCC_PCIE_0_PIPE_CLK>; 2313 clock-names = "aux", 2314 "cfg_ahb", 2315 "ref", 2316 "refgen", 2317 "pipe"; 2318 2319 clock-output-names = "pcie_0_pipe_clk"; 2320 #clock-cells = <0>; 2321 2322 #phy-cells = <0>; 2323 2324 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 2325 reset-names = "phy"; 2326 2327 assigned-clocks = <&gcc GCC_PCIE0_PHY_RCHNG_CLK>; 2328 assigned-clock-rates = <100000000>; 2329 2330 status = "disabled"; 2331 }; 2332 2333 pcie1: pcie@1c08000 { 2334 compatible = "qcom,pcie-sc7280"; 2335 reg = <0 0x01c08000 0 0x3000>, 2336 <0 0x40000000 0 0xf1d>, 2337 <0 0x40000f20 0 0xa8>, 2338 <0 0x40001000 0 0x1000>, 2339 <0 0x40100000 0 0x100000>; 2340 2341 reg-names = "parf", "dbi", "elbi", "atu", "config"; 2342 device_type = "pci"; 2343 linux,pci-domain = <1>; 2344 bus-range = <0x00 0xff>; 2345 num-lanes = <2>; 2346 2347 #address-cells = <3>; 2348 #size-cells = <2>; 2349 2350 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 2351 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 2352 2353 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 2354 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 2355 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 2356 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 2357 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 2358 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 2359 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, 2360 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, 2361 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 2362 interrupt-names = "msi0", 2363 "msi1", 2364 "msi2", 2365 "msi3", 2366 "msi4", 2367 "msi5", 2368 "msi6", 2369 "msi7", 2370 "global"; 2371 #interrupt-cells = <1>; 2372 interrupt-map-mask = <0 0 0 0x7>; 2373 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, 2374 <0 0 0 2 &intc 0 0 GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, 2375 <0 0 0 3 &intc 0 0 GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, 2376 <0 0 0 4 &intc 0 0 GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>; 2377 2378 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 2379 <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, 2380 <&pcie1_phy>, 2381 <&rpmhcc RPMH_CXO_CLK>, 2382 <&gcc GCC_PCIE_1_AUX_CLK>, 2383 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2384 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 2385 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 2386 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 2387 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 2388 <&gcc GCC_DDRSS_PCIE_SF_CLK>, 2389 <&gcc GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK>, 2390 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; 2391 2392 clock-names = "pipe", 2393 "pipe_mux", 2394 "phy_pipe", 2395 "ref", 2396 "aux", 2397 "cfg", 2398 "bus_master", 2399 "bus_slave", 2400 "slave_q2a", 2401 "tbu", 2402 "ddrss_sf_tbu", 2403 "aggre0", 2404 "aggre1"; 2405 2406 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 2407 assigned-clock-rates = <19200000>; 2408 2409 resets = <&gcc GCC_PCIE_1_BCR>; 2410 reset-names = "pci"; 2411 2412 power-domains = <&gcc GCC_PCIE_1_GDSC>; 2413 2414 phys = <&pcie1_phy>; 2415 phy-names = "pciephy"; 2416 2417 pinctrl-names = "default"; 2418 pinctrl-0 = <&pcie1_clkreq_n>; 2419 2420 dma-coherent; 2421 2422 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 2423 <0x100 &apps_smmu 0x1c81 0x1>; 2424 2425 status = "disabled"; 2426 2427 pcie@0 { 2428 device_type = "pci"; 2429 reg = <0x0 0x0 0x0 0x0 0x0>; 2430 bus-range = <0x01 0xff>; 2431 2432 #address-cells = <3>; 2433 #size-cells = <2>; 2434 ranges; 2435 }; 2436 }; 2437 2438 pcie1_phy: phy@1c0e000 { 2439 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy"; 2440 reg = <0 0x01c0e000 0 0x1000>; 2441 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 2442 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2443 <&gcc GCC_PCIE_CLKREF_EN>, 2444 <&gcc GCC_PCIE1_PHY_RCHNG_CLK>, 2445 <&gcc GCC_PCIE_1_PIPE_CLK>; 2446 clock-names = "aux", 2447 "cfg_ahb", 2448 "ref", 2449 "refgen", 2450 "pipe"; 2451 2452 clock-output-names = "pcie_1_pipe_clk"; 2453 #clock-cells = <0>; 2454 2455 #phy-cells = <0>; 2456 2457 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 2458 reset-names = "phy"; 2459 2460 assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 2461 assigned-clock-rates = <100000000>; 2462 2463 status = "disabled"; 2464 }; 2465 2466 ufs_mem_hc: ufshc@1d84000 { 2467 compatible = "qcom,sc7280-ufshc", "qcom,ufshc", 2468 "jedec,ufs-2.0"; 2469 reg = <0x0 0x01d84000 0x0 0x3000>; 2470 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2471 phys = <&ufs_mem_phy>; 2472 phy-names = "ufsphy"; 2473 lanes-per-direction = <2>; 2474 #reset-cells = <1>; 2475 resets = <&gcc GCC_UFS_PHY_BCR>; 2476 reset-names = "rst"; 2477 2478 power-domains = <&gcc GCC_UFS_PHY_GDSC>; 2479 required-opps = <&rpmhpd_opp_nom>; 2480 2481 iommus = <&apps_smmu 0x80 0x0>; 2482 dma-coherent; 2483 2484 interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS 2485 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 2486 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2487 &cnoc2 SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>; 2488 interconnect-names = "ufs-ddr", "cpu-ufs"; 2489 2490 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 2491 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2492 <&gcc GCC_UFS_PHY_AHB_CLK>, 2493 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2494 <&rpmhcc RPMH_CXO_CLK>, 2495 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2496 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2497 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 2498 clock-names = "core_clk", 2499 "bus_aggr_clk", 2500 "iface_clk", 2501 "core_clk_unipro", 2502 "ref_clk", 2503 "tx_lane0_sync_clk", 2504 "rx_lane0_sync_clk", 2505 "rx_lane1_sync_clk"; 2506 2507 operating-points-v2 = <&ufs_opp_table>; 2508 2509 qcom,ice = <&ice>; 2510 2511 status = "disabled"; 2512 2513 ufs_opp_table: opp-table { 2514 compatible = "operating-points-v2"; 2515 2516 opp-75000000 { 2517 opp-hz = /bits/ 64 <75000000>, 2518 /bits/ 64 <0>, 2519 /bits/ 64 <0>, 2520 /bits/ 64 <75000000>, 2521 /bits/ 64 <0>, 2522 /bits/ 64 <0>, 2523 /bits/ 64 <0>, 2524 /bits/ 64 <0>; 2525 required-opps = <&rpmhpd_opp_low_svs>; 2526 }; 2527 2528 opp-150000000 { 2529 opp-hz = /bits/ 64 <150000000>, 2530 /bits/ 64 <0>, 2531 /bits/ 64 <0>, 2532 /bits/ 64 <150000000>, 2533 /bits/ 64 <0>, 2534 /bits/ 64 <0>, 2535 /bits/ 64 <0>, 2536 /bits/ 64 <0>; 2537 required-opps = <&rpmhpd_opp_svs>; 2538 }; 2539 2540 opp-300000000 { 2541 opp-hz = /bits/ 64 <300000000>, 2542 /bits/ 64 <0>, 2543 /bits/ 64 <0>, 2544 /bits/ 64 <300000000>, 2545 /bits/ 64 <0>, 2546 /bits/ 64 <0>, 2547 /bits/ 64 <0>, 2548 /bits/ 64 <0>; 2549 required-opps = <&rpmhpd_opp_nom>; 2550 }; 2551 }; 2552 }; 2553 2554 ufs_mem_phy: phy@1d87000 { 2555 compatible = "qcom,sc7280-qmp-ufs-phy"; 2556 reg = <0x0 0x01d87000 0x0 0xe00>; 2557 clocks = <&rpmhcc RPMH_CXO_CLK>, 2558 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 2559 <&gcc GCC_UFS_1_CLKREF_EN>; 2560 clock-names = "ref", "ref_aux", "qref"; 2561 2562 power-domains = <&rpmhpd SC7280_MX>; 2563 2564 resets = <&ufs_mem_hc 0>; 2565 reset-names = "ufsphy"; 2566 2567 #clock-cells = <1>; 2568 #phy-cells = <0>; 2569 2570 status = "disabled"; 2571 }; 2572 2573 ice: crypto@1d88000 { 2574 compatible = "qcom,sc7280-inline-crypto-engine", 2575 "qcom,inline-crypto-engine"; 2576 reg = <0 0x01d88000 0 0x8000>; 2577 clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 2578 }; 2579 2580 cryptobam: dma-controller@1dc4000 { 2581 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 2582 reg = <0x0 0x01dc4000 0x0 0x28000>; 2583 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 2584 #dma-cells = <1>; 2585 iommus = <&apps_smmu 0x4e4 0x0011>, 2586 <&apps_smmu 0x4e6 0x0011>; 2587 qcom,ee = <0>; 2588 qcom,controlled-remotely; 2589 num-channels = <16>; 2590 qcom,num-ees = <4>; 2591 }; 2592 2593 crypto: crypto@1dfa000 { 2594 compatible = "qcom,sc7280-qce", "qcom,sm8150-qce", "qcom,qce"; 2595 reg = <0x0 0x01dfa000 0x0 0x6000>; 2596 dmas = <&cryptobam 4>, <&cryptobam 5>; 2597 dma-names = "rx", "tx"; 2598 iommus = <&apps_smmu 0x4e4 0x0011>, 2599 <&apps_smmu 0x4e4 0x0011>; 2600 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; 2601 interconnect-names = "memory"; 2602 }; 2603 2604 ipa: ipa@1e40000 { 2605 compatible = "qcom,sc7280-ipa"; 2606 2607 iommus = <&apps_smmu 0x480 0x0>, 2608 <&apps_smmu 0x482 0x0>; 2609 reg = <0 0x01e40000 0 0x8000>, 2610 <0 0x01e50000 0 0x4ad0>, 2611 <0 0x01e04000 0 0x23000>; 2612 reg-names = "ipa-reg", 2613 "ipa-shared", 2614 "gsi"; 2615 2616 interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>, 2617 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 2618 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2619 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 2620 interrupt-names = "ipa", 2621 "gsi", 2622 "ipa-clock-query", 2623 "ipa-setup-ready"; 2624 2625 clocks = <&rpmhcc RPMH_IPA_CLK>; 2626 clock-names = "core"; 2627 2628 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 2629 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_IPA_CFG 0>; 2630 interconnect-names = "memory", 2631 "config"; 2632 2633 qcom,qmp = <&aoss_qmp>; 2634 2635 qcom,smem-states = <&ipa_smp2p_out 0>, 2636 <&ipa_smp2p_out 1>; 2637 qcom,smem-state-names = "ipa-clock-enabled-valid", 2638 "ipa-clock-enabled"; 2639 2640 status = "disabled"; 2641 }; 2642 2643 tcsr_mutex: hwlock@1f40000 { 2644 compatible = "qcom,tcsr-mutex"; 2645 reg = <0 0x01f40000 0 0x20000>; 2646 #hwlock-cells = <1>; 2647 }; 2648 2649 tcsr_1: syscon@1f60000 { 2650 compatible = "qcom,sc7280-tcsr", "syscon"; 2651 reg = <0 0x01f60000 0 0x20000>; 2652 }; 2653 2654 tcsr_2: syscon@1fc0000 { 2655 compatible = "qcom,sc7280-tcsr", "syscon"; 2656 reg = <0 0x01fc0000 0 0x30000>; 2657 }; 2658 2659 lpasscc: lpasscc@3000000 { 2660 compatible = "qcom,sc7280-lpasscc"; 2661 reg = <0 0x03000000 0 0x40>, 2662 <0 0x03c04000 0 0x4>; 2663 reg-names = "qdsp6ss", "top_cc"; 2664 clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>; 2665 clock-names = "iface"; 2666 #clock-cells = <1>; 2667 status = "reserved"; /* Owned by ADSP firmware */ 2668 }; 2669 2670 lpass_rx_macro: codec@3200000 { 2671 compatible = "qcom,sc7280-lpass-rx-macro"; 2672 reg = <0 0x03200000 0 0x1000>; 2673 2674 pinctrl-names = "default"; 2675 pinctrl-0 = <&lpass_rx_swr_clk>, <&lpass_rx_swr_data>; 2676 2677 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>, 2678 <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>, 2679 <&lpass_va_macro>; 2680 clock-names = "mclk", "npl", "fsgen"; 2681 2682 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, 2683 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2684 power-domain-names = "macro", "dcodec"; 2685 2686 #clock-cells = <0>; 2687 #sound-dai-cells = <1>; 2688 2689 status = "disabled"; 2690 }; 2691 2692 swr0: soundwire@3210000 { 2693 compatible = "qcom,soundwire-v1.6.0"; 2694 reg = <0 0x03210000 0 0x2000>; 2695 2696 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 2697 clocks = <&lpass_rx_macro>; 2698 clock-names = "iface"; 2699 2700 qcom,din-ports = <0>; 2701 qcom,dout-ports = <5>; 2702 2703 resets = <&lpass_audiocc LPASS_AUDIO_SWR_RX_CGCR>; 2704 reset-names = "swr_audio_cgcr"; 2705 2706 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>; 2707 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x3f 0x1f 0x03 0x03>; 2708 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x01>; 2709 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>; 2710 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; 2711 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>; 2712 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>; 2713 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>; 2714 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>; 2715 2716 #sound-dai-cells = <1>; 2717 #address-cells = <2>; 2718 #size-cells = <0>; 2719 2720 status = "disabled"; 2721 }; 2722 2723 lpass_tx_macro: codec@3220000 { 2724 compatible = "qcom,sc7280-lpass-tx-macro"; 2725 reg = <0 0x03220000 0 0x1000>; 2726 2727 pinctrl-names = "default"; 2728 pinctrl-0 = <&lpass_tx_swr_clk>, <&lpass_tx_swr_data>; 2729 2730 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>, 2731 <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>, 2732 <&lpass_va_macro>; 2733 clock-names = "mclk", "npl", "fsgen"; 2734 2735 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, 2736 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2737 power-domain-names = "macro", "dcodec"; 2738 2739 #clock-cells = <0>; 2740 #sound-dai-cells = <1>; 2741 2742 status = "disabled"; 2743 }; 2744 2745 swr1: soundwire@3230000 { 2746 compatible = "qcom,soundwire-v1.6.0"; 2747 reg = <0 0x03230000 0 0x2000>; 2748 2749 interrupts-extended = <&intc GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, 2750 <&pdc 130 IRQ_TYPE_LEVEL_HIGH>; 2751 clocks = <&lpass_tx_macro>; 2752 clock-names = "iface"; 2753 2754 qcom,din-ports = <3>; 2755 qcom,dout-ports = <0>; 2756 2757 resets = <&lpass_audiocc LPASS_AUDIO_SWR_TX_CGCR>; 2758 reset-names = "swr_audio_cgcr"; 2759 2760 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x03 0x03>; 2761 qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02>; 2762 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00>; 2763 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff>; 2764 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff>; 2765 qcom,ports-word-length = /bits/ 8 <0xff 0x00 0xff>; 2766 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff>; 2767 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff>; 2768 qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00>; 2769 2770 #sound-dai-cells = <1>; 2771 #address-cells = <2>; 2772 #size-cells = <0>; 2773 2774 status = "disabled"; 2775 }; 2776 2777 lpass_wsa_macro: codec@3240000 { 2778 compatible = "qcom,sc7280-lpass-wsa-macro"; 2779 reg = <0x0 0x03240000 0x0 0x1000>; 2780 2781 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>, 2782 <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>, 2783 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2784 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2785 <&lpass_va_macro>; 2786 clock-names = "mclk", 2787 "npl", 2788 "macro", 2789 "dcodec", 2790 "fsgen"; 2791 2792 pinctrl-0 = <&lpass_wsa_swr_clk>, <&lpass_wsa_swr_data>; 2793 pinctrl-names = "default"; 2794 2795 #clock-cells = <0>; 2796 clock-output-names = "mclk"; 2797 #sound-dai-cells = <1>; 2798 2799 status = "disabled"; 2800 }; 2801 2802 swr2: soundwire@3250000 { 2803 compatible = "qcom,soundwire-v1.6.0"; 2804 reg = <0x0 0x03250000 0x0 0x2000>; 2805 2806 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 2807 clocks = <&lpass_wsa_macro>; 2808 clock-names = "iface"; 2809 2810 resets = <&lpass_audiocc LPASS_AUDIO_SWR_WSA_CGCR>; 2811 reset-names = "swr_audio_cgcr"; 2812 2813 qcom,din-ports = <2>; 2814 qcom,dout-ports = <6>; 2815 2816 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 2817 0x1f 0x3f 0x0f 0x0f>; 2818 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>; 2819 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>; 2820 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2821 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2822 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2823 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 2824 0xff 0xff>; 2825 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 2826 0xff 0xff>; 2827 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 2828 0xff 0xff>; 2829 2830 #address-cells = <2>; 2831 #size-cells = <0>; 2832 #sound-dai-cells = <1>; 2833 2834 status = "disabled"; 2835 }; 2836 2837 lpass_audiocc: clock-controller@3300000 { 2838 compatible = "qcom,sc7280-lpassaudiocc"; 2839 reg = <0 0x03300000 0 0x30000>, 2840 <0 0x032a9000 0 0x1000>; 2841 clocks = <&rpmhcc RPMH_CXO_CLK>, 2842 <&lpass_aon LPASS_AON_CC_MAIN_RCG_CLK_SRC>; 2843 clock-names = "bi_tcxo", "lpass_aon_cc_main_rcg_clk_src"; 2844 power-domains = <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2845 #clock-cells = <1>; 2846 #power-domain-cells = <1>; 2847 #reset-cells = <1>; 2848 }; 2849 2850 lpass_va_macro: codec@3370000 { 2851 compatible = "qcom,sc7280-lpass-va-macro"; 2852 reg = <0 0x03370000 0 0x1000>; 2853 2854 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>; 2855 clock-names = "mclk"; 2856 2857 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, 2858 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2859 power-domain-names = "macro", "dcodec"; 2860 2861 #clock-cells = <0>; 2862 #sound-dai-cells = <1>; 2863 2864 status = "disabled"; 2865 }; 2866 2867 lpass_aon: clock-controller@3380000 { 2868 compatible = "qcom,sc7280-lpassaoncc"; 2869 reg = <0 0x03380000 0 0x30000>; 2870 clocks = <&rpmhcc RPMH_CXO_CLK>, 2871 <&rpmhcc RPMH_CXO_CLK_A>, 2872 <&lpass_core LPASS_CORE_CC_CORE_CLK>; 2873 clock-names = "bi_tcxo", "bi_tcxo_ao", "iface"; 2874 #clock-cells = <1>; 2875 #power-domain-cells = <1>; 2876 status = "reserved"; /* Owned by ADSP firmware */ 2877 }; 2878 2879 lpass_core: clock-controller@3900000 { 2880 compatible = "qcom,sc7280-lpasscorecc"; 2881 reg = <0 0x03900000 0 0x50000>; 2882 clocks = <&rpmhcc RPMH_CXO_CLK>; 2883 clock-names = "bi_tcxo"; 2884 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>; 2885 #clock-cells = <1>; 2886 #power-domain-cells = <1>; 2887 status = "reserved"; /* Owned by ADSP firmware */ 2888 }; 2889 2890 lpass_cpu: audio@3987000 { 2891 compatible = "qcom,sc7280-lpass-cpu"; 2892 2893 reg = <0 0x03987000 0 0x68000>, 2894 <0 0x03b00000 0 0x29000>, 2895 <0 0x03260000 0 0xc000>, 2896 <0 0x03280000 0 0x29000>, 2897 <0 0x03340000 0 0x29000>, 2898 <0 0x0336c000 0 0x3000>; 2899 reg-names = "lpass-hdmiif", 2900 "lpass-lpaif", 2901 "lpass-rxtx-cdc-dma-lpm", 2902 "lpass-rxtx-lpaif", 2903 "lpass-va-lpaif", 2904 "lpass-va-cdc-dma-lpm"; 2905 2906 iommus = <&apps_smmu 0x1820 0>, 2907 <&apps_smmu 0x1821 0>, 2908 <&apps_smmu 0x1832 0>; 2909 2910 power-domains = <&rpmhpd SC7280_LCX>; 2911 power-domain-names = "lcx"; 2912 required-opps = <&rpmhpd_opp_nom>; 2913 2914 clocks = <&lpass_aon LPASS_AON_CC_AUDIO_HM_H_CLK>, 2915 <&lpass_core LPASS_CORE_CC_EXT_MCLK0_CLK>, 2916 <&lpass_core LPASS_CORE_CC_SYSNOC_MPORT_CORE_CLK>, 2917 <&lpass_core LPASS_CORE_CC_EXT_IF0_IBIT_CLK>, 2918 <&lpass_core LPASS_CORE_CC_EXT_IF1_IBIT_CLK>, 2919 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM_CLK>, 2920 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM0_CLK>, 2921 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM1_CLK>, 2922 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM2_CLK>, 2923 <&lpass_aon LPASS_AON_CC_VA_MEM0_CLK>; 2924 clock-names = "aon_cc_audio_hm_h", 2925 "audio_cc_ext_mclk0", 2926 "core_cc_sysnoc_mport_core", 2927 "core_cc_ext_if0_ibit", 2928 "core_cc_ext_if1_ibit", 2929 "audio_cc_codec_mem", 2930 "audio_cc_codec_mem0", 2931 "audio_cc_codec_mem1", 2932 "audio_cc_codec_mem2", 2933 "aon_cc_va_mem0"; 2934 2935 #sound-dai-cells = <1>; 2936 #address-cells = <1>; 2937 #size-cells = <0>; 2938 2939 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 2940 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 2941 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 2942 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 2943 interrupt-names = "lpass-irq-lpaif", 2944 "lpass-irq-hdmi", 2945 "lpass-irq-vaif", 2946 "lpass-irq-rxtxif"; 2947 2948 status = "disabled"; 2949 }; 2950 2951 slimbam: dma-controller@3a84000 { 2952 compatible = "qcom,bam-v1.7.0"; 2953 reg = <0 0x03a84000 0 0x20000>; 2954 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 2955 #dma-cells = <1>; 2956 qcom,controlled-remotely; 2957 num-channels = <31>; 2958 qcom,ee = <1>; 2959 qcom,num-ees = <2>; 2960 iommus = <&apps_smmu 0x1826 0x0>; 2961 status = "disabled"; 2962 }; 2963 2964 slim: slim-ngd@3ac0000 { 2965 compatible = "qcom,slim-ngd-v1.5.0"; 2966 reg = <0 0x03ac0000 0 0x2c000>; 2967 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 2968 dmas = <&slimbam 3>, <&slimbam 4>; 2969 dma-names = "rx", "tx"; 2970 iommus = <&apps_smmu 0x1826 0x0>; 2971 #address-cells = <1>; 2972 #size-cells = <0>; 2973 status = "disabled"; 2974 }; 2975 2976 lpass_hm: clock-controller@3c00000 { 2977 compatible = "qcom,sc7280-lpasshm"; 2978 reg = <0 0x03c00000 0 0x28>; 2979 clocks = <&rpmhcc RPMH_CXO_CLK>; 2980 clock-names = "bi_tcxo"; 2981 #clock-cells = <1>; 2982 #power-domain-cells = <1>; 2983 status = "reserved"; /* Owned by ADSP firmware */ 2984 }; 2985 2986 lpass_ag_noc: interconnect@3c40000 { 2987 reg = <0 0x03c40000 0 0xf080>; 2988 compatible = "qcom,sc7280-lpass-ag-noc"; 2989 #interconnect-cells = <2>; 2990 qcom,bcm-voters = <&apps_bcm_voter>; 2991 }; 2992 2993 lpass_tlmm: pinctrl@33c0000 { 2994 compatible = "qcom,sc7280-lpass-lpi-pinctrl"; 2995 reg = <0 0x033c0000 0x0 0x20000>, 2996 <0 0x03550000 0x0 0x10000>; 2997 gpio-controller; 2998 #gpio-cells = <2>; 2999 gpio-ranges = <&lpass_tlmm 0 0 15>; 3000 3001 lpass_dmic01_clk: dmic01-clk-state { 3002 pins = "gpio6"; 3003 function = "dmic1_clk"; 3004 drive-strength = <8>; 3005 bias-disable; 3006 }; 3007 3008 lpass_dmic01_data: dmic01-data-state { 3009 pins = "gpio7"; 3010 function = "dmic1_data"; 3011 drive-strength = <8>; 3012 bias-pull-down; 3013 }; 3014 3015 lpass_dmic23_clk: dmic23-clk-state { 3016 pins = "gpio8"; 3017 function = "dmic2_clk"; 3018 drive-strength = <8>; 3019 bias-disable; 3020 }; 3021 3022 lpass_dmic23_data: dmic23-data-state { 3023 pins = "gpio9"; 3024 function = "dmic2_data"; 3025 drive-strength = <8>; 3026 bias-pull-down; 3027 }; 3028 3029 lpass_rx_swr_clk: rx-swr-clk-state { 3030 pins = "gpio3"; 3031 function = "swr_rx_clk"; 3032 drive-strength = <2>; 3033 slew-rate = <1>; 3034 bias-disable; 3035 }; 3036 3037 lpass_rx_swr_data: rx-swr-data-state { 3038 pins = "gpio4", "gpio5"; 3039 function = "swr_rx_data"; 3040 drive-strength = <2>; 3041 slew-rate = <1>; 3042 bias-bus-hold; 3043 }; 3044 3045 lpass_tx_swr_clk: tx-swr-clk-state { 3046 pins = "gpio0"; 3047 function = "swr_tx_clk"; 3048 drive-strength = <2>; 3049 slew-rate = <1>; 3050 bias-disable; 3051 }; 3052 3053 lpass_tx_swr_data: tx-swr-data-state { 3054 pins = "gpio1", "gpio2", "gpio14"; 3055 function = "swr_tx_data"; 3056 drive-strength = <2>; 3057 slew-rate = <1>; 3058 bias-bus-hold; 3059 }; 3060 3061 lpass_wsa_swr_clk: wsa-swr-clk-state { 3062 pins = "gpio10"; 3063 function = "wsa_swr_clk"; 3064 drive-strength = <2>; 3065 slew-rate = <1>; 3066 bias-disable; 3067 }; 3068 3069 lpass_wsa_swr_data: wsa-swr-data-state { 3070 pins = "gpio11"; 3071 function = "wsa_swr_data"; 3072 drive-strength = <2>; 3073 slew-rate = <1>; 3074 bias-bus-hold; 3075 }; 3076 }; 3077 3078 gpu: gpu@3d00000 { 3079 compatible = "qcom,adreno-635.0", "qcom,adreno"; 3080 reg = <0 0x03d00000 0 0x40000>, 3081 <0 0x03d9e000 0 0x1000>, 3082 <0 0x03d61000 0 0x800>; 3083 reg-names = "kgsl_3d0_reg_memory", 3084 "cx_mem", 3085 "cx_dbgc"; 3086 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 3087 iommus = <&adreno_smmu 0 0x400>, 3088 <&adreno_smmu 1 0x400>; 3089 operating-points-v2 = <&gpu_opp_table>; 3090 qcom,gmu = <&gmu>; 3091 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; 3092 interconnect-names = "gfx-mem"; 3093 #cooling-cells = <2>; 3094 3095 nvmem-cells = <&gpu_speed_bin>; 3096 nvmem-cell-names = "speed_bin"; 3097 3098 status = "disabled"; 3099 3100 gpu_zap_shader: zap-shader { 3101 memory-region = <&gpu_zap_mem>; 3102 }; 3103 3104 gpu_opp_table: opp-table { 3105 compatible = "operating-points-v2"; 3106 3107 opp-315000000 { 3108 opp-hz = /bits/ 64 <315000000>; 3109 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3110 opp-peak-kBps = <1804000>; 3111 opp-supported-hw = <0x17>; 3112 }; 3113 3114 opp-450000000 { 3115 opp-hz = /bits/ 64 <450000000>; 3116 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3117 opp-peak-kBps = <4068000>; 3118 opp-supported-hw = <0x17>; 3119 }; 3120 3121 /* Only applicable for SKUs which has 550Mhz as Fmax */ 3122 opp-550000000-0 { 3123 opp-hz = /bits/ 64 <550000000>; 3124 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3125 opp-peak-kBps = <8368000>; 3126 opp-supported-hw = <0x01>; 3127 }; 3128 3129 opp-550000000-1 { 3130 opp-hz = /bits/ 64 <550000000>; 3131 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3132 opp-peak-kBps = <6832000>; 3133 opp-supported-hw = <0x16>; 3134 }; 3135 3136 opp-608000000 { 3137 opp-hz = /bits/ 64 <608000000>; 3138 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 3139 opp-peak-kBps = <8368000>; 3140 opp-supported-hw = <0x16>; 3141 }; 3142 3143 opp-700000000 { 3144 opp-hz = /bits/ 64 <700000000>; 3145 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3146 opp-peak-kBps = <8532000>; 3147 opp-supported-hw = <0x06>; 3148 }; 3149 3150 opp-812000000 { 3151 opp-hz = /bits/ 64 <812000000>; 3152 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3153 opp-peak-kBps = <8532000>; 3154 opp-supported-hw = <0x06>; 3155 }; 3156 3157 opp-840000000 { 3158 opp-hz = /bits/ 64 <840000000>; 3159 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3160 opp-peak-kBps = <8532000>; 3161 opp-supported-hw = <0x02>; 3162 }; 3163 3164 opp-900000000 { 3165 opp-hz = /bits/ 64 <900000000>; 3166 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3167 opp-peak-kBps = <8532000>; 3168 opp-supported-hw = <0x02>; 3169 }; 3170 }; 3171 }; 3172 3173 gmu: gmu@3d6a000 { 3174 compatible = "qcom,adreno-gmu-635.0", "qcom,adreno-gmu"; 3175 reg = <0 0x03d6a000 0 0x34000>, 3176 <0 0x3de0000 0 0x10000>, 3177 <0 0x0b290000 0 0x10000>; 3178 reg-names = "gmu", "rscc", "gmu_pdc"; 3179 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 3180 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 3181 interrupt-names = "hfi", "gmu"; 3182 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 3183 <&gpucc GPU_CC_CXO_CLK>, 3184 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 3185 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 3186 <&gpucc GPU_CC_AHB_CLK>, 3187 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 3188 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; 3189 clock-names = "gmu", 3190 "cxo", 3191 "axi", 3192 "memnoc", 3193 "ahb", 3194 "hub", 3195 "smmu_vote"; 3196 power-domains = <&gpucc GPU_CC_CX_GDSC>, 3197 <&gpucc GPU_CC_GX_GDSC>; 3198 power-domain-names = "cx", 3199 "gx"; 3200 iommus = <&adreno_smmu 5 0x400>; 3201 operating-points-v2 = <&gmu_opp_table>; 3202 3203 gmu_opp_table: opp-table { 3204 compatible = "operating-points-v2"; 3205 3206 opp-200000000 { 3207 opp-hz = /bits/ 64 <200000000>; 3208 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3209 }; 3210 }; 3211 }; 3212 3213 gpucc: clock-controller@3d90000 { 3214 compatible = "qcom,sc7280-gpucc"; 3215 reg = <0 0x03d90000 0 0x9000>; 3216 clocks = <&rpmhcc RPMH_CXO_CLK>, 3217 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 3218 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 3219 clock-names = "bi_tcxo", 3220 "gcc_gpu_gpll0_clk_src", 3221 "gcc_gpu_gpll0_div_clk_src"; 3222 #clock-cells = <1>; 3223 #reset-cells = <1>; 3224 #power-domain-cells = <1>; 3225 }; 3226 3227 dma@117f000 { 3228 compatible = "qcom,sc7280-dcc", "qcom,dcc"; 3229 reg = <0x0 0x0117f000 0x0 0x1000>, 3230 <0x0 0x01112000 0x0 0x6000>; 3231 }; 3232 3233 adreno_smmu: iommu@3da0000 { 3234 compatible = "qcom,sc7280-smmu-500", "qcom,adreno-smmu", 3235 "qcom,smmu-500", "arm,mmu-500"; 3236 reg = <0 0x03da0000 0 0x20000>; 3237 #iommu-cells = <2>; 3238 #global-interrupts = <2>; 3239 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 3240 <GIC_SPI 675 IRQ_TYPE_LEVEL_HIGH>, 3241 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 3242 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 3243 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 3244 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 3245 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 3246 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 3247 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 3248 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 3249 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 3250 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; 3251 3252 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 3253 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 3254 <&gpucc GPU_CC_AHB_CLK>, 3255 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 3256 <&gpucc GPU_CC_CX_GMU_CLK>, 3257 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 3258 <&gpucc GPU_CC_HUB_AON_CLK>; 3259 clock-names = "gcc_gpu_memnoc_gfx_clk", 3260 "gcc_gpu_snoc_dvm_gfx_clk", 3261 "gpu_cc_ahb_clk", 3262 "gpu_cc_hlos1_vote_gpu_smmu_clk", 3263 "gpu_cc_cx_gmu_clk", 3264 "gpu_cc_hub_cx_int_clk", 3265 "gpu_cc_hub_aon_clk"; 3266 3267 power-domains = <&gpucc GPU_CC_CX_GDSC>; 3268 dma-coherent; 3269 }; 3270 3271 gfx_0_tbu: tbu@3dd9000 { 3272 compatible = "qcom,sc7280-tbu"; 3273 reg = <0x0 0x3dd9000 0x0 0x1000>; 3274 qcom,stream-id-range = <&adreno_smmu 0x0 0x400>; 3275 }; 3276 3277 gfx_1_tbu: tbu@3ddd000 { 3278 compatible = "qcom,sc7280-tbu"; 3279 reg = <0x0 0x3ddd000 0x0 0x1000>; 3280 qcom,stream-id-range = <&adreno_smmu 0x400 0x400>; 3281 }; 3282 3283 remoteproc_mpss: remoteproc@4080000 { 3284 compatible = "qcom,sc7280-mpss-pas"; 3285 reg = <0 0x04080000 0 0x10000>; 3286 3287 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 3288 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3289 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3290 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3291 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 3292 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 3293 interrupt-names = "wdog", "fatal", "ready", "handover", 3294 "stop-ack", "shutdown-ack"; 3295 3296 clocks = <&rpmhcc RPMH_CXO_CLK>; 3297 clock-names = "xo"; 3298 3299 power-domains = <&rpmhpd SC7280_CX>, 3300 <&rpmhpd SC7280_MSS>; 3301 power-domain-names = "cx", "mss"; 3302 3303 memory-region = <&mpss_mem>; 3304 3305 qcom,qmp = <&aoss_qmp>; 3306 3307 qcom,smem-states = <&modem_smp2p_out 0>; 3308 qcom,smem-state-names = "stop"; 3309 3310 status = "disabled"; 3311 3312 glink-edge { 3313 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 3314 IPCC_MPROC_SIGNAL_GLINK_QMP 3315 IRQ_TYPE_EDGE_RISING>; 3316 mboxes = <&ipcc IPCC_CLIENT_MPSS 3317 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3318 label = "modem"; 3319 qcom,remote-pid = <1>; 3320 }; 3321 }; 3322 3323 stm@6002000 { 3324 compatible = "arm,coresight-stm", "arm,primecell"; 3325 reg = <0 0x06002000 0 0x1000>, 3326 <0 0x16280000 0 0x180000>; 3327 reg-names = "stm-base", "stm-stimulus-base"; 3328 3329 clocks = <&aoss_qmp>; 3330 clock-names = "apb_pclk"; 3331 3332 out-ports { 3333 port { 3334 stm_out: endpoint { 3335 remote-endpoint = <&funnel0_in7>; 3336 }; 3337 }; 3338 }; 3339 }; 3340 3341 tpda@6004000 { 3342 compatible = "qcom,coresight-tpda", "arm,primecell"; 3343 reg = <0x0 0x06004000 0x0 0x1000>; 3344 3345 clocks = <&aoss_qmp>; 3346 clock-names = "apb_pclk"; 3347 3348 in-ports { 3349 #address-cells = <1>; 3350 #size-cells = <0>; 3351 3352 port@1c { 3353 reg = <0x1c>; 3354 3355 qdss_tpda_in28: endpoint { 3356 remote-endpoint = <&spdm_tpdm_out>; 3357 }; 3358 }; 3359 }; 3360 3361 out-ports { 3362 port { 3363 qdss_tpda_out: endpoint { 3364 remote-endpoint = <&qdss_dl_funnel_in0>; 3365 }; 3366 }; 3367 }; 3368 }; 3369 3370 funnel@6005000 { 3371 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3372 reg = <0x0 0x06005000 0x0 0x1000>; 3373 3374 clocks = <&aoss_qmp>; 3375 clock-names = "apb_pclk"; 3376 3377 in-ports { 3378 port { 3379 qdss_dl_funnel_in0: endpoint { 3380 remote-endpoint = <&qdss_tpda_out>; 3381 }; 3382 }; 3383 }; 3384 3385 out-ports { 3386 port { 3387 qdss_dl_funnel_out: endpoint { 3388 remote-endpoint = <&funnel0_in6>; 3389 }; 3390 }; 3391 }; 3392 }; 3393 3394 tpdm@600f000 { 3395 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3396 reg = <0x0 0x0600f000 0x0 0x1000>; 3397 3398 clocks = <&aoss_qmp>; 3399 clock-names = "apb_pclk"; 3400 3401 qcom,cmb-element-bits = <32>; 3402 qcom,cmb-msrs-num = <32>; 3403 3404 out-ports { 3405 port { 3406 spdm_tpdm_out: endpoint { 3407 remote-endpoint = <&qdss_tpda_in28>; 3408 }; 3409 }; 3410 }; 3411 }; 3412 3413 cti@6010000 { 3414 compatible = "arm,coresight-cti", "arm,primecell"; 3415 reg = <0x0 0x06010000 0x0 0x1000>; 3416 3417 clocks = <&aoss_qmp>; 3418 clock-names = "apb_pclk"; 3419 }; 3420 3421 funnel@6041000 { 3422 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3423 reg = <0 0x06041000 0 0x1000>; 3424 3425 clocks = <&aoss_qmp>; 3426 clock-names = "apb_pclk"; 3427 3428 out-ports { 3429 port { 3430 funnel0_out: endpoint { 3431 remote-endpoint = <&merge_funnel_in0>; 3432 }; 3433 }; 3434 }; 3435 3436 in-ports { 3437 #address-cells = <1>; 3438 #size-cells = <0>; 3439 3440 port@6 { 3441 reg = <6>; 3442 3443 funnel0_in6: endpoint { 3444 remote-endpoint = <&qdss_dl_funnel_out>; 3445 }; 3446 }; 3447 3448 port@7 { 3449 reg = <7>; 3450 funnel0_in7: endpoint { 3451 remote-endpoint = <&stm_out>; 3452 }; 3453 }; 3454 }; 3455 }; 3456 3457 funnel@6042000 { 3458 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3459 reg = <0 0x06042000 0 0x1000>; 3460 3461 clocks = <&aoss_qmp>; 3462 clock-names = "apb_pclk"; 3463 3464 out-ports { 3465 port { 3466 funnel1_out: endpoint { 3467 remote-endpoint = <&merge_funnel_in1>; 3468 }; 3469 }; 3470 }; 3471 3472 in-ports { 3473 #address-cells = <1>; 3474 #size-cells = <0>; 3475 3476 port@4 { 3477 reg = <4>; 3478 funnel1_in4: endpoint { 3479 remote-endpoint = <&apss_merge_funnel_out>; 3480 }; 3481 }; 3482 }; 3483 }; 3484 3485 funnel@6045000 { 3486 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3487 reg = <0 0x06045000 0 0x1000>; 3488 3489 clocks = <&aoss_qmp>; 3490 clock-names = "apb_pclk"; 3491 3492 out-ports { 3493 port { 3494 merge_funnel_out: endpoint { 3495 remote-endpoint = <&swao_funnel_in>; 3496 }; 3497 }; 3498 }; 3499 3500 in-ports { 3501 #address-cells = <1>; 3502 #size-cells = <0>; 3503 3504 port@0 { 3505 reg = <0>; 3506 merge_funnel_in0: endpoint { 3507 remote-endpoint = <&funnel0_out>; 3508 }; 3509 }; 3510 3511 port@1 { 3512 reg = <1>; 3513 merge_funnel_in1: endpoint { 3514 remote-endpoint = <&funnel1_out>; 3515 }; 3516 }; 3517 }; 3518 }; 3519 3520 replicator@6046000 { 3521 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 3522 reg = <0 0x06046000 0 0x1000>; 3523 3524 clocks = <&aoss_qmp>; 3525 clock-names = "apb_pclk"; 3526 3527 out-ports { 3528 port { 3529 replicator_out: endpoint { 3530 remote-endpoint = <&etr_in>; 3531 }; 3532 }; 3533 }; 3534 3535 in-ports { 3536 port { 3537 replicator_in: endpoint { 3538 remote-endpoint = <&swao_replicator_out>; 3539 }; 3540 }; 3541 }; 3542 }; 3543 3544 etr@6048000 { 3545 compatible = "arm,coresight-tmc", "arm,primecell"; 3546 reg = <0 0x06048000 0 0x1000>; 3547 iommus = <&apps_smmu 0x04c0 0>; 3548 3549 clocks = <&aoss_qmp>; 3550 clock-names = "apb_pclk"; 3551 arm,scatter-gather; 3552 3553 in-ports { 3554 port { 3555 etr_in: endpoint { 3556 remote-endpoint = <&replicator_out>; 3557 }; 3558 }; 3559 }; 3560 }; 3561 3562 cti@6b00000 { 3563 compatible = "arm,coresight-cti", "arm,primecell"; 3564 reg = <0x0 0x06b00000 0x0 0x1000>; 3565 3566 clocks = <&aoss_qmp>; 3567 clock-names = "apb_pclk"; 3568 }; 3569 3570 cti@6b01000 { 3571 compatible = "arm,coresight-cti", "arm,primecell"; 3572 reg = <0x0 0x06b01000 0x0 0x1000>; 3573 3574 clocks = <&aoss_qmp>; 3575 clock-names = "apb_pclk"; 3576 }; 3577 3578 cti@6b02000 { 3579 compatible = "arm,coresight-cti", "arm,primecell"; 3580 reg = <0x0 0x06b02000 0x0 0x1000>; 3581 3582 clocks = <&aoss_qmp>; 3583 clock-names = "apb_pclk"; 3584 }; 3585 3586 cti@6b03000 { 3587 compatible = "arm,coresight-cti", "arm,primecell"; 3588 reg = <0x0 0x06b03000 0x0 0x1000>; 3589 3590 clocks = <&aoss_qmp>; 3591 clock-names = "apb_pclk"; 3592 }; 3593 3594 funnel@6b04000 { 3595 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3596 reg = <0 0x06b04000 0 0x1000>; 3597 3598 clocks = <&aoss_qmp>; 3599 clock-names = "apb_pclk"; 3600 3601 out-ports { 3602 port { 3603 swao_funnel_out: endpoint { 3604 remote-endpoint = <&etf_in>; 3605 }; 3606 }; 3607 }; 3608 3609 in-ports { 3610 #address-cells = <1>; 3611 #size-cells = <0>; 3612 3613 port@6 { 3614 reg = <6>; 3615 3616 swao_funnel_in6: endpoint { 3617 remote-endpoint = <&aoss_tpda_out>; 3618 }; 3619 }; 3620 3621 port@7 { 3622 reg = <7>; 3623 swao_funnel_in: endpoint { 3624 remote-endpoint = <&merge_funnel_out>; 3625 }; 3626 }; 3627 }; 3628 }; 3629 3630 etf@6b05000 { 3631 compatible = "arm,coresight-tmc", "arm,primecell"; 3632 reg = <0 0x06b05000 0 0x1000>; 3633 3634 clocks = <&aoss_qmp>; 3635 clock-names = "apb_pclk"; 3636 3637 out-ports { 3638 port { 3639 etf_out: endpoint { 3640 remote-endpoint = <&swao_replicator_in>; 3641 }; 3642 }; 3643 }; 3644 3645 in-ports { 3646 port { 3647 etf_in: endpoint { 3648 remote-endpoint = <&swao_funnel_out>; 3649 }; 3650 }; 3651 }; 3652 }; 3653 3654 replicator@6b06000 { 3655 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 3656 reg = <0 0x06b06000 0 0x1000>; 3657 3658 clocks = <&aoss_qmp>; 3659 clock-names = "apb_pclk"; 3660 qcom,replicator-loses-context; 3661 3662 out-ports { 3663 port { 3664 swao_replicator_out: endpoint { 3665 remote-endpoint = <&replicator_in>; 3666 }; 3667 }; 3668 }; 3669 3670 in-ports { 3671 port { 3672 swao_replicator_in: endpoint { 3673 remote-endpoint = <&etf_out>; 3674 }; 3675 }; 3676 }; 3677 }; 3678 3679 tpda@6b08000 { 3680 compatible = "qcom,coresight-tpda", "arm,primecell"; 3681 reg = <0x0 0x06b08000 0x0 0x1000>; 3682 3683 clocks = <&aoss_qmp>; 3684 clock-names = "apb_pclk"; 3685 3686 in-ports { 3687 #address-cells = <1>; 3688 #size-cells = <0>; 3689 3690 port@0 { 3691 reg = <0>; 3692 3693 aoss_tpda_in0: endpoint { 3694 remote-endpoint = <&swao_prio0_tpdm_out>; 3695 }; 3696 }; 3697 3698 port@1 { 3699 reg = <1>; 3700 3701 aoss_tpda_in1: endpoint { 3702 remote-endpoint = <&swao_prio1_tpdm_out>; 3703 }; 3704 }; 3705 3706 port@2 { 3707 reg = <2>; 3708 3709 aoss_tpda_in2: endpoint { 3710 remote-endpoint = <&swao_prio2_tpdm_out>; 3711 }; 3712 }; 3713 3714 port@3 { 3715 reg = <3>; 3716 3717 aoss_tpda_in3: endpoint { 3718 remote-endpoint = <&swao_prio3_tpdm_out>; 3719 }; 3720 }; 3721 3722 port@4 { 3723 reg = <4>; 3724 3725 aoss_tpda_in4: endpoint { 3726 remote-endpoint = <&swao_tpdm_out>; 3727 }; 3728 }; 3729 }; 3730 3731 out-ports { 3732 port { 3733 aoss_tpda_out: endpoint { 3734 remote-endpoint = <&swao_funnel_in6>; 3735 }; 3736 }; 3737 }; 3738 }; 3739 3740 tpdm@6b09000 { 3741 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3742 reg = <0x0 0x06b09000 0x0 0x1000>; 3743 3744 clocks = <&aoss_qmp>; 3745 clock-names = "apb_pclk"; 3746 3747 qcom,cmb-element-bits = <64>; 3748 qcom,cmb-msrs-num = <32>; 3749 3750 out-ports { 3751 port { 3752 swao_prio0_tpdm_out: endpoint { 3753 remote-endpoint = <&aoss_tpda_in0>; 3754 }; 3755 }; 3756 }; 3757 }; 3758 3759 tpdm@6b0a000 { 3760 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3761 reg = <0x0 0x06b0a000 0x0 0x1000>; 3762 3763 clocks = <&aoss_qmp>; 3764 clock-names = "apb_pclk"; 3765 3766 qcom,cmb-element-bits = <64>; 3767 qcom,cmb-msrs-num = <32>; 3768 3769 out-ports { 3770 port { 3771 swao_prio1_tpdm_out: endpoint { 3772 remote-endpoint = <&aoss_tpda_in1>; 3773 }; 3774 }; 3775 }; 3776 }; 3777 3778 tpdm@6b0b000 { 3779 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3780 reg = <0x0 0x06b0b000 0x0 0x1000>; 3781 3782 clocks = <&aoss_qmp>; 3783 clock-names = "apb_pclk"; 3784 3785 qcom,cmb-element-bits = <64>; 3786 qcom,cmb-msrs-num = <32>; 3787 3788 out-ports { 3789 port { 3790 swao_prio2_tpdm_out: endpoint { 3791 remote-endpoint = <&aoss_tpda_in2>; 3792 }; 3793 }; 3794 }; 3795 }; 3796 3797 tpdm@6b0c000 { 3798 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3799 reg = <0x0 0x06b0c000 0x0 0x1000>; 3800 3801 clocks = <&aoss_qmp>; 3802 clock-names = "apb_pclk"; 3803 3804 qcom,cmb-element-bits = <64>; 3805 qcom,cmb-msrs-num = <32>; 3806 3807 out-ports { 3808 port { 3809 swao_prio3_tpdm_out: endpoint { 3810 remote-endpoint = <&aoss_tpda_in3>; 3811 }; 3812 }; 3813 }; 3814 }; 3815 3816 tpdm@6b0d000 { 3817 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3818 reg = <0x0 0x06b0d000 0x0 0x1000>; 3819 3820 clocks = <&aoss_qmp>; 3821 clock-names = "apb_pclk"; 3822 3823 qcom,dsb-element-bits = <32>; 3824 qcom,dsb-msrs-num = <32>; 3825 3826 out-ports { 3827 port { 3828 swao_tpdm_out: endpoint { 3829 remote-endpoint = <&aoss_tpda_in4>; 3830 }; 3831 }; 3832 }; 3833 }; 3834 3835 cti@6b11000 { 3836 compatible = "arm,coresight-cti", "arm,primecell"; 3837 reg = <0x0 0x06b11000 0x0 0x1000>; 3838 3839 clocks = <&aoss_qmp>; 3840 clock-names = "apb_pclk"; 3841 }; 3842 3843 etm@7040000 { 3844 compatible = "arm,coresight-etm4x", "arm,primecell"; 3845 reg = <0 0x07040000 0 0x1000>; 3846 3847 cpu = <&cpu0>; 3848 3849 clocks = <&aoss_qmp>; 3850 clock-names = "apb_pclk"; 3851 arm,coresight-loses-context-with-cpu; 3852 qcom,skip-power-up; 3853 3854 out-ports { 3855 port { 3856 etm0_out: endpoint { 3857 remote-endpoint = <&apss_funnel_in0>; 3858 }; 3859 }; 3860 }; 3861 }; 3862 3863 etm@7140000 { 3864 compatible = "arm,coresight-etm4x", "arm,primecell"; 3865 reg = <0 0x07140000 0 0x1000>; 3866 3867 cpu = <&cpu1>; 3868 3869 clocks = <&aoss_qmp>; 3870 clock-names = "apb_pclk"; 3871 arm,coresight-loses-context-with-cpu; 3872 qcom,skip-power-up; 3873 3874 out-ports { 3875 port { 3876 etm1_out: endpoint { 3877 remote-endpoint = <&apss_funnel_in1>; 3878 }; 3879 }; 3880 }; 3881 }; 3882 3883 etm@7240000 { 3884 compatible = "arm,coresight-etm4x", "arm,primecell"; 3885 reg = <0 0x07240000 0 0x1000>; 3886 3887 cpu = <&cpu2>; 3888 3889 clocks = <&aoss_qmp>; 3890 clock-names = "apb_pclk"; 3891 arm,coresight-loses-context-with-cpu; 3892 qcom,skip-power-up; 3893 3894 out-ports { 3895 port { 3896 etm2_out: endpoint { 3897 remote-endpoint = <&apss_funnel_in2>; 3898 }; 3899 }; 3900 }; 3901 }; 3902 3903 etm@7340000 { 3904 compatible = "arm,coresight-etm4x", "arm,primecell"; 3905 reg = <0 0x07340000 0 0x1000>; 3906 3907 cpu = <&cpu3>; 3908 3909 clocks = <&aoss_qmp>; 3910 clock-names = "apb_pclk"; 3911 arm,coresight-loses-context-with-cpu; 3912 qcom,skip-power-up; 3913 3914 out-ports { 3915 port { 3916 etm3_out: endpoint { 3917 remote-endpoint = <&apss_funnel_in3>; 3918 }; 3919 }; 3920 }; 3921 }; 3922 3923 etm@7440000 { 3924 compatible = "arm,coresight-etm4x", "arm,primecell"; 3925 reg = <0 0x07440000 0 0x1000>; 3926 3927 cpu = <&cpu4>; 3928 3929 clocks = <&aoss_qmp>; 3930 clock-names = "apb_pclk"; 3931 arm,coresight-loses-context-with-cpu; 3932 qcom,skip-power-up; 3933 3934 out-ports { 3935 port { 3936 etm4_out: endpoint { 3937 remote-endpoint = <&apss_funnel_in4>; 3938 }; 3939 }; 3940 }; 3941 }; 3942 3943 etm@7540000 { 3944 compatible = "arm,coresight-etm4x", "arm,primecell"; 3945 reg = <0 0x07540000 0 0x1000>; 3946 3947 cpu = <&cpu5>; 3948 3949 clocks = <&aoss_qmp>; 3950 clock-names = "apb_pclk"; 3951 arm,coresight-loses-context-with-cpu; 3952 qcom,skip-power-up; 3953 3954 out-ports { 3955 port { 3956 etm5_out: endpoint { 3957 remote-endpoint = <&apss_funnel_in5>; 3958 }; 3959 }; 3960 }; 3961 }; 3962 3963 etm@7640000 { 3964 compatible = "arm,coresight-etm4x", "arm,primecell"; 3965 reg = <0 0x07640000 0 0x1000>; 3966 3967 cpu = <&cpu6>; 3968 3969 clocks = <&aoss_qmp>; 3970 clock-names = "apb_pclk"; 3971 arm,coresight-loses-context-with-cpu; 3972 qcom,skip-power-up; 3973 3974 out-ports { 3975 port { 3976 etm6_out: endpoint { 3977 remote-endpoint = <&apss_funnel_in6>; 3978 }; 3979 }; 3980 }; 3981 }; 3982 3983 etm@7740000 { 3984 compatible = "arm,coresight-etm4x", "arm,primecell"; 3985 reg = <0 0x07740000 0 0x1000>; 3986 3987 cpu = <&cpu7>; 3988 3989 clocks = <&aoss_qmp>; 3990 clock-names = "apb_pclk"; 3991 arm,coresight-loses-context-with-cpu; 3992 qcom,skip-power-up; 3993 3994 out-ports { 3995 port { 3996 etm7_out: endpoint { 3997 remote-endpoint = <&apss_funnel_in7>; 3998 }; 3999 }; 4000 }; 4001 }; 4002 4003 funnel@7800000 { /* APSS Funnel */ 4004 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 4005 reg = <0 0x07800000 0 0x1000>; 4006 4007 clocks = <&aoss_qmp>; 4008 clock-names = "apb_pclk"; 4009 4010 out-ports { 4011 port { 4012 apss_funnel_out: endpoint { 4013 remote-endpoint = <&apss_merge_funnel_in>; 4014 }; 4015 }; 4016 }; 4017 4018 in-ports { 4019 #address-cells = <1>; 4020 #size-cells = <0>; 4021 4022 port@0 { 4023 reg = <0>; 4024 apss_funnel_in0: endpoint { 4025 remote-endpoint = <&etm0_out>; 4026 }; 4027 }; 4028 4029 port@1 { 4030 reg = <1>; 4031 apss_funnel_in1: endpoint { 4032 remote-endpoint = <&etm1_out>; 4033 }; 4034 }; 4035 4036 port@2 { 4037 reg = <2>; 4038 apss_funnel_in2: endpoint { 4039 remote-endpoint = <&etm2_out>; 4040 }; 4041 }; 4042 4043 port@3 { 4044 reg = <3>; 4045 apss_funnel_in3: endpoint { 4046 remote-endpoint = <&etm3_out>; 4047 }; 4048 }; 4049 4050 port@4 { 4051 reg = <4>; 4052 apss_funnel_in4: endpoint { 4053 remote-endpoint = <&etm4_out>; 4054 }; 4055 }; 4056 4057 port@5 { 4058 reg = <5>; 4059 apss_funnel_in5: endpoint { 4060 remote-endpoint = <&etm5_out>; 4061 }; 4062 }; 4063 4064 port@6 { 4065 reg = <6>; 4066 apss_funnel_in6: endpoint { 4067 remote-endpoint = <&etm6_out>; 4068 }; 4069 }; 4070 4071 port@7 { 4072 reg = <7>; 4073 apss_funnel_in7: endpoint { 4074 remote-endpoint = <&etm7_out>; 4075 }; 4076 }; 4077 }; 4078 }; 4079 4080 funnel@7810000 { 4081 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 4082 reg = <0 0x07810000 0 0x1000>; 4083 4084 clocks = <&aoss_qmp>; 4085 clock-names = "apb_pclk"; 4086 4087 out-ports { 4088 port { 4089 apss_merge_funnel_out: endpoint { 4090 remote-endpoint = <&funnel1_in4>; 4091 }; 4092 }; 4093 }; 4094 4095 in-ports { 4096 port { 4097 apss_merge_funnel_in: endpoint { 4098 remote-endpoint = <&apss_funnel_out>; 4099 }; 4100 }; 4101 }; 4102 }; 4103 4104 sdhc_2: mmc@8804000 { 4105 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 4106 pinctrl-names = "default", "sleep"; 4107 pinctrl-0 = <&sdc2_clk>, <&sdc2_cmd>, <&sdc2_data>; 4108 pinctrl-1 = <&sdc2_clk_sleep>, <&sdc2_cmd_sleep>, <&sdc2_data_sleep>; 4109 status = "disabled"; 4110 4111 reg = <0 0x08804000 0 0x1000>; 4112 4113 iommus = <&apps_smmu 0x100 0x0>; 4114 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 4115 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 4116 interrupt-names = "hc_irq", "pwr_irq"; 4117 4118 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 4119 <&gcc GCC_SDCC2_APPS_CLK>, 4120 <&rpmhcc RPMH_CXO_CLK>; 4121 clock-names = "iface", "core", "xo"; 4122 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 4123 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_2 0>; 4124 interconnect-names = "sdhc-ddr","cpu-sdhc"; 4125 power-domains = <&rpmhpd SC7280_CX>; 4126 operating-points-v2 = <&sdhc2_opp_table>; 4127 4128 bus-width = <4>; 4129 dma-coherent; 4130 4131 qcom,dll-config = <0x0007642c>; 4132 4133 resets = <&gcc GCC_SDCC2_BCR>; 4134 4135 sdhc2_opp_table: opp-table { 4136 compatible = "operating-points-v2"; 4137 4138 opp-100000000 { 4139 opp-hz = /bits/ 64 <100000000>; 4140 required-opps = <&rpmhpd_opp_low_svs>; 4141 opp-peak-kBps = <1800000 400000>; 4142 opp-avg-kBps = <100000 0>; 4143 }; 4144 4145 opp-202000000 { 4146 opp-hz = /bits/ 64 <202000000>; 4147 required-opps = <&rpmhpd_opp_nom>; 4148 opp-peak-kBps = <5400000 1600000>; 4149 opp-avg-kBps = <200000 0>; 4150 }; 4151 }; 4152 }; 4153 4154 usb_1_hsphy: phy@88e3000 { 4155 compatible = "qcom,sc7280-usb-hs-phy", 4156 "qcom,usb-snps-hs-7nm-phy"; 4157 reg = <0 0x088e3000 0 0x400>; 4158 status = "disabled"; 4159 #phy-cells = <0>; 4160 4161 clocks = <&rpmhcc RPMH_CXO_CLK>; 4162 clock-names = "ref"; 4163 4164 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 4165 }; 4166 4167 usb_2_hsphy: phy@88e4000 { 4168 compatible = "qcom,sc7280-usb-hs-phy", 4169 "qcom,usb-snps-hs-7nm-phy"; 4170 reg = <0 0x088e4000 0 0x400>; 4171 status = "disabled"; 4172 #phy-cells = <0>; 4173 4174 clocks = <&rpmhcc RPMH_CXO_CLK>; 4175 clock-names = "ref"; 4176 4177 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 4178 }; 4179 4180 refgen: regulator@88e7000 { 4181 compatible = "qcom,sc7280-refgen-regulator", 4182 "qcom,sm8250-refgen-regulator"; 4183 reg = <0x0 0x088e7000 0x0 0x84>; 4184 }; 4185 4186 usb_1_qmpphy: phy@88e8000 { 4187 compatible = "qcom,sc7280-qmp-usb3-dp-phy"; 4188 reg = <0 0x088e8000 0 0x3000>; 4189 status = "disabled"; 4190 4191 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 4192 <&rpmhcc RPMH_CXO_CLK>, 4193 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 4194 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 4195 clock-names = "aux", 4196 "ref", 4197 "com_aux", 4198 "usb3_pipe"; 4199 4200 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 4201 <&gcc GCC_USB3_PHY_PRIM_BCR>; 4202 reset-names = "phy", "common"; 4203 4204 #clock-cells = <1>; 4205 #phy-cells = <1>; 4206 4207 orientation-switch; 4208 4209 ports { 4210 #address-cells = <1>; 4211 #size-cells = <0>; 4212 4213 port@0 { 4214 reg = <0>; 4215 4216 usb_dp_qmpphy_out: endpoint { 4217 }; 4218 }; 4219 4220 port@1 { 4221 reg = <1>; 4222 4223 usb_dp_qmpphy_usb_ss_in: endpoint { 4224 remote-endpoint = <&usb_1_dwc3_ss>; 4225 }; 4226 }; 4227 4228 port@2 { 4229 reg = <2>; 4230 4231 usb_dp_qmpphy_dp_in: endpoint { 4232 remote-endpoint = <&mdss_dp_out>; 4233 }; 4234 }; 4235 }; 4236 }; 4237 4238 usb_2: usb@8c00000 { 4239 compatible = "qcom,sc7280-dwc3", "qcom,snps-dwc3"; 4240 reg = <0 0x08c00000 0 0xfc100>; 4241 status = "disabled"; 4242 4243 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 4244 <&gcc GCC_USB30_SEC_MASTER_CLK>, 4245 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 4246 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 4247 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>; 4248 clock-names = "cfg_noc", 4249 "core", 4250 "iface", 4251 "sleep", 4252 "mock_utmi"; 4253 4254 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 4255 <&gcc GCC_USB30_SEC_MASTER_CLK>; 4256 assigned-clock-rates = <19200000>, <200000000>; 4257 4258 interrupts-extended = <&intc GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, 4259 <&intc GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>, 4260 <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4261 <&pdc 12 IRQ_TYPE_EDGE_BOTH>, 4262 <&pdc 13 IRQ_TYPE_EDGE_BOTH>; 4263 interrupt-names = "dwc_usb3", 4264 "pwr_event", 4265 "hs_phy_irq", 4266 "dp_hs_phy_irq", 4267 "dm_hs_phy_irq"; 4268 4269 power-domains = <&gcc GCC_USB30_SEC_GDSC>; 4270 required-opps = <&rpmhpd_opp_nom>; 4271 4272 resets = <&gcc GCC_USB30_SEC_BCR>; 4273 4274 interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>, 4275 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB2 0>; 4276 interconnect-names = "usb-ddr", "apps-usb"; 4277 4278 iommus = <&apps_smmu 0xa0 0x0>; 4279 snps,dis_u2_susphy_quirk; 4280 snps,dis_enblslpm_quirk; 4281 snps,dis-u1-entry-quirk; 4282 snps,dis-u2-entry-quirk; 4283 phys = <&usb_2_hsphy>; 4284 phy-names = "usb2-phy"; 4285 maximum-speed = "high-speed"; 4286 usb-role-switch; 4287 4288 port { 4289 usb2_role_switch: endpoint { 4290 remote-endpoint = <&eud_ep>; 4291 }; 4292 }; 4293 }; 4294 4295 qspi: spi@88dc000 { 4296 compatible = "qcom,sc7280-qspi", "qcom,qspi-v1"; 4297 reg = <0 0x088dc000 0 0x1000>; 4298 iommus = <&apps_smmu 0x20 0x0>; 4299 #address-cells = <1>; 4300 #size-cells = <0>; 4301 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 4302 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 4303 <&gcc GCC_QSPI_CORE_CLK>; 4304 clock-names = "iface", "core"; 4305 interconnects = <&gem_noc MASTER_APPSS_PROC 0 4306 &cnoc2 SLAVE_QSPI_0 0>; 4307 interconnect-names = "qspi-config"; 4308 power-domains = <&rpmhpd SC7280_CX>; 4309 operating-points-v2 = <&qspi_opp_table>; 4310 status = "disabled"; 4311 }; 4312 4313 remoteproc_adsp: remoteproc@3700000 { 4314 compatible = "qcom,sc7280-adsp-pas"; 4315 reg = <0 0x03700000 0 0x100>; 4316 4317 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 4318 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 4319 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 4320 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 4321 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 4322 <&adsp_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 4323 interrupt-names = "wdog", "fatal", "ready", "handover", 4324 "stop-ack", "shutdown-ack"; 4325 4326 clocks = <&rpmhcc RPMH_CXO_CLK>; 4327 clock-names = "xo"; 4328 4329 power-domains = <&rpmhpd SC7280_LCX>, 4330 <&rpmhpd SC7280_LMX>; 4331 power-domain-names = "lcx", "lmx"; 4332 4333 memory-region = <&adsp_mem>; 4334 4335 qcom,qmp = <&aoss_qmp>; 4336 4337 qcom,smem-states = <&adsp_smp2p_out 0>; 4338 qcom,smem-state-names = "stop"; 4339 4340 status = "disabled"; 4341 4342 remoteproc_adsp_glink: glink-edge { 4343 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 4344 IPCC_MPROC_SIGNAL_GLINK_QMP 4345 IRQ_TYPE_EDGE_RISING>; 4346 4347 mboxes = <&ipcc IPCC_CLIENT_LPASS 4348 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4349 4350 label = "lpass"; 4351 qcom,remote-pid = <2>; 4352 4353 apr { 4354 compatible = "qcom,apr-v2"; 4355 qcom,glink-channels = "apr_audio_svc"; 4356 qcom,domain = <APR_DOMAIN_ADSP>; 4357 #address-cells = <1>; 4358 #size-cells = <0>; 4359 4360 service@3 { 4361 reg = <APR_SVC_ADSP_CORE>; 4362 compatible = "qcom,q6core"; 4363 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 4364 }; 4365 4366 q6afe: service@4 { 4367 compatible = "qcom,q6afe"; 4368 reg = <APR_SVC_AFE>; 4369 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 4370 4371 q6afedai: dais { 4372 compatible = "qcom,q6afe-dais"; 4373 #address-cells = <1>; 4374 #size-cells = <0>; 4375 #sound-dai-cells = <1>; 4376 }; 4377 4378 q6afecc: clock-controller { 4379 compatible = "qcom,q6afe-clocks"; 4380 #clock-cells = <2>; 4381 }; 4382 4383 q6usbdai: usbd { 4384 compatible = "qcom,q6usb"; 4385 iommus = <&apps_smmu 0x180f 0x0>; 4386 #sound-dai-cells = <1>; 4387 qcom,usb-audio-intr-idx = /bits/ 16 <2>; 4388 }; 4389 }; 4390 4391 q6asm: service@7 { 4392 compatible = "qcom,q6asm"; 4393 reg = <APR_SVC_ASM>; 4394 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 4395 4396 q6asmdai: dais { 4397 compatible = "qcom,q6asm-dais"; 4398 #address-cells = <1>; 4399 #size-cells = <0>; 4400 #sound-dai-cells = <1>; 4401 iommus = <&apps_smmu 0x1801 0x0>; 4402 4403 dai@0 { 4404 reg = <MSM_FRONTEND_DAI_MULTIMEDIA1>; 4405 }; 4406 4407 dai@1 { 4408 reg = <MSM_FRONTEND_DAI_MULTIMEDIA2>; 4409 }; 4410 4411 dai@2 { 4412 reg = <MSM_FRONTEND_DAI_MULTIMEDIA3>; 4413 }; 4414 }; 4415 }; 4416 4417 q6adm: service@8 { 4418 compatible = "qcom,q6adm"; 4419 reg = <APR_SVC_ADM>; 4420 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 4421 4422 q6routing: routing { 4423 compatible = "qcom,q6adm-routing"; 4424 #sound-dai-cells = <0>; 4425 }; 4426 }; 4427 }; 4428 4429 fastrpc { 4430 compatible = "qcom,fastrpc"; 4431 qcom,glink-channels = "fastrpcglink-apps-dsp"; 4432 label = "adsp"; 4433 qcom,non-secure-domain; 4434 #address-cells = <1>; 4435 #size-cells = <0>; 4436 4437 compute-cb@3 { 4438 compatible = "qcom,fastrpc-compute-cb"; 4439 reg = <3>; 4440 iommus = <&apps_smmu 0x1803 0x0>; 4441 dma-coherent; 4442 }; 4443 4444 compute-cb@4 { 4445 compatible = "qcom,fastrpc-compute-cb"; 4446 reg = <4>; 4447 iommus = <&apps_smmu 0x1804 0x0>; 4448 dma-coherent; 4449 }; 4450 4451 compute-cb@5 { 4452 compatible = "qcom,fastrpc-compute-cb"; 4453 reg = <5>; 4454 iommus = <&apps_smmu 0x1805 0x0>; 4455 dma-coherent; 4456 }; 4457 }; 4458 }; 4459 }; 4460 4461 remoteproc_wpss: remoteproc@8a00000 { 4462 compatible = "qcom,sc7280-wpss-pas"; 4463 reg = <0 0x08a00000 0 0x10000>; 4464 4465 interrupts-extended = <&intc GIC_SPI 587 IRQ_TYPE_EDGE_RISING>, 4466 <&wpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 4467 <&wpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 4468 <&wpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 4469 <&wpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 4470 <&wpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 4471 interrupt-names = "wdog", "fatal", "ready", "handover", 4472 "stop-ack", "shutdown-ack"; 4473 4474 clocks = <&rpmhcc RPMH_CXO_CLK>; 4475 clock-names = "xo"; 4476 4477 power-domains = <&rpmhpd SC7280_CX>, 4478 <&rpmhpd SC7280_MX>; 4479 power-domain-names = "cx", "mx"; 4480 4481 memory-region = <&wpss_mem>; 4482 4483 qcom,qmp = <&aoss_qmp>; 4484 4485 qcom,smem-states = <&wpss_smp2p_out 0>; 4486 qcom,smem-state-names = "stop"; 4487 4488 4489 status = "disabled"; 4490 4491 glink-edge { 4492 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 4493 IPCC_MPROC_SIGNAL_GLINK_QMP 4494 IRQ_TYPE_EDGE_RISING>; 4495 mboxes = <&ipcc IPCC_CLIENT_WPSS 4496 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4497 4498 label = "wpss"; 4499 qcom,remote-pid = <13>; 4500 }; 4501 }; 4502 4503 pmu@9091000 { 4504 compatible = "qcom,sc7280-llcc-bwmon"; 4505 reg = <0 0x09091000 0 0x1000>; 4506 4507 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 4508 4509 interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>; 4510 4511 operating-points-v2 = <&llcc_bwmon_opp_table>; 4512 4513 llcc_bwmon_opp_table: opp-table { 4514 compatible = "operating-points-v2"; 4515 4516 opp-0 { 4517 opp-peak-kBps = <800000>; 4518 }; 4519 opp-1 { 4520 opp-peak-kBps = <1804000>; 4521 }; 4522 opp-2 { 4523 opp-peak-kBps = <2188000>; 4524 }; 4525 opp-3 { 4526 opp-peak-kBps = <3072000>; 4527 }; 4528 opp-4 { 4529 opp-peak-kBps = <4068000>; 4530 }; 4531 opp-5 { 4532 opp-peak-kBps = <6220000>; 4533 }; 4534 opp-6 { 4535 opp-peak-kBps = <6832000>; 4536 }; 4537 opp-7 { 4538 opp-peak-kBps = <8532000>; 4539 }; 4540 opp-8 { 4541 opp-peak-kBps = <10944000>; 4542 }; 4543 opp-9 { 4544 opp-peak-kBps = <12787200>; 4545 }; 4546 }; 4547 }; 4548 4549 pmu@90b6400 { 4550 compatible = "qcom,sc7280-cpu-bwmon", "qcom,sdm845-bwmon"; 4551 reg = <0 0x090b6400 0 0x600>; 4552 4553 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 4554 4555 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>; 4556 operating-points-v2 = <&cpu_bwmon_opp_table>; 4557 4558 cpu_bwmon_opp_table: opp-table { 4559 compatible = "operating-points-v2"; 4560 4561 opp-0 { 4562 opp-peak-kBps = <2400000>; 4563 }; 4564 opp-1 { 4565 opp-peak-kBps = <4800000>; 4566 }; 4567 opp-2 { 4568 opp-peak-kBps = <7456000>; 4569 }; 4570 opp-3 { 4571 opp-peak-kBps = <9600000>; 4572 }; 4573 opp-4 { 4574 opp-peak-kBps = <12896000>; 4575 }; 4576 opp-5 { 4577 opp-peak-kBps = <14928000>; 4578 }; 4579 opp-6 { 4580 opp-peak-kBps = <17056000>; 4581 }; 4582 }; 4583 }; 4584 4585 dc_noc: interconnect@90e0000 { 4586 reg = <0 0x090e0000 0 0x5080>; 4587 compatible = "qcom,sc7280-dc-noc"; 4588 #interconnect-cells = <2>; 4589 qcom,bcm-voters = <&apps_bcm_voter>; 4590 }; 4591 4592 gem_noc: interconnect@9100000 { 4593 reg = <0 0x09100000 0 0xe2200>; 4594 compatible = "qcom,sc7280-gem-noc"; 4595 #interconnect-cells = <2>; 4596 qcom,bcm-voters = <&apps_bcm_voter>; 4597 }; 4598 4599 system-cache-controller@9200000 { 4600 compatible = "qcom,sc7280-llcc"; 4601 reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>, 4602 <0 0x09600000 0 0x58000>; 4603 reg-names = "llcc0_base", "llcc1_base", "llcc_broadcast_base"; 4604 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 4605 }; 4606 4607 eud: eud@88e0000 { 4608 compatible = "qcom,sc7280-eud", "qcom,eud"; 4609 reg = <0 0x88e0000 0 0x2000>, 4610 <0 0x88e2000 0 0x1000>; 4611 interrupts-extended = <&pdc 11 IRQ_TYPE_LEVEL_HIGH>; 4612 4613 status = "disabled"; 4614 4615 ports { 4616 #address-cells = <1>; 4617 #size-cells = <0>; 4618 4619 port@0 { 4620 reg = <0>; 4621 eud_ep: endpoint { 4622 remote-endpoint = <&usb2_role_switch>; 4623 }; 4624 }; 4625 }; 4626 }; 4627 4628 nsp_noc: interconnect@a0c0000 { 4629 reg = <0 0x0a0c0000 0 0x10000>; 4630 compatible = "qcom,sc7280-nsp-noc"; 4631 #interconnect-cells = <2>; 4632 qcom,bcm-voters = <&apps_bcm_voter>; 4633 }; 4634 4635 remoteproc_cdsp: remoteproc@a300000 { 4636 compatible = "qcom,sc7280-cdsp-pas"; 4637 reg = <0 0x0a300000 0 0x10000>; 4638 4639 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 4640 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 4641 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 4642 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 4643 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 4644 <&cdsp_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 4645 interrupt-names = "wdog", "fatal", "ready", "handover", 4646 "stop-ack", "shutdown-ack"; 4647 4648 clocks = <&rpmhcc RPMH_CXO_CLK>; 4649 clock-names = "xo"; 4650 4651 power-domains = <&rpmhpd SC7280_CX>, 4652 <&rpmhpd SC7280_MX>; 4653 power-domain-names = "cx", "mx"; 4654 4655 interconnects = <&nsp_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>; 4656 4657 memory-region = <&cdsp_mem>; 4658 4659 qcom,qmp = <&aoss_qmp>; 4660 4661 qcom,smem-states = <&cdsp_smp2p_out 0>; 4662 qcom,smem-state-names = "stop"; 4663 4664 status = "disabled"; 4665 4666 glink-edge { 4667 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 4668 IPCC_MPROC_SIGNAL_GLINK_QMP 4669 IRQ_TYPE_EDGE_RISING>; 4670 mboxes = <&ipcc IPCC_CLIENT_CDSP 4671 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4672 4673 label = "cdsp"; 4674 qcom,remote-pid = <5>; 4675 4676 fastrpc { 4677 compatible = "qcom,fastrpc"; 4678 qcom,glink-channels = "fastrpcglink-apps-dsp"; 4679 label = "cdsp"; 4680 qcom,non-secure-domain; 4681 #address-cells = <1>; 4682 #size-cells = <0>; 4683 4684 compute-cb@1 { 4685 compatible = "qcom,fastrpc-compute-cb"; 4686 reg = <1>; 4687 iommus = <&apps_smmu 0x11a1 0x0420>, 4688 <&apps_smmu 0x1181 0x0420>; 4689 dma-coherent; 4690 }; 4691 4692 compute-cb@2 { 4693 compatible = "qcom,fastrpc-compute-cb"; 4694 reg = <2>; 4695 iommus = <&apps_smmu 0x11a2 0x0420>, 4696 <&apps_smmu 0x1182 0x0420>; 4697 dma-coherent; 4698 }; 4699 4700 compute-cb@3 { 4701 compatible = "qcom,fastrpc-compute-cb"; 4702 reg = <3>; 4703 iommus = <&apps_smmu 0x11a3 0x0420>, 4704 <&apps_smmu 0x1183 0x0420>; 4705 dma-coherent; 4706 }; 4707 4708 compute-cb@4 { 4709 compatible = "qcom,fastrpc-compute-cb"; 4710 reg = <4>; 4711 iommus = <&apps_smmu 0x11a4 0x0420>, 4712 <&apps_smmu 0x1184 0x0420>; 4713 dma-coherent; 4714 }; 4715 4716 compute-cb@5 { 4717 compatible = "qcom,fastrpc-compute-cb"; 4718 reg = <5>; 4719 iommus = <&apps_smmu 0x11a5 0x0420>, 4720 <&apps_smmu 0x1185 0x0420>; 4721 dma-coherent; 4722 }; 4723 4724 compute-cb@6 { 4725 compatible = "qcom,fastrpc-compute-cb"; 4726 reg = <6>; 4727 iommus = <&apps_smmu 0x11a6 0x0420>, 4728 <&apps_smmu 0x1186 0x0420>; 4729 dma-coherent; 4730 }; 4731 4732 compute-cb@7 { 4733 compatible = "qcom,fastrpc-compute-cb"; 4734 reg = <7>; 4735 iommus = <&apps_smmu 0x11a7 0x0420>, 4736 <&apps_smmu 0x1187 0x0420>; 4737 dma-coherent; 4738 }; 4739 4740 compute-cb@8 { 4741 compatible = "qcom,fastrpc-compute-cb"; 4742 reg = <8>; 4743 iommus = <&apps_smmu 0x11a8 0x0420>, 4744 <&apps_smmu 0x1188 0x0420>; 4745 dma-coherent; 4746 }; 4747 4748 /* note: secure cb9 in downstream */ 4749 4750 compute-cb@11 { 4751 compatible = "qcom,fastrpc-compute-cb"; 4752 reg = <11>; 4753 iommus = <&apps_smmu 0x11ab 0x0420>, 4754 <&apps_smmu 0x118b 0x0420>; 4755 dma-coherent; 4756 }; 4757 4758 compute-cb@12 { 4759 compatible = "qcom,fastrpc-compute-cb"; 4760 reg = <12>; 4761 iommus = <&apps_smmu 0x11ac 0x0420>, 4762 <&apps_smmu 0x118c 0x0420>; 4763 dma-coherent; 4764 }; 4765 4766 compute-cb@13 { 4767 compatible = "qcom,fastrpc-compute-cb"; 4768 reg = <13>; 4769 iommus = <&apps_smmu 0x11ad 0x0420>, 4770 <&apps_smmu 0x118d 0x0420>; 4771 dma-coherent; 4772 }; 4773 4774 compute-cb@14 { 4775 compatible = "qcom,fastrpc-compute-cb"; 4776 reg = <14>; 4777 iommus = <&apps_smmu 0x11ae 0x0420>, 4778 <&apps_smmu 0x118e 0x0420>; 4779 dma-coherent; 4780 }; 4781 }; 4782 }; 4783 }; 4784 4785 usb_1: usb@a600000 { 4786 compatible = "qcom,sc7280-dwc3", "qcom,snps-dwc3"; 4787 reg = <0 0x0a600000 0 0xfc100>; 4788 status = "disabled"; 4789 4790 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 4791 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 4792 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 4793 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 4794 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 4795 clock-names = "cfg_noc", 4796 "core", 4797 "iface", 4798 "sleep", 4799 "mock_utmi"; 4800 4801 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4802 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 4803 assigned-clock-rates = <19200000>, <200000000>; 4804 4805 interrupts-extended = <&intc GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 4806 <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 4807 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 4808 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 4809 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 4810 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 4811 interrupt-names = "dwc_usb3", 4812 "pwr_event", 4813 "hs_phy_irq", 4814 "dp_hs_phy_irq", 4815 "dm_hs_phy_irq", 4816 "ss_phy_irq"; 4817 4818 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 4819 required-opps = <&rpmhpd_opp_nom>; 4820 4821 resets = <&gcc GCC_USB30_PRIM_BCR>; 4822 4823 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 4824 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB3_0 0>; 4825 interconnect-names = "usb-ddr", "apps-usb"; 4826 4827 wakeup-source; 4828 4829 iommus = <&apps_smmu 0xe0 0x0>; 4830 snps,dis_u2_susphy_quirk; 4831 snps,dis_enblslpm_quirk; 4832 snps,parkmode-disable-ss-quirk; 4833 snps,dis-u1-entry-quirk; 4834 snps,dis-u2-entry-quirk; 4835 num-hc-interrupters = /bits/ 16 <3>; 4836 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; 4837 phy-names = "usb2-phy", "usb3-phy"; 4838 maximum-speed = "super-speed"; 4839 4840 ports { 4841 #address-cells = <1>; 4842 #size-cells = <0>; 4843 4844 port@0 { 4845 reg = <0>; 4846 4847 usb_1_dwc3_hs: endpoint { 4848 }; 4849 }; 4850 4851 port@1 { 4852 reg = <1>; 4853 4854 usb_1_dwc3_ss: endpoint { 4855 remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>; 4856 }; 4857 }; 4858 }; 4859 }; 4860 4861 venus: video-codec@aa00000 { 4862 compatible = "qcom,sc7280-venus"; 4863 reg = <0 0x0aa00000 0 0xd0600>; 4864 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 4865 4866 clocks = <&videocc VIDEO_CC_MVSC_CORE_CLK>, 4867 <&videocc VIDEO_CC_MVSC_CTL_AXI_CLK>, 4868 <&videocc VIDEO_CC_VENUS_AHB_CLK>, 4869 <&videocc VIDEO_CC_MVS0_CORE_CLK>, 4870 <&videocc VIDEO_CC_MVS0_AXI_CLK>; 4871 clock-names = "core", "bus", "iface", 4872 "vcodec_core", "vcodec_bus"; 4873 4874 power-domains = <&videocc MVSC_GDSC>, 4875 <&videocc MVS0_GDSC>, 4876 <&rpmhpd SC7280_CX>; 4877 power-domain-names = "venus", "vcodec0", "cx"; 4878 operating-points-v2 = <&venus_opp_table>; 4879 4880 interconnects = <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_VENUS_CFG 0>, 4881 <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>; 4882 interconnect-names = "cpu-cfg", "video-mem"; 4883 4884 iommus = <&apps_smmu 0x2180 0x20>; 4885 memory-region = <&video_mem>; 4886 4887 status = "disabled"; 4888 4889 venus_opp_table: opp-table { 4890 compatible = "operating-points-v2"; 4891 4892 opp-133330000 { 4893 opp-hz = /bits/ 64 <133330000>; 4894 required-opps = <&rpmhpd_opp_low_svs>; 4895 }; 4896 4897 opp-240000000 { 4898 opp-hz = /bits/ 64 <240000000>; 4899 required-opps = <&rpmhpd_opp_svs>; 4900 }; 4901 4902 opp-335000000 { 4903 opp-hz = /bits/ 64 <335000000>; 4904 required-opps = <&rpmhpd_opp_svs_l1>; 4905 }; 4906 4907 opp-424000000 { 4908 opp-hz = /bits/ 64 <424000000>; 4909 required-opps = <&rpmhpd_opp_nom>; 4910 }; 4911 4912 opp-460000048 { 4913 opp-hz = /bits/ 64 <460000048>; 4914 required-opps = <&rpmhpd_opp_turbo>; 4915 }; 4916 }; 4917 }; 4918 4919 videocc: clock-controller@aaf0000 { 4920 compatible = "qcom,sc7280-videocc"; 4921 reg = <0 0x0aaf0000 0 0x10000>; 4922 clocks = <&rpmhcc RPMH_CXO_CLK>, 4923 <&rpmhcc RPMH_CXO_CLK_A>; 4924 clock-names = "bi_tcxo", "bi_tcxo_ao"; 4925 #clock-cells = <1>; 4926 #reset-cells = <1>; 4927 #power-domain-cells = <1>; 4928 }; 4929 4930 cci0: cci@ac4a000 { 4931 compatible = "qcom,sc7280-cci", "qcom,msm8996-cci"; 4932 reg = <0 0x0ac4a000 0 0x1000>; 4933 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>; 4934 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; 4935 4936 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 4937 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, 4938 <&camcc CAM_CC_CPAS_AHB_CLK>, 4939 <&camcc CAM_CC_CCI_0_CLK>, 4940 <&camcc CAM_CC_CCI_0_CLK_SRC>; 4941 clock-names = "camnoc_axi", 4942 "slow_ahb_src", 4943 "cpas_ahb", 4944 "cci", 4945 "cci_src"; 4946 pinctrl-0 = <&cci0_default &cci1_default>; 4947 pinctrl-1 = <&cci0_sleep &cci1_sleep>; 4948 pinctrl-names = "default", "sleep"; 4949 4950 #address-cells = <1>; 4951 #size-cells = <0>; 4952 4953 status = "disabled"; 4954 4955 cci0_i2c0: i2c-bus@0 { 4956 reg = <0>; 4957 clock-frequency = <1000000>; 4958 #address-cells = <1>; 4959 #size-cells = <0>; 4960 }; 4961 4962 cci0_i2c1: i2c-bus@1 { 4963 reg = <1>; 4964 clock-frequency = <1000000>; 4965 #address-cells = <1>; 4966 #size-cells = <0>; 4967 }; 4968 }; 4969 4970 cci1: cci@ac4b000 { 4971 compatible = "qcom,sc7280-cci", "qcom,msm8996-cci"; 4972 reg = <0 0x0ac4b000 0 0x1000>; 4973 interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>; 4974 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; 4975 4976 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 4977 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, 4978 <&camcc CAM_CC_CPAS_AHB_CLK>, 4979 <&camcc CAM_CC_CCI_1_CLK>, 4980 <&camcc CAM_CC_CCI_1_CLK_SRC>; 4981 clock-names = "camnoc_axi", 4982 "slow_ahb_src", 4983 "cpas_ahb", 4984 "cci", 4985 "cci_src"; 4986 pinctrl-0 = <&cci2_default &cci3_default>; 4987 pinctrl-1 = <&cci2_sleep &cci3_sleep>; 4988 pinctrl-names = "default", "sleep"; 4989 4990 #address-cells = <1>; 4991 #size-cells = <0>; 4992 4993 status = "disabled"; 4994 4995 cci1_i2c0: i2c-bus@0 { 4996 reg = <0>; 4997 clock-frequency = <1000000>; 4998 #address-cells = <1>; 4999 #size-cells = <0>; 5000 }; 5001 5002 cci1_i2c1: i2c-bus@1 { 5003 reg = <1>; 5004 clock-frequency = <1000000>; 5005 #address-cells = <1>; 5006 #size-cells = <0>; 5007 }; 5008 }; 5009 5010 camss: isp@acb3000 { 5011 compatible = "qcom,sc7280-camss"; 5012 5013 reg = <0x0 0x0acb3000 0x0 0x1000>, 5014 <0x0 0x0acba000 0x0 0x1000>, 5015 <0x0 0x0acc1000 0x0 0x1000>, 5016 <0x0 0x0acc8000 0x0 0x1000>, 5017 <0x0 0x0accf000 0x0 0x1000>, 5018 <0x0 0x0ace0000 0x0 0x2000>, 5019 <0x0 0x0ace2000 0x0 0x2000>, 5020 <0x0 0x0ace4000 0x0 0x2000>, 5021 <0x0 0x0ace6000 0x0 0x2000>, 5022 <0x0 0x0ace8000 0x0 0x2000>, 5023 <0x0 0x0acaf000 0x0 0x4000>, 5024 <0x0 0x0acb6000 0x0 0x4000>, 5025 <0x0 0x0acbd000 0x0 0x4000>, 5026 <0x0 0x0acc4000 0x0 0x4000>, 5027 <0x0 0x0accb000 0x0 0x4000>; 5028 reg-names = "csid0", 5029 "csid1", 5030 "csid2", 5031 "csid_lite0", 5032 "csid_lite1", 5033 "csiphy0", 5034 "csiphy1", 5035 "csiphy2", 5036 "csiphy3", 5037 "csiphy4", 5038 "vfe0", 5039 "vfe1", 5040 "vfe2", 5041 "vfe_lite0", 5042 "vfe_lite1"; 5043 5044 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 5045 <&camcc CAM_CC_CPAS_AHB_CLK>, 5046 <&camcc CAM_CC_CSIPHY0_CLK>, 5047 <&camcc CAM_CC_CSI0PHYTIMER_CLK>, 5048 <&camcc CAM_CC_CSIPHY1_CLK>, 5049 <&camcc CAM_CC_CSI1PHYTIMER_CLK>, 5050 <&camcc CAM_CC_CSIPHY2_CLK>, 5051 <&camcc CAM_CC_CSI2PHYTIMER_CLK>, 5052 <&camcc CAM_CC_CSIPHY3_CLK>, 5053 <&camcc CAM_CC_CSI3PHYTIMER_CLK>, 5054 <&camcc CAM_CC_CSIPHY4_CLK>, 5055 <&camcc CAM_CC_CSI4PHYTIMER_CLK>, 5056 <&gcc GCC_CAMERA_HF_AXI_CLK>, 5057 <&gcc GCC_CAMERA_SF_AXI_CLK>, 5058 <&camcc CAM_CC_ICP_AHB_CLK>, 5059 <&camcc CAM_CC_IFE_0_CLK>, 5060 <&camcc CAM_CC_IFE_0_AXI_CLK>, 5061 <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>, 5062 <&camcc CAM_CC_IFE_0_CSID_CLK>, 5063 <&camcc CAM_CC_IFE_1_CLK>, 5064 <&camcc CAM_CC_IFE_1_AXI_CLK>, 5065 <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>, 5066 <&camcc CAM_CC_IFE_1_CSID_CLK>, 5067 <&camcc CAM_CC_IFE_2_CLK>, 5068 <&camcc CAM_CC_IFE_2_AXI_CLK>, 5069 <&camcc CAM_CC_IFE_2_CPHY_RX_CLK>, 5070 <&camcc CAM_CC_IFE_2_CSID_CLK>, 5071 <&camcc CAM_CC_IFE_LITE_0_CLK>, 5072 <&camcc CAM_CC_IFE_LITE_0_CPHY_RX_CLK>, 5073 <&camcc CAM_CC_IFE_LITE_0_CSID_CLK>, 5074 <&camcc CAM_CC_IFE_LITE_1_CLK>, 5075 <&camcc CAM_CC_IFE_LITE_1_CPHY_RX_CLK>, 5076 <&camcc CAM_CC_IFE_LITE_1_CSID_CLK>; 5077 clock-names = "camnoc_axi", 5078 "cpas_ahb", 5079 "csiphy0", 5080 "csiphy0_timer", 5081 "csiphy1", 5082 "csiphy1_timer", 5083 "csiphy2", 5084 "csiphy2_timer", 5085 "csiphy3", 5086 "csiphy3_timer", 5087 "csiphy4", 5088 "csiphy4_timer", 5089 "gcc_axi_hf", 5090 "gcc_axi_sf", 5091 "icp_ahb", 5092 "vfe0", 5093 "vfe0_axi", 5094 "vfe0_cphy_rx", 5095 "vfe0_csid", 5096 "vfe1", 5097 "vfe1_axi", 5098 "vfe1_cphy_rx", 5099 "vfe1_csid", 5100 "vfe2", 5101 "vfe2_axi", 5102 "vfe2_cphy_rx", 5103 "vfe2_csid", 5104 "vfe_lite0", 5105 "vfe_lite0_cphy_rx", 5106 "vfe_lite0_csid", 5107 "vfe_lite1", 5108 "vfe_lite1_cphy_rx", 5109 "vfe_lite1_csid"; 5110 5111 interrupts = <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>, 5112 <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>, 5113 <GIC_SPI 640 IRQ_TYPE_EDGE_RISING>, 5114 <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>, 5115 <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>, 5116 <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>, 5117 <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>, 5118 <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>, 5119 <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>, 5120 <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>, 5121 <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>, 5122 <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>, 5123 <GIC_SPI 641 IRQ_TYPE_EDGE_RISING>, 5124 <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>, 5125 <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>; 5126 interrupt-names = "csid0", 5127 "csid1", 5128 "csid2", 5129 "csid_lite0", 5130 "csid_lite1", 5131 "csiphy0", 5132 "csiphy1", 5133 "csiphy2", 5134 "csiphy3", 5135 "csiphy4", 5136 "vfe0", 5137 "vfe1", 5138 "vfe2", 5139 "vfe_lite0", 5140 "vfe_lite1"; 5141 5142 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5143 &cnoc2 SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, 5144 <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS 5145 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 5146 interconnect-names = "ahb", 5147 "hf_0"; 5148 5149 iommus = <&apps_smmu 0x800 0x4e0>; 5150 5151 power-domains = <&camcc CAM_CC_IFE_0_GDSC>, 5152 <&camcc CAM_CC_IFE_1_GDSC>, 5153 <&camcc CAM_CC_IFE_2_GDSC>, 5154 <&camcc CAM_CC_TITAN_TOP_GDSC>; 5155 power-domain-names = "ife0", 5156 "ife1", 5157 "ife2", 5158 "top"; 5159 5160 status = "disabled"; 5161 5162 ports { 5163 #address-cells = <1>; 5164 #size-cells = <0>; 5165 5166 port@0 { 5167 reg = <0>; 5168 }; 5169 5170 port@1 { 5171 reg = <1>; 5172 }; 5173 5174 port@2 { 5175 reg = <2>; 5176 }; 5177 5178 port@3 { 5179 reg = <3>; 5180 }; 5181 5182 port@4 { 5183 reg = <4>; 5184 }; 5185 }; 5186 }; 5187 5188 camcc: clock-controller@ad00000 { 5189 compatible = "qcom,sc7280-camcc"; 5190 reg = <0 0x0ad00000 0 0x10000>; 5191 clocks = <&rpmhcc RPMH_CXO_CLK>, 5192 <&rpmhcc RPMH_CXO_CLK_A>, 5193 <&sleep_clk>; 5194 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; 5195 #clock-cells = <1>; 5196 #reset-cells = <1>; 5197 #power-domain-cells = <1>; 5198 }; 5199 5200 dispcc: clock-controller@af00000 { 5201 compatible = "qcom,sc7280-dispcc"; 5202 reg = <0 0x0af00000 0 0x20000>; 5203 clocks = <&rpmhcc RPMH_CXO_CLK>, 5204 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 5205 <&mdss_dsi_phy DSI_BYTE_PLL_CLK>, 5206 <&mdss_dsi_phy DSI_PIXEL_PLL_CLK>, 5207 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 5208 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 5209 <&mdss_edp_phy 0>, 5210 <&mdss_edp_phy 1>; 5211 clock-names = "bi_tcxo", 5212 "gcc_disp_gpll0_clk", 5213 "dsi0_phy_pll_out_byteclk", 5214 "dsi0_phy_pll_out_dsiclk", 5215 "dp_phy_pll_link_clk", 5216 "dp_phy_pll_vco_div_clk", 5217 "edp_phy_pll_link_clk", 5218 "edp_phy_pll_vco_div_clk"; 5219 #clock-cells = <1>; 5220 #reset-cells = <1>; 5221 #power-domain-cells = <1>; 5222 }; 5223 5224 mdss: display-subsystem@ae00000 { 5225 compatible = "qcom,sc7280-mdss"; 5226 reg = <0 0x0ae00000 0 0x1000>; 5227 reg-names = "mdss"; 5228 5229 power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; 5230 5231 clocks = <&gcc GCC_DISP_AHB_CLK>, 5232 <&dispcc DISP_CC_MDSS_AHB_CLK>, 5233 <&dispcc DISP_CC_MDSS_MDP_CLK>; 5234 clock-names = "iface", 5235 "ahb", 5236 "core"; 5237 5238 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 5239 interrupt-controller; 5240 #interrupt-cells = <1>; 5241 5242 interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ALWAYS 5243 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 5244 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 5245 &cnoc2 SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ALWAYS>; 5246 interconnect-names = "mdp0-mem", 5247 "cpu-cfg"; 5248 5249 iommus = <&apps_smmu 0x900 0x402>; 5250 5251 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 5252 5253 #address-cells = <2>; 5254 #size-cells = <2>; 5255 ranges; 5256 5257 status = "disabled"; 5258 5259 mdss_mdp: display-controller@ae01000 { 5260 compatible = "qcom,sc7280-dpu"; 5261 reg = <0 0x0ae01000 0 0x8f030>, 5262 <0 0x0aeb0000 0 0x3000>; 5263 reg-names = "mdp", "vbif"; 5264 5265 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 5266 <&gcc GCC_DISP_SF_AXI_CLK>, 5267 <&dispcc DISP_CC_MDSS_AHB_CLK>, 5268 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 5269 <&dispcc DISP_CC_MDSS_MDP_CLK>, 5270 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 5271 clock-names = "bus", 5272 "nrt_bus", 5273 "iface", 5274 "lut", 5275 "core", 5276 "vsync"; 5277 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>, 5278 <&dispcc DISP_CC_MDSS_AHB_CLK>; 5279 assigned-clock-rates = <19200000>, 5280 <19200000>; 5281 operating-points-v2 = <&mdp_opp_table>; 5282 power-domains = <&rpmhpd SC7280_CX>; 5283 5284 interrupt-parent = <&mdss>; 5285 interrupts = <0>; 5286 5287 ports { 5288 #address-cells = <1>; 5289 #size-cells = <0>; 5290 5291 port@0 { 5292 reg = <0>; 5293 dpu_intf1_out: endpoint { 5294 remote-endpoint = <&mdss_dsi0_in>; 5295 }; 5296 }; 5297 5298 port@1 { 5299 reg = <1>; 5300 dpu_intf5_out: endpoint { 5301 remote-endpoint = <&edp_in>; 5302 }; 5303 }; 5304 5305 port@2 { 5306 reg = <2>; 5307 dpu_intf0_out: endpoint { 5308 remote-endpoint = <&dp_in>; 5309 }; 5310 }; 5311 }; 5312 5313 mdp_opp_table: opp-table { 5314 compatible = "operating-points-v2"; 5315 5316 opp-200000000 { 5317 opp-hz = /bits/ 64 <200000000>; 5318 required-opps = <&rpmhpd_opp_low_svs>; 5319 }; 5320 5321 opp-300000000 { 5322 opp-hz = /bits/ 64 <300000000>; 5323 required-opps = <&rpmhpd_opp_svs>; 5324 }; 5325 5326 opp-380000000 { 5327 opp-hz = /bits/ 64 <380000000>; 5328 required-opps = <&rpmhpd_opp_svs_l1>; 5329 }; 5330 5331 opp-506666667 { 5332 opp-hz = /bits/ 64 <506666667>; 5333 required-opps = <&rpmhpd_opp_nom>; 5334 }; 5335 5336 opp-608000000 { 5337 opp-hz = /bits/ 64 <608000000>; 5338 required-opps = <&rpmhpd_opp_turbo>; 5339 }; 5340 }; 5341 }; 5342 5343 mdss_dsi: dsi@ae94000 { 5344 compatible = "qcom,sc7280-dsi-ctrl", 5345 "qcom,mdss-dsi-ctrl"; 5346 reg = <0 0x0ae94000 0 0x400>; 5347 reg-names = "dsi_ctrl"; 5348 5349 interrupt-parent = <&mdss>; 5350 interrupts = <4>; 5351 5352 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 5353 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 5354 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 5355 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 5356 <&dispcc DISP_CC_MDSS_AHB_CLK>, 5357 <&gcc GCC_DISP_HF_AXI_CLK>; 5358 clock-names = "byte", 5359 "byte_intf", 5360 "pixel", 5361 "core", 5362 "iface", 5363 "bus"; 5364 5365 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 5366 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 5367 assigned-clock-parents = <&mdss_dsi_phy DSI_BYTE_PLL_CLK>, 5368 <&mdss_dsi_phy DSI_PIXEL_PLL_CLK>; 5369 5370 operating-points-v2 = <&dsi_opp_table>; 5371 power-domains = <&rpmhpd SC7280_CX>; 5372 5373 phys = <&mdss_dsi_phy>; 5374 5375 refgen-supply = <&refgen>; 5376 5377 #address-cells = <1>; 5378 #size-cells = <0>; 5379 5380 status = "disabled"; 5381 5382 ports { 5383 #address-cells = <1>; 5384 #size-cells = <0>; 5385 5386 port@0 { 5387 reg = <0>; 5388 mdss_dsi0_in: endpoint { 5389 remote-endpoint = <&dpu_intf1_out>; 5390 }; 5391 }; 5392 5393 port@1 { 5394 reg = <1>; 5395 mdss_dsi0_out: endpoint { 5396 }; 5397 }; 5398 }; 5399 5400 dsi_opp_table: opp-table { 5401 compatible = "operating-points-v2"; 5402 5403 opp-187500000 { 5404 opp-hz = /bits/ 64 <187500000>; 5405 required-opps = <&rpmhpd_opp_low_svs>; 5406 }; 5407 5408 opp-300000000 { 5409 opp-hz = /bits/ 64 <300000000>; 5410 required-opps = <&rpmhpd_opp_svs>; 5411 }; 5412 5413 opp-358000000 { 5414 opp-hz = /bits/ 64 <358000000>; 5415 required-opps = <&rpmhpd_opp_svs_l1>; 5416 }; 5417 }; 5418 }; 5419 5420 mdss_dsi_phy: phy@ae94400 { 5421 compatible = "qcom,sc7280-dsi-phy-7nm"; 5422 reg = <0 0x0ae94400 0 0x200>, 5423 <0 0x0ae94600 0 0x280>, 5424 <0 0x0ae94900 0 0x280>; 5425 reg-names = "dsi_phy", 5426 "dsi_phy_lane", 5427 "dsi_pll"; 5428 5429 #clock-cells = <1>; 5430 #phy-cells = <0>; 5431 5432 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 5433 <&rpmhcc RPMH_CXO_CLK>; 5434 clock-names = "iface", "ref"; 5435 5436 status = "disabled"; 5437 }; 5438 5439 mdss_edp: edp@aea0000 { 5440 compatible = "qcom,sc7280-edp"; 5441 pinctrl-names = "default"; 5442 pinctrl-0 = <&edp_hot_plug_det>; 5443 5444 reg = <0 0x0aea0000 0 0x200>, 5445 <0 0x0aea0200 0 0x200>, 5446 <0 0x0aea0400 0 0xc00>, 5447 <0 0x0aea1000 0 0x400>, 5448 <0 0x0aea1400 0 0x400>; 5449 5450 interrupt-parent = <&mdss>; 5451 interrupts = <14>; 5452 5453 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 5454 <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>, 5455 <&dispcc DISP_CC_MDSS_EDP_LINK_CLK>, 5456 <&dispcc DISP_CC_MDSS_EDP_LINK_INTF_CLK>, 5457 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK>; 5458 clock-names = "core_iface", 5459 "core_aux", 5460 "ctrl_link", 5461 "ctrl_link_iface", 5462 "stream_pixel"; 5463 assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>, 5464 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>; 5465 assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>; 5466 5467 phys = <&mdss_edp_phy>; 5468 phy-names = "dp"; 5469 5470 operating-points-v2 = <&edp_opp_table>; 5471 power-domains = <&rpmhpd SC7280_CX>; 5472 5473 status = "disabled"; 5474 5475 ports { 5476 #address-cells = <1>; 5477 #size-cells = <0>; 5478 5479 port@0 { 5480 reg = <0>; 5481 edp_in: endpoint { 5482 remote-endpoint = <&dpu_intf5_out>; 5483 }; 5484 }; 5485 5486 port@1 { 5487 reg = <1>; 5488 mdss_edp_out: endpoint { }; 5489 }; 5490 }; 5491 5492 edp_opp_table: opp-table { 5493 compatible = "operating-points-v2"; 5494 5495 opp-160000000 { 5496 opp-hz = /bits/ 64 <160000000>; 5497 required-opps = <&rpmhpd_opp_low_svs>; 5498 }; 5499 5500 opp-270000000 { 5501 opp-hz = /bits/ 64 <270000000>; 5502 required-opps = <&rpmhpd_opp_svs>; 5503 }; 5504 5505 opp-540000000 { 5506 opp-hz = /bits/ 64 <540000000>; 5507 required-opps = <&rpmhpd_opp_nom>; 5508 }; 5509 5510 opp-810000000 { 5511 opp-hz = /bits/ 64 <810000000>; 5512 required-opps = <&rpmhpd_opp_nom>; 5513 }; 5514 }; 5515 }; 5516 5517 mdss_edp_phy: phy@aec2a00 { 5518 compatible = "qcom,sc7280-edp-phy"; 5519 5520 reg = <0 0x0aec2a00 0 0x19c>, 5521 <0 0x0aec2200 0 0xa0>, 5522 <0 0x0aec2600 0 0xa0>, 5523 <0 0x0aec2000 0 0x1c0>; 5524 5525 clocks = <&rpmhcc RPMH_CXO_CLK>, 5526 <&gcc GCC_EDP_CLKREF_EN>; 5527 clock-names = "aux", 5528 "cfg_ahb"; 5529 5530 #clock-cells = <1>; 5531 #phy-cells = <0>; 5532 5533 status = "disabled"; 5534 }; 5535 5536 mdss_dp: displayport-controller@ae90000 { 5537 compatible = "qcom,sc7280-dp"; 5538 5539 reg = <0 0x0ae90000 0 0x200>, 5540 <0 0x0ae90200 0 0x200>, 5541 <0 0x0ae90400 0 0xc00>, 5542 <0 0x0ae91000 0 0x400>, 5543 <0 0x0ae91400 0 0x400>; 5544 5545 interrupt-parent = <&mdss>; 5546 interrupts = <12>; 5547 5548 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 5549 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 5550 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 5551 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 5552 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 5553 clock-names = "core_iface", 5554 "core_aux", 5555 "ctrl_link", 5556 "ctrl_link_iface", 5557 "stream_pixel"; 5558 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 5559 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 5560 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 5561 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 5562 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; 5563 phy-names = "dp"; 5564 5565 operating-points-v2 = <&dp_opp_table>; 5566 power-domains = <&rpmhpd SC7280_CX>; 5567 5568 #sound-dai-cells = <0>; 5569 5570 status = "disabled"; 5571 5572 ports { 5573 #address-cells = <1>; 5574 #size-cells = <0>; 5575 5576 port@0 { 5577 reg = <0>; 5578 dp_in: endpoint { 5579 remote-endpoint = <&dpu_intf0_out>; 5580 }; 5581 }; 5582 5583 port@1 { 5584 reg = <1>; 5585 mdss_dp_out: endpoint { 5586 remote-endpoint = <&usb_dp_qmpphy_dp_in>; 5587 }; 5588 }; 5589 }; 5590 5591 dp_opp_table: opp-table { 5592 compatible = "operating-points-v2"; 5593 5594 opp-160000000 { 5595 opp-hz = /bits/ 64 <160000000>; 5596 required-opps = <&rpmhpd_opp_low_svs>; 5597 }; 5598 5599 opp-270000000 { 5600 opp-hz = /bits/ 64 <270000000>; 5601 required-opps = <&rpmhpd_opp_svs>; 5602 }; 5603 5604 opp-540000000 { 5605 opp-hz = /bits/ 64 <540000000>; 5606 required-opps = <&rpmhpd_opp_svs_l1>; 5607 }; 5608 5609 opp-810000000 { 5610 opp-hz = /bits/ 64 <810000000>; 5611 required-opps = <&rpmhpd_opp_nom>; 5612 }; 5613 }; 5614 }; 5615 }; 5616 5617 pdc: interrupt-controller@b220000 { 5618 compatible = "qcom,sc7280-pdc", "qcom,pdc"; 5619 reg = <0 0x0b220000 0 0x30000>; 5620 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, 5621 <55 306 4>, <59 312 3>, <62 374 2>, 5622 <64 434 2>, <66 438 3>, <69 86 1>, 5623 <70 520 54>, <124 609 31>, <155 63 1>, 5624 <156 716 12>; 5625 #interrupt-cells = <2>; 5626 interrupt-parent = <&intc>; 5627 interrupt-controller; 5628 }; 5629 5630 pdc_reset: reset-controller@b5e0000 { 5631 compatible = "qcom,sc7280-pdc-global"; 5632 reg = <0 0x0b5e0000 0 0x20000>; 5633 #reset-cells = <1>; 5634 status = "reserved"; /* Owned by firmware */ 5635 }; 5636 5637 tsens0: thermal-sensor@c263000 { 5638 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 5639 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 5640 <0 0x0c222000 0 0x1ff>; /* SROT */ 5641 #qcom,sensors = <15>; 5642 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 5643 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 5644 interrupt-names = "uplow","critical"; 5645 #thermal-sensor-cells = <1>; 5646 }; 5647 5648 tsens1: thermal-sensor@c265000 { 5649 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 5650 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 5651 <0 0x0c223000 0 0x1ff>; /* SROT */ 5652 #qcom,sensors = <12>; 5653 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 5654 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 5655 interrupt-names = "uplow","critical"; 5656 #thermal-sensor-cells = <1>; 5657 }; 5658 5659 aoss_reset: reset-controller@c2a0000 { 5660 compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc"; 5661 reg = <0 0x0c2a0000 0 0x31000>; 5662 #reset-cells = <1>; 5663 }; 5664 5665 aoss_qmp: power-management@c300000 { 5666 compatible = "qcom,sc7280-aoss-qmp", "qcom,aoss-qmp"; 5667 reg = <0 0x0c300000 0 0x400>; 5668 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 5669 IPCC_MPROC_SIGNAL_GLINK_QMP 5670 IRQ_TYPE_EDGE_RISING>; 5671 mboxes = <&ipcc IPCC_CLIENT_AOP 5672 IPCC_MPROC_SIGNAL_GLINK_QMP>; 5673 5674 #clock-cells = <0>; 5675 }; 5676 5677 sram@c3f0000 { 5678 compatible = "qcom,rpmh-stats"; 5679 reg = <0 0x0c3f0000 0 0x400>; 5680 }; 5681 5682 spmi_bus: spmi@c440000 { 5683 compatible = "qcom,spmi-pmic-arb"; 5684 reg = <0 0x0c440000 0 0x1100>, 5685 <0 0x0c600000 0 0x2000000>, 5686 <0 0x0e600000 0 0x100000>, 5687 <0 0x0e700000 0 0xa0000>, 5688 <0 0x0c40a000 0 0x26000>; 5689 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 5690 interrupt-names = "periph_irq"; 5691 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 5692 qcom,ee = <0>; 5693 qcom,channel = <0>; 5694 #address-cells = <2>; 5695 #size-cells = <0>; 5696 interrupt-controller; 5697 #interrupt-cells = <4>; 5698 }; 5699 5700 tlmm: pinctrl@f100000 { 5701 compatible = "qcom,sc7280-pinctrl"; 5702 reg = <0 0x0f100000 0 0x300000>; 5703 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 5704 gpio-controller; 5705 #gpio-cells = <2>; 5706 interrupt-controller; 5707 #interrupt-cells = <2>; 5708 gpio-ranges = <&tlmm 0 0 175>; 5709 wakeup-parent = <&pdc>; 5710 5711 cci0_default: cci0-default-state { 5712 pins = "gpio69", "gpio70"; 5713 function = "cci_i2c"; 5714 drive-strength = <2>; 5715 bias-pull-up; 5716 }; 5717 5718 cci0_sleep: cci0-sleep-state { 5719 pins = "gpio69", "gpio70"; 5720 function = "cci_i2c"; 5721 drive-strength = <2>; 5722 bias-pull-down; 5723 }; 5724 5725 cci1_default: cci1-default-state { 5726 pins = "gpio71", "gpio72"; 5727 function = "cci_i2c"; 5728 drive-strength = <2>; 5729 bias-pull-up; 5730 }; 5731 5732 cci1_sleep: cci1-sleep-state { 5733 pins = "gpio71", "gpio72"; 5734 function = "cci_i2c"; 5735 drive-strength = <2>; 5736 bias-pull-down; 5737 }; 5738 5739 cci2_default: cci2-default-state { 5740 pins = "gpio73", "gpio74"; 5741 function = "cci_i2c"; 5742 drive-strength = <2>; 5743 bias-pull-up; 5744 }; 5745 5746 cci2_sleep: cci2-sleep-state { 5747 pins = "gpio73", "gpio74"; 5748 function = "cci_i2c"; 5749 drive-strength = <2>; 5750 bias-pull-down; 5751 }; 5752 5753 cci3_default: cci3-default-state { 5754 pins = "gpio75", "gpio76"; 5755 function = "cci_i2c"; 5756 drive-strength = <2>; 5757 bias-pull-up; 5758 }; 5759 5760 cci3_sleep: cci3-sleep-state { 5761 pins = "gpio75", "gpio76"; 5762 function = "cci_i2c"; 5763 drive-strength = <2>; 5764 bias-pull-down; 5765 }; 5766 5767 dp_hot_plug_det: dp-hot-plug-det-state { 5768 pins = "gpio47"; 5769 function = "dp_hot"; 5770 }; 5771 5772 edp_hot_plug_det: edp-hot-plug-det-state { 5773 pins = "gpio60"; 5774 function = "edp_hot"; 5775 }; 5776 5777 mi2s0_data0: mi2s0-data0-state { 5778 pins = "gpio98"; 5779 function = "mi2s0_data0"; 5780 }; 5781 5782 mi2s0_data1: mi2s0-data1-state { 5783 pins = "gpio99"; 5784 function = "mi2s0_data1"; 5785 }; 5786 5787 mi2s0_mclk: mi2s0-mclk-state { 5788 pins = "gpio96"; 5789 function = "pri_mi2s"; 5790 }; 5791 5792 mi2s0_sclk: mi2s0-sclk-state { 5793 pins = "gpio97"; 5794 function = "mi2s0_sck"; 5795 }; 5796 5797 mi2s0_ws: mi2s0-ws-state { 5798 pins = "gpio100"; 5799 function = "mi2s0_ws"; 5800 }; 5801 5802 mi2s1_data0: mi2s1-data0-state { 5803 pins = "gpio107"; 5804 function = "mi2s1_data0"; 5805 }; 5806 5807 mi2s1_sclk: mi2s1-sclk-state { 5808 pins = "gpio106"; 5809 function = "mi2s1_sck"; 5810 }; 5811 5812 mi2s1_ws: mi2s1-ws-state { 5813 pins = "gpio108"; 5814 function = "mi2s1_ws"; 5815 }; 5816 5817 pcie0_clkreq_n: pcie0-clkreq-n-state { 5818 pins = "gpio88"; 5819 function = "pcie0_clkreqn"; 5820 }; 5821 5822 pcie1_clkreq_n: pcie1-clkreq-n-state { 5823 pins = "gpio79"; 5824 function = "pcie1_clkreqn"; 5825 }; 5826 5827 qspi_clk: qspi-clk-state { 5828 pins = "gpio14"; 5829 function = "qspi_clk"; 5830 }; 5831 5832 qspi_cs0: qspi-cs0-state { 5833 pins = "gpio15"; 5834 function = "qspi_cs"; 5835 }; 5836 5837 qspi_cs1: qspi-cs1-state { 5838 pins = "gpio19"; 5839 function = "qspi_cs"; 5840 }; 5841 5842 qspi_data0: qspi-data0-state { 5843 pins = "gpio12"; 5844 function = "qspi_data"; 5845 }; 5846 5847 qspi_data1: qspi-data1-state { 5848 pins = "gpio13"; 5849 function = "qspi_data"; 5850 }; 5851 5852 qspi_data23: qspi-data23-state { 5853 pins = "gpio16", "gpio17"; 5854 function = "qspi_data"; 5855 }; 5856 5857 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 5858 pins = "gpio0", "gpio1"; 5859 function = "qup00"; 5860 }; 5861 5862 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 5863 pins = "gpio4", "gpio5"; 5864 function = "qup01"; 5865 }; 5866 5867 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 5868 pins = "gpio8", "gpio9"; 5869 function = "qup02"; 5870 }; 5871 5872 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 5873 pins = "gpio12", "gpio13"; 5874 function = "qup03"; 5875 }; 5876 5877 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 5878 pins = "gpio16", "gpio17"; 5879 function = "qup04"; 5880 }; 5881 5882 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 5883 pins = "gpio20", "gpio21"; 5884 function = "qup05"; 5885 }; 5886 5887 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 5888 pins = "gpio24", "gpio25"; 5889 function = "qup06"; 5890 }; 5891 5892 qup_i2c7_data_clk: qup-i2c7-data-clk-state { 5893 pins = "gpio28", "gpio29"; 5894 function = "qup07"; 5895 }; 5896 5897 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 5898 pins = "gpio32", "gpio33"; 5899 function = "qup10"; 5900 }; 5901 5902 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 5903 pins = "gpio36", "gpio37"; 5904 function = "qup11"; 5905 }; 5906 5907 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 5908 pins = "gpio40", "gpio41"; 5909 function = "qup12"; 5910 }; 5911 5912 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 5913 pins = "gpio44", "gpio45"; 5914 function = "qup13"; 5915 }; 5916 5917 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 5918 pins = "gpio48", "gpio49"; 5919 function = "qup14"; 5920 }; 5921 5922 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 5923 pins = "gpio52", "gpio53"; 5924 function = "qup15"; 5925 }; 5926 5927 qup_i2c14_data_clk: qup-i2c14-data-clk-state { 5928 pins = "gpio56", "gpio57"; 5929 function = "qup16"; 5930 }; 5931 5932 qup_i2c15_data_clk: qup-i2c15-data-clk-state { 5933 pins = "gpio60", "gpio61"; 5934 function = "qup17"; 5935 }; 5936 5937 qup_spi0_data_clk: qup-spi0-data-clk-state { 5938 pins = "gpio0", "gpio1", "gpio2"; 5939 function = "qup00"; 5940 }; 5941 5942 qup_spi0_cs: qup-spi0-cs-state { 5943 pins = "gpio3"; 5944 function = "qup00"; 5945 }; 5946 5947 qup_spi0_cs_gpio: qup-spi0-cs-gpio-state { 5948 pins = "gpio3"; 5949 function = "gpio"; 5950 }; 5951 5952 qup_spi1_data_clk: qup-spi1-data-clk-state { 5953 pins = "gpio4", "gpio5", "gpio6"; 5954 function = "qup01"; 5955 }; 5956 5957 qup_spi1_cs: qup-spi1-cs-state { 5958 pins = "gpio7"; 5959 function = "qup01"; 5960 }; 5961 5962 qup_spi1_cs_gpio: qup-spi1-cs-gpio-state { 5963 pins = "gpio7"; 5964 function = "gpio"; 5965 }; 5966 5967 qup_spi2_data_clk: qup-spi2-data-clk-state { 5968 pins = "gpio8", "gpio9", "gpio10"; 5969 function = "qup02"; 5970 }; 5971 5972 qup_spi2_cs: qup-spi2-cs-state { 5973 pins = "gpio11"; 5974 function = "qup02"; 5975 }; 5976 5977 qup_spi2_cs_gpio: qup-spi2-cs-gpio-state { 5978 pins = "gpio11"; 5979 function = "gpio"; 5980 }; 5981 5982 qup_spi3_data_clk: qup-spi3-data-clk-state { 5983 pins = "gpio12", "gpio13", "gpio14"; 5984 function = "qup03"; 5985 }; 5986 5987 qup_spi3_cs: qup-spi3-cs-state { 5988 pins = "gpio15"; 5989 function = "qup03"; 5990 }; 5991 5992 qup_spi3_cs_gpio: qup-spi3-cs-gpio-state { 5993 pins = "gpio15"; 5994 function = "gpio"; 5995 }; 5996 5997 qup_spi4_data_clk: qup-spi4-data-clk-state { 5998 pins = "gpio16", "gpio17", "gpio18"; 5999 function = "qup04"; 6000 }; 6001 6002 qup_spi4_cs: qup-spi4-cs-state { 6003 pins = "gpio19"; 6004 function = "qup04"; 6005 }; 6006 6007 qup_spi4_cs_gpio: qup-spi4-cs-gpio-state { 6008 pins = "gpio19"; 6009 function = "gpio"; 6010 }; 6011 6012 qup_spi5_data_clk: qup-spi5-data-clk-state { 6013 pins = "gpio20", "gpio21", "gpio22"; 6014 function = "qup05"; 6015 }; 6016 6017 qup_spi5_cs: qup-spi5-cs-state { 6018 pins = "gpio23"; 6019 function = "qup05"; 6020 }; 6021 6022 qup_spi5_cs_gpio: qup-spi5-cs-gpio-state { 6023 pins = "gpio23"; 6024 function = "gpio"; 6025 }; 6026 6027 qup_spi6_data_clk: qup-spi6-data-clk-state { 6028 pins = "gpio24", "gpio25", "gpio26"; 6029 function = "qup06"; 6030 }; 6031 6032 qup_spi6_cs: qup-spi6-cs-state { 6033 pins = "gpio27"; 6034 function = "qup06"; 6035 }; 6036 6037 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state { 6038 pins = "gpio27"; 6039 function = "gpio"; 6040 }; 6041 6042 qup_spi7_data_clk: qup-spi7-data-clk-state { 6043 pins = "gpio28", "gpio29", "gpio30"; 6044 function = "qup07"; 6045 }; 6046 6047 qup_spi7_cs: qup-spi7-cs-state { 6048 pins = "gpio31"; 6049 function = "qup07"; 6050 }; 6051 6052 qup_spi7_cs_gpio: qup-spi7-cs-gpio-state { 6053 pins = "gpio31"; 6054 function = "gpio"; 6055 }; 6056 6057 qup_spi8_data_clk: qup-spi8-data-clk-state { 6058 pins = "gpio32", "gpio33", "gpio34"; 6059 function = "qup10"; 6060 }; 6061 6062 qup_spi8_cs: qup-spi8-cs-state { 6063 pins = "gpio35"; 6064 function = "qup10"; 6065 }; 6066 6067 qup_spi8_cs_gpio: qup-spi8-cs-gpio-state { 6068 pins = "gpio35"; 6069 function = "gpio"; 6070 }; 6071 6072 qup_spi9_data_clk: qup-spi9-data-clk-state { 6073 pins = "gpio36", "gpio37", "gpio38"; 6074 function = "qup11"; 6075 }; 6076 6077 qup_spi9_cs: qup-spi9-cs-state { 6078 pins = "gpio39"; 6079 function = "qup11"; 6080 }; 6081 6082 qup_spi9_cs_gpio: qup-spi9-cs-gpio-state { 6083 pins = "gpio39"; 6084 function = "gpio"; 6085 }; 6086 6087 qup_spi10_data_clk: qup-spi10-data-clk-state { 6088 pins = "gpio40", "gpio41", "gpio42"; 6089 function = "qup12"; 6090 }; 6091 6092 qup_spi10_cs: qup-spi10-cs-state { 6093 pins = "gpio43"; 6094 function = "qup12"; 6095 }; 6096 6097 qup_spi10_cs_gpio: qup-spi10-cs-gpio-state { 6098 pins = "gpio43"; 6099 function = "gpio"; 6100 }; 6101 6102 qup_spi11_data_clk: qup-spi11-data-clk-state { 6103 pins = "gpio44", "gpio45", "gpio46"; 6104 function = "qup13"; 6105 }; 6106 6107 qup_spi11_cs: qup-spi11-cs-state { 6108 pins = "gpio47"; 6109 function = "qup13"; 6110 }; 6111 6112 qup_spi11_cs_gpio: qup-spi11-cs-gpio-state { 6113 pins = "gpio47"; 6114 function = "gpio"; 6115 }; 6116 6117 qup_spi12_data_clk: qup-spi12-data-clk-state { 6118 pins = "gpio48", "gpio49", "gpio50"; 6119 function = "qup14"; 6120 }; 6121 6122 qup_spi12_cs: qup-spi12-cs-state { 6123 pins = "gpio51"; 6124 function = "qup14"; 6125 }; 6126 6127 qup_spi12_cs_gpio: qup-spi12-cs-gpio-state { 6128 pins = "gpio51"; 6129 function = "gpio"; 6130 }; 6131 6132 qup_spi13_data_clk: qup-spi13-data-clk-state { 6133 pins = "gpio52", "gpio53", "gpio54"; 6134 function = "qup15"; 6135 }; 6136 6137 qup_spi13_cs: qup-spi13-cs-state { 6138 pins = "gpio55"; 6139 function = "qup15"; 6140 }; 6141 6142 qup_spi13_cs_gpio: qup-spi13-cs-gpio-state { 6143 pins = "gpio55"; 6144 function = "gpio"; 6145 }; 6146 6147 qup_spi14_data_clk: qup-spi14-data-clk-state { 6148 pins = "gpio56", "gpio57", "gpio58"; 6149 function = "qup16"; 6150 }; 6151 6152 qup_spi14_cs: qup-spi14-cs-state { 6153 pins = "gpio59"; 6154 function = "qup16"; 6155 }; 6156 6157 qup_spi14_cs_gpio: qup-spi14-cs-gpio-state { 6158 pins = "gpio59"; 6159 function = "gpio"; 6160 }; 6161 6162 qup_spi15_data_clk: qup-spi15-data-clk-state { 6163 pins = "gpio60", "gpio61", "gpio62"; 6164 function = "qup17"; 6165 }; 6166 6167 qup_spi15_cs: qup-spi15-cs-state { 6168 pins = "gpio63"; 6169 function = "qup17"; 6170 }; 6171 6172 qup_spi15_cs_gpio: qup-spi15-cs-gpio-state { 6173 pins = "gpio63"; 6174 function = "gpio"; 6175 }; 6176 6177 qup_uart0_cts: qup-uart0-cts-state { 6178 pins = "gpio0"; 6179 function = "qup00"; 6180 }; 6181 6182 qup_uart0_rts: qup-uart0-rts-state { 6183 pins = "gpio1"; 6184 function = "qup00"; 6185 }; 6186 6187 qup_uart0_tx: qup-uart0-tx-state { 6188 pins = "gpio2"; 6189 function = "qup00"; 6190 }; 6191 6192 qup_uart0_rx: qup-uart0-rx-state { 6193 pins = "gpio3"; 6194 function = "qup00"; 6195 }; 6196 6197 qup_uart1_cts: qup-uart1-cts-state { 6198 pins = "gpio4"; 6199 function = "qup01"; 6200 }; 6201 6202 qup_uart1_rts: qup-uart1-rts-state { 6203 pins = "gpio5"; 6204 function = "qup01"; 6205 }; 6206 6207 qup_uart1_tx: qup-uart1-tx-state { 6208 pins = "gpio6"; 6209 function = "qup01"; 6210 }; 6211 6212 qup_uart1_rx: qup-uart1-rx-state { 6213 pins = "gpio7"; 6214 function = "qup01"; 6215 }; 6216 6217 qup_uart2_cts: qup-uart2-cts-state { 6218 pins = "gpio8"; 6219 function = "qup02"; 6220 }; 6221 6222 qup_uart2_rts: qup-uart2-rts-state { 6223 pins = "gpio9"; 6224 function = "qup02"; 6225 }; 6226 6227 qup_uart2_tx: qup-uart2-tx-state { 6228 pins = "gpio10"; 6229 function = "qup02"; 6230 }; 6231 6232 qup_uart2_rx: qup-uart2-rx-state { 6233 pins = "gpio11"; 6234 function = "qup02"; 6235 }; 6236 6237 qup_uart3_cts: qup-uart3-cts-state { 6238 pins = "gpio12"; 6239 function = "qup03"; 6240 }; 6241 6242 qup_uart3_rts: qup-uart3-rts-state { 6243 pins = "gpio13"; 6244 function = "qup03"; 6245 }; 6246 6247 qup_uart3_tx: qup-uart3-tx-state { 6248 pins = "gpio14"; 6249 function = "qup03"; 6250 }; 6251 6252 qup_uart3_rx: qup-uart3-rx-state { 6253 pins = "gpio15"; 6254 function = "qup03"; 6255 }; 6256 6257 qup_uart4_cts: qup-uart4-cts-state { 6258 pins = "gpio16"; 6259 function = "qup04"; 6260 }; 6261 6262 qup_uart4_rts: qup-uart4-rts-state { 6263 pins = "gpio17"; 6264 function = "qup04"; 6265 }; 6266 6267 qup_uart4_tx: qup-uart4-tx-state { 6268 pins = "gpio18"; 6269 function = "qup04"; 6270 }; 6271 6272 qup_uart4_rx: qup-uart4-rx-state { 6273 pins = "gpio19"; 6274 function = "qup04"; 6275 }; 6276 6277 qup_uart5_tx: qup-uart5-tx-state { 6278 pins = "gpio22"; 6279 function = "qup05"; 6280 }; 6281 6282 qup_uart5_rx: qup-uart5-rx-state { 6283 pins = "gpio23"; 6284 function = "qup05"; 6285 }; 6286 6287 qup_uart6_cts: qup-uart6-cts-state { 6288 pins = "gpio24"; 6289 function = "qup06"; 6290 }; 6291 6292 qup_uart6_rts: qup-uart6-rts-state { 6293 pins = "gpio25"; 6294 function = "qup06"; 6295 }; 6296 6297 qup_uart6_tx: qup-uart6-tx-state { 6298 pins = "gpio26"; 6299 function = "qup06"; 6300 }; 6301 6302 qup_uart6_rx: qup-uart6-rx-state { 6303 pins = "gpio27"; 6304 function = "qup06"; 6305 }; 6306 6307 qup_uart7_cts: qup-uart7-cts-state { 6308 pins = "gpio28"; 6309 function = "qup07"; 6310 }; 6311 6312 qup_uart7_rts: qup-uart7-rts-state { 6313 pins = "gpio29"; 6314 function = "qup07"; 6315 }; 6316 6317 qup_uart7_tx: qup-uart7-tx-state { 6318 pins = "gpio30"; 6319 function = "qup07"; 6320 }; 6321 6322 qup_uart7_rx: qup-uart7-rx-state { 6323 pins = "gpio31"; 6324 function = "qup07"; 6325 }; 6326 6327 qup_uart8_cts: qup-uart8-cts-state { 6328 pins = "gpio32"; 6329 function = "qup10"; 6330 }; 6331 6332 qup_uart8_rts: qup-uart8-rts-state { 6333 pins = "gpio33"; 6334 function = "qup10"; 6335 }; 6336 6337 qup_uart8_tx: qup-uart8-tx-state { 6338 pins = "gpio34"; 6339 function = "qup10"; 6340 }; 6341 6342 qup_uart8_rx: qup-uart8-rx-state { 6343 pins = "gpio35"; 6344 function = "qup10"; 6345 }; 6346 6347 qup_uart9_cts: qup-uart9-cts-state { 6348 pins = "gpio36"; 6349 function = "qup11"; 6350 }; 6351 6352 qup_uart9_rts: qup-uart9-rts-state { 6353 pins = "gpio37"; 6354 function = "qup11"; 6355 }; 6356 6357 qup_uart9_tx: qup-uart9-tx-state { 6358 pins = "gpio38"; 6359 function = "qup11"; 6360 }; 6361 6362 qup_uart9_rx: qup-uart9-rx-state { 6363 pins = "gpio39"; 6364 function = "qup11"; 6365 }; 6366 6367 qup_uart10_cts: qup-uart10-cts-state { 6368 pins = "gpio40"; 6369 function = "qup12"; 6370 }; 6371 6372 qup_uart10_rts: qup-uart10-rts-state { 6373 pins = "gpio41"; 6374 function = "qup12"; 6375 }; 6376 6377 qup_uart10_tx: qup-uart10-tx-state { 6378 pins = "gpio42"; 6379 function = "qup12"; 6380 }; 6381 6382 qup_uart10_rx: qup-uart10-rx-state { 6383 pins = "gpio43"; 6384 function = "qup12"; 6385 }; 6386 6387 qup_uart11_cts: qup-uart11-cts-state { 6388 pins = "gpio44"; 6389 function = "qup13"; 6390 }; 6391 6392 qup_uart11_rts: qup-uart11-rts-state { 6393 pins = "gpio45"; 6394 function = "qup13"; 6395 }; 6396 6397 qup_uart11_tx: qup-uart11-tx-state { 6398 pins = "gpio46"; 6399 function = "qup13"; 6400 }; 6401 6402 qup_uart11_rx: qup-uart11-rx-state { 6403 pins = "gpio47"; 6404 function = "qup13"; 6405 }; 6406 6407 qup_uart12_cts: qup-uart12-cts-state { 6408 pins = "gpio48"; 6409 function = "qup14"; 6410 }; 6411 6412 qup_uart12_rts: qup-uart12-rts-state { 6413 pins = "gpio49"; 6414 function = "qup14"; 6415 }; 6416 6417 qup_uart12_tx: qup-uart12-tx-state { 6418 pins = "gpio50"; 6419 function = "qup14"; 6420 }; 6421 6422 qup_uart12_rx: qup-uart12-rx-state { 6423 pins = "gpio51"; 6424 function = "qup14"; 6425 }; 6426 6427 qup_uart13_cts: qup-uart13-cts-state { 6428 pins = "gpio52"; 6429 function = "qup15"; 6430 }; 6431 6432 qup_uart13_rts: qup-uart13-rts-state { 6433 pins = "gpio53"; 6434 function = "qup15"; 6435 }; 6436 6437 qup_uart13_tx: qup-uart13-tx-state { 6438 pins = "gpio54"; 6439 function = "qup15"; 6440 }; 6441 6442 qup_uart13_rx: qup-uart13-rx-state { 6443 pins = "gpio55"; 6444 function = "qup15"; 6445 }; 6446 6447 qup_uart14_cts: qup-uart14-cts-state { 6448 pins = "gpio56"; 6449 function = "qup16"; 6450 }; 6451 6452 qup_uart14_rts: qup-uart14-rts-state { 6453 pins = "gpio57"; 6454 function = "qup16"; 6455 }; 6456 6457 qup_uart14_tx: qup-uart14-tx-state { 6458 pins = "gpio58"; 6459 function = "qup16"; 6460 }; 6461 6462 qup_uart14_rx: qup-uart14-rx-state { 6463 pins = "gpio59"; 6464 function = "qup16"; 6465 }; 6466 6467 qup_uart15_cts: qup-uart15-cts-state { 6468 pins = "gpio60"; 6469 function = "qup17"; 6470 }; 6471 6472 qup_uart15_rts: qup-uart15-rts-state { 6473 pins = "gpio61"; 6474 function = "qup17"; 6475 }; 6476 6477 qup_uart15_tx: qup-uart15-tx-state { 6478 pins = "gpio62"; 6479 function = "qup17"; 6480 }; 6481 6482 qup_uart15_rx: qup-uart15-rx-state { 6483 pins = "gpio63"; 6484 function = "qup17"; 6485 }; 6486 6487 sdc1_clk: sdc1-clk-state { 6488 pins = "sdc1_clk"; 6489 }; 6490 6491 sdc1_cmd: sdc1-cmd-state { 6492 pins = "sdc1_cmd"; 6493 }; 6494 6495 sdc1_data: sdc1-data-state { 6496 pins = "sdc1_data"; 6497 }; 6498 6499 sdc1_rclk: sdc1-rclk-state { 6500 pins = "sdc1_rclk"; 6501 }; 6502 6503 sdc1_clk_sleep: sdc1-clk-sleep-state { 6504 pins = "sdc1_clk"; 6505 drive-strength = <2>; 6506 bias-bus-hold; 6507 }; 6508 6509 sdc1_cmd_sleep: sdc1-cmd-sleep-state { 6510 pins = "sdc1_cmd"; 6511 drive-strength = <2>; 6512 bias-bus-hold; 6513 }; 6514 6515 sdc1_data_sleep: sdc1-data-sleep-state { 6516 pins = "sdc1_data"; 6517 drive-strength = <2>; 6518 bias-bus-hold; 6519 }; 6520 6521 sdc1_rclk_sleep: sdc1-rclk-sleep-state { 6522 pins = "sdc1_rclk"; 6523 drive-strength = <2>; 6524 bias-bus-hold; 6525 }; 6526 6527 sdc2_clk: sdc2-clk-state { 6528 pins = "sdc2_clk"; 6529 }; 6530 6531 sdc2_cmd: sdc2-cmd-state { 6532 pins = "sdc2_cmd"; 6533 }; 6534 6535 sdc2_data: sdc2-data-state { 6536 pins = "sdc2_data"; 6537 }; 6538 6539 sdc2_clk_sleep: sdc2-clk-sleep-state { 6540 pins = "sdc2_clk"; 6541 drive-strength = <2>; 6542 bias-bus-hold; 6543 }; 6544 6545 sdc2_cmd_sleep: sdc2-cmd-sleep-state { 6546 pins = "sdc2_cmd"; 6547 drive-strength = <2>; 6548 bias-bus-hold; 6549 }; 6550 6551 sdc2_data_sleep: sdc2-data-sleep-state { 6552 pins = "sdc2_data"; 6553 drive-strength = <2>; 6554 bias-bus-hold; 6555 }; 6556 }; 6557 6558 sram@146a5000 { 6559 compatible = "qcom,sc7280-imem", "syscon", "simple-mfd"; 6560 reg = <0 0x146a5000 0 0x6000>; 6561 6562 #address-cells = <1>; 6563 #size-cells = <1>; 6564 6565 ranges = <0 0 0x146a5000 0x6000>; 6566 6567 pil-reloc@594c { 6568 compatible = "qcom,pil-reloc-info"; 6569 reg = <0x594c 0xc8>; 6570 }; 6571 }; 6572 6573 apps_smmu: iommu@15000000 { 6574 compatible = "qcom,sc7280-smmu-500", "arm,mmu-500"; 6575 reg = <0 0x15000000 0 0x100000>; 6576 #iommu-cells = <2>; 6577 #global-interrupts = <1>; 6578 dma-coherent; 6579 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 6580 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 6581 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 6582 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 6583 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 6584 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 6585 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 6586 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 6587 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 6588 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 6589 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 6590 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 6591 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 6592 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 6593 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 6594 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 6595 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 6596 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 6597 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 6598 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 6599 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 6600 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 6601 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 6602 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 6603 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 6604 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 6605 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 6606 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 6607 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 6608 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 6609 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 6610 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 6611 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 6612 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 6613 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 6614 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 6615 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 6616 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 6617 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 6618 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 6619 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 6620 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 6621 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 6622 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 6623 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 6624 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 6625 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 6626 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 6627 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 6628 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 6629 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 6630 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 6631 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 6632 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 6633 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 6634 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 6635 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 6636 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 6637 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 6638 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 6639 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 6640 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 6641 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 6642 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 6643 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 6644 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 6645 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 6646 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 6647 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 6648 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 6649 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 6650 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 6651 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 6652 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 6653 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 6654 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 6655 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 6656 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 6657 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 6658 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 6659 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 6660 }; 6661 6662 anoc_1_tbu: tbu@151dd000 { 6663 compatible = "qcom,sc7280-tbu"; 6664 reg = <0x0 0x151dd000 0x0 0x1000>; 6665 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 6666 &cnoc3 SLAVE_TCU QCOM_ICC_TAG_ACTIVE_ONLY>; 6667 qcom,stream-id-range = <&apps_smmu 0x0 0x400>; 6668 }; 6669 6670 anoc_2_tbu: tbu@151e1000 { 6671 compatible = "qcom,sc7280-tbu"; 6672 reg = <0x0 0x151e1000 0x0 0x1000>; 6673 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 6674 &cnoc3 SLAVE_TCU QCOM_ICC_TAG_ACTIVE_ONLY>; 6675 qcom,stream-id-range = <&apps_smmu 0x400 0x400>; 6676 }; 6677 6678 mnoc_hf_0_tbu: tbu@151e5000 { 6679 compatible = "qcom,sc7280-tbu"; 6680 reg = <0x0 0x151e5000 0x0 0x1000>; 6681 interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ACTIVE_ONLY 6682 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 6683 power-domains = <&gcc HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC>; 6684 qcom,stream-id-range = <&apps_smmu 0x800 0x400>; 6685 }; 6686 6687 mnoc_hf_1_tbu: tbu@151e9000 { 6688 compatible = "qcom,sc7280-tbu"; 6689 reg = <0x0 0x151e9000 0x0 0x1000>; 6690 interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ACTIVE_ONLY 6691 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 6692 power-domains = <&gcc HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC>; 6693 qcom,stream-id-range = <&apps_smmu 0xc00 0x400>; 6694 }; 6695 6696 compute_dsp_1_tbu: tbu@151ed000 { 6697 compatible = "qcom,sc7280-tbu"; 6698 reg = <0x0 0x151ed000 0x0 0x1000>; 6699 interconnects = <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ACTIVE_ONLY 6700 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 6701 power-domains = <&gcc HLOS1_VOTE_TURING_MMU_TBU1_GDSC>; 6702 qcom,stream-id-range = <&apps_smmu 0x1000 0x400>; 6703 }; 6704 6705 compute_dsp_0_tbu: tbu@151f1000 { 6706 compatible = "qcom,sc7280-tbu"; 6707 reg = <0x0 0x151f1000 0x0 0x1000>; 6708 interconnects = <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ACTIVE_ONLY 6709 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 6710 power-domains = <&gcc HLOS1_VOTE_TURING_MMU_TBU0_GDSC>; 6711 qcom,stream-id-range = <&apps_smmu 0x1400 0x400>; 6712 }; 6713 6714 adsp_tbu: tbu@151f5000 { 6715 compatible = "qcom,sc7280-tbu"; 6716 reg = <0x0 0x151f5000 0x0 0x1000>; 6717 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 6718 &lpass_ag_noc SLAVE_LPASS_CORE_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 6719 qcom,stream-id-range = <&apps_smmu 0x1800 0x400>; 6720 }; 6721 6722 anoc_1_pcie_tbu: tbu@151f9000 { 6723 compatible = "qcom,sc7280-tbu"; 6724 reg = <0x0 0x151f9000 0x0 0x1000>; 6725 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 6726 &cnoc3 SLAVE_TCU QCOM_ICC_TAG_ACTIVE_ONLY>; 6727 qcom,stream-id-range = <&apps_smmu 0x1c00 0x400>; 6728 }; 6729 6730 mnoc_sf_0_tbu: tbu@151fd000 { 6731 compatible = "qcom,sc7280-tbu"; 6732 reg = <0x0 0x151fd000 0x0 0x1000>; 6733 interconnects = <&mmss_noc MASTER_CAMNOC_SF QCOM_ICC_TAG_ACTIVE_ONLY 6734 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 6735 power-domains = <&gcc HLOS1_VOTE_MMNOC_MMU_TBU_SF0_GDSC>; 6736 qcom,stream-id-range = <&apps_smmu 0x2000 0x400>; 6737 }; 6738 6739 intc: interrupt-controller@17a00000 { 6740 compatible = "arm,gic-v3"; 6741 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 6742 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 6743 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 6744 #interrupt-cells = <3>; 6745 interrupt-controller; 6746 #address-cells = <2>; 6747 #size-cells = <2>; 6748 ranges; 6749 6750 msi-controller@17a40000 { 6751 compatible = "arm,gic-v3-its"; 6752 reg = <0 0x17a40000 0 0x20000>; 6753 msi-controller; 6754 #msi-cells = <1>; 6755 status = "disabled"; 6756 }; 6757 }; 6758 6759 watchdog: watchdog@17c10000 { 6760 compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt"; 6761 reg = <0 0x17c10000 0 0x1000>; 6762 clocks = <&sleep_clk>; 6763 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 6764 status = "reserved"; /* Owned by Gunyah hyp */ 6765 }; 6766 6767 timer@17c20000 { 6768 #address-cells = <1>; 6769 #size-cells = <1>; 6770 ranges = <0 0 0 0x20000000>; 6771 compatible = "arm,armv7-timer-mem"; 6772 reg = <0 0x17c20000 0 0x1000>; 6773 6774 frame@17c21000 { 6775 frame-number = <0>; 6776 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 6777 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 6778 reg = <0x17c21000 0x1000>, 6779 <0x17c22000 0x1000>; 6780 }; 6781 6782 frame@17c23000 { 6783 frame-number = <1>; 6784 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 6785 reg = <0x17c23000 0x1000>; 6786 status = "disabled"; 6787 }; 6788 6789 frame@17c25000 { 6790 frame-number = <2>; 6791 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 6792 reg = <0x17c25000 0x1000>; 6793 status = "disabled"; 6794 }; 6795 6796 frame@17c27000 { 6797 frame-number = <3>; 6798 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 6799 reg = <0x17c27000 0x1000>; 6800 status = "disabled"; 6801 }; 6802 6803 frame@17c29000 { 6804 frame-number = <4>; 6805 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 6806 reg = <0x17c29000 0x1000>; 6807 status = "disabled"; 6808 }; 6809 6810 frame@17c2b000 { 6811 frame-number = <5>; 6812 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 6813 reg = <0x17c2b000 0x1000>; 6814 status = "disabled"; 6815 }; 6816 6817 frame@17c2d000 { 6818 frame-number = <6>; 6819 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 6820 reg = <0x17c2d000 0x1000>; 6821 status = "disabled"; 6822 }; 6823 }; 6824 6825 apps_rsc: rsc@18200000 { 6826 compatible = "qcom,rpmh-rsc"; 6827 reg = <0 0x18200000 0 0x10000>, 6828 <0 0x18210000 0 0x10000>, 6829 <0 0x18220000 0 0x10000>; 6830 reg-names = "drv-0", "drv-1", "drv-2"; 6831 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 6832 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 6833 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 6834 qcom,tcs-offset = <0xd00>; 6835 qcom,drv-id = <2>; 6836 qcom,tcs-config = <ACTIVE_TCS 2>, 6837 <SLEEP_TCS 3>, 6838 <WAKE_TCS 3>, 6839 <CONTROL_TCS 1>; 6840 power-domains = <&cluster_pd>; 6841 6842 apps_bcm_voter: bcm-voter { 6843 compatible = "qcom,bcm-voter"; 6844 }; 6845 6846 rpmhpd: power-controller { 6847 compatible = "qcom,sc7280-rpmhpd"; 6848 #power-domain-cells = <1>; 6849 operating-points-v2 = <&rpmhpd_opp_table>; 6850 6851 rpmhpd_opp_table: opp-table { 6852 compatible = "operating-points-v2"; 6853 6854 rpmhpd_opp_ret: opp1 { 6855 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 6856 }; 6857 6858 rpmhpd_opp_low_svs: opp2 { 6859 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 6860 }; 6861 6862 rpmhpd_opp_svs: opp3 { 6863 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 6864 }; 6865 6866 rpmhpd_opp_svs_l1: opp4 { 6867 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 6868 }; 6869 6870 rpmhpd_opp_svs_l2: opp5 { 6871 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 6872 }; 6873 6874 rpmhpd_opp_nom: opp6 { 6875 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 6876 }; 6877 6878 rpmhpd_opp_nom_l1: opp7 { 6879 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 6880 }; 6881 6882 rpmhpd_opp_turbo: opp8 { 6883 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 6884 }; 6885 6886 rpmhpd_opp_turbo_l1: opp9 { 6887 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 6888 }; 6889 }; 6890 }; 6891 6892 rpmhcc: clock-controller { 6893 compatible = "qcom,sc7280-rpmh-clk"; 6894 clocks = <&xo_board>; 6895 clock-names = "xo"; 6896 #clock-cells = <1>; 6897 }; 6898 }; 6899 6900 epss_l3: interconnect@18590000 { 6901 compatible = "qcom,sc7280-epss-l3", "qcom,epss-l3"; 6902 reg = <0 0x18590000 0 0x1000>; 6903 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 6904 clock-names = "xo", "alternate"; 6905 #interconnect-cells = <1>; 6906 }; 6907 6908 cpufreq_hw: cpufreq@18591000 { 6909 compatible = "qcom,sc7280-cpufreq-epss", "qcom,cpufreq-epss"; 6910 reg = <0 0x18591000 0 0x1000>, 6911 <0 0x18592000 0 0x1000>, 6912 <0 0x18593000 0 0x1000>; 6913 6914 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 6915 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 6916 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 6917 interrupt-names = "dcvsh-irq-0", 6918 "dcvsh-irq-1", 6919 "dcvsh-irq-2"; 6920 6921 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 6922 clock-names = "xo", "alternate"; 6923 #freq-domain-cells = <1>; 6924 #clock-cells = <1>; 6925 }; 6926 }; 6927 6928 sound: sound { 6929 }; 6930 6931 thermal_zones: thermal-zones { 6932 cpu0-thermal { 6933 polling-delay-passive = <250>; 6934 6935 thermal-sensors = <&tsens0 1>; 6936 6937 trips { 6938 cpu0_alert0: trip-point0 { 6939 temperature = <90000>; 6940 hysteresis = <2000>; 6941 type = "passive"; 6942 }; 6943 6944 cpu0_alert1: trip-point1 { 6945 temperature = <95000>; 6946 hysteresis = <2000>; 6947 type = "passive"; 6948 }; 6949 6950 cpu0_crit: cpu-crit { 6951 temperature = <110000>; 6952 hysteresis = <0>; 6953 type = "critical"; 6954 }; 6955 }; 6956 6957 cooling-maps { 6958 map0 { 6959 trip = <&cpu0_alert0>; 6960 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6961 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6962 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6963 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6964 }; 6965 map1 { 6966 trip = <&cpu0_alert1>; 6967 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6968 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6969 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6970 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6971 }; 6972 }; 6973 }; 6974 6975 cpu1-thermal { 6976 polling-delay-passive = <250>; 6977 6978 thermal-sensors = <&tsens0 2>; 6979 6980 trips { 6981 cpu1_alert0: trip-point0 { 6982 temperature = <90000>; 6983 hysteresis = <2000>; 6984 type = "passive"; 6985 }; 6986 6987 cpu1_alert1: trip-point1 { 6988 temperature = <95000>; 6989 hysteresis = <2000>; 6990 type = "passive"; 6991 }; 6992 6993 cpu1_crit: cpu-crit { 6994 temperature = <110000>; 6995 hysteresis = <0>; 6996 type = "critical"; 6997 }; 6998 }; 6999 7000 cooling-maps { 7001 map0 { 7002 trip = <&cpu1_alert0>; 7003 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7004 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7005 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7006 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7007 }; 7008 map1 { 7009 trip = <&cpu1_alert1>; 7010 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7011 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7012 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7013 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7014 }; 7015 }; 7016 }; 7017 7018 cpu2-thermal { 7019 polling-delay-passive = <250>; 7020 7021 thermal-sensors = <&tsens0 3>; 7022 7023 trips { 7024 cpu2_alert0: trip-point0 { 7025 temperature = <90000>; 7026 hysteresis = <2000>; 7027 type = "passive"; 7028 }; 7029 7030 cpu2_alert1: trip-point1 { 7031 temperature = <95000>; 7032 hysteresis = <2000>; 7033 type = "passive"; 7034 }; 7035 7036 cpu2_crit: cpu-crit { 7037 temperature = <110000>; 7038 hysteresis = <0>; 7039 type = "critical"; 7040 }; 7041 }; 7042 7043 cooling-maps { 7044 map0 { 7045 trip = <&cpu2_alert0>; 7046 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7047 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7048 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7049 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7050 }; 7051 map1 { 7052 trip = <&cpu2_alert1>; 7053 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7054 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7055 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7056 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7057 }; 7058 }; 7059 }; 7060 7061 cpu3-thermal { 7062 polling-delay-passive = <250>; 7063 7064 thermal-sensors = <&tsens0 4>; 7065 7066 trips { 7067 cpu3_alert0: trip-point0 { 7068 temperature = <90000>; 7069 hysteresis = <2000>; 7070 type = "passive"; 7071 }; 7072 7073 cpu3_alert1: trip-point1 { 7074 temperature = <95000>; 7075 hysteresis = <2000>; 7076 type = "passive"; 7077 }; 7078 7079 cpu3_crit: cpu-crit { 7080 temperature = <110000>; 7081 hysteresis = <0>; 7082 type = "critical"; 7083 }; 7084 }; 7085 7086 cooling-maps { 7087 map0 { 7088 trip = <&cpu3_alert0>; 7089 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7090 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7091 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7092 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7093 }; 7094 map1 { 7095 trip = <&cpu3_alert1>; 7096 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7097 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7098 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7099 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7100 }; 7101 }; 7102 }; 7103 7104 cpu4-thermal { 7105 polling-delay-passive = <250>; 7106 7107 thermal-sensors = <&tsens0 7>; 7108 7109 trips { 7110 cpu4_alert0: trip-point0 { 7111 temperature = <90000>; 7112 hysteresis = <2000>; 7113 type = "passive"; 7114 }; 7115 7116 cpu4_alert1: trip-point1 { 7117 temperature = <95000>; 7118 hysteresis = <2000>; 7119 type = "passive"; 7120 }; 7121 7122 cpu4_crit: cpu-crit { 7123 temperature = <110000>; 7124 hysteresis = <0>; 7125 type = "critical"; 7126 }; 7127 }; 7128 7129 cooling-maps { 7130 map0 { 7131 trip = <&cpu4_alert0>; 7132 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7133 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7134 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7135 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7136 }; 7137 map1 { 7138 trip = <&cpu4_alert1>; 7139 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7140 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7141 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7142 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7143 }; 7144 }; 7145 }; 7146 7147 cpu5-thermal { 7148 polling-delay-passive = <250>; 7149 7150 thermal-sensors = <&tsens0 8>; 7151 7152 trips { 7153 cpu5_alert0: trip-point0 { 7154 temperature = <90000>; 7155 hysteresis = <2000>; 7156 type = "passive"; 7157 }; 7158 7159 cpu5_alert1: trip-point1 { 7160 temperature = <95000>; 7161 hysteresis = <2000>; 7162 type = "passive"; 7163 }; 7164 7165 cpu5_crit: cpu-crit { 7166 temperature = <110000>; 7167 hysteresis = <0>; 7168 type = "critical"; 7169 }; 7170 }; 7171 7172 cooling-maps { 7173 map0 { 7174 trip = <&cpu5_alert0>; 7175 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7176 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7177 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7178 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7179 }; 7180 map1 { 7181 trip = <&cpu5_alert1>; 7182 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7183 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7184 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7185 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7186 }; 7187 }; 7188 }; 7189 7190 cpu6-thermal { 7191 polling-delay-passive = <250>; 7192 7193 thermal-sensors = <&tsens0 9>; 7194 7195 trips { 7196 cpu6_alert0: trip-point0 { 7197 temperature = <90000>; 7198 hysteresis = <2000>; 7199 type = "passive"; 7200 }; 7201 7202 cpu6_alert1: trip-point1 { 7203 temperature = <95000>; 7204 hysteresis = <2000>; 7205 type = "passive"; 7206 }; 7207 7208 cpu6_crit: cpu-crit { 7209 temperature = <110000>; 7210 hysteresis = <0>; 7211 type = "critical"; 7212 }; 7213 }; 7214 7215 cooling-maps { 7216 map0 { 7217 trip = <&cpu6_alert0>; 7218 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7219 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7220 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7221 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7222 }; 7223 map1 { 7224 trip = <&cpu6_alert1>; 7225 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7226 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7227 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7228 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7229 }; 7230 }; 7231 }; 7232 7233 cpu7-thermal { 7234 polling-delay-passive = <250>; 7235 7236 thermal-sensors = <&tsens0 10>; 7237 7238 trips { 7239 cpu7_alert0: trip-point0 { 7240 temperature = <90000>; 7241 hysteresis = <2000>; 7242 type = "passive"; 7243 }; 7244 7245 cpu7_alert1: trip-point1 { 7246 temperature = <95000>; 7247 hysteresis = <2000>; 7248 type = "passive"; 7249 }; 7250 7251 cpu7_crit: cpu-crit { 7252 temperature = <110000>; 7253 hysteresis = <0>; 7254 type = "critical"; 7255 }; 7256 }; 7257 7258 cooling-maps { 7259 map0 { 7260 trip = <&cpu7_alert0>; 7261 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7262 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7263 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7264 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7265 }; 7266 map1 { 7267 trip = <&cpu7_alert1>; 7268 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7269 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7270 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7271 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7272 }; 7273 }; 7274 }; 7275 7276 cpu8-thermal { 7277 polling-delay-passive = <250>; 7278 7279 thermal-sensors = <&tsens0 11>; 7280 7281 trips { 7282 cpu8_alert0: trip-point0 { 7283 temperature = <90000>; 7284 hysteresis = <2000>; 7285 type = "passive"; 7286 }; 7287 7288 cpu8_alert1: trip-point1 { 7289 temperature = <95000>; 7290 hysteresis = <2000>; 7291 type = "passive"; 7292 }; 7293 7294 cpu8_crit: cpu-crit { 7295 temperature = <110000>; 7296 hysteresis = <0>; 7297 type = "critical"; 7298 }; 7299 }; 7300 7301 cooling-maps { 7302 map0 { 7303 trip = <&cpu8_alert0>; 7304 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7305 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7306 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7307 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7308 }; 7309 map1 { 7310 trip = <&cpu8_alert1>; 7311 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7312 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7313 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7314 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7315 }; 7316 }; 7317 }; 7318 7319 cpu9-thermal { 7320 polling-delay-passive = <250>; 7321 7322 thermal-sensors = <&tsens0 12>; 7323 7324 trips { 7325 cpu9_alert0: trip-point0 { 7326 temperature = <90000>; 7327 hysteresis = <2000>; 7328 type = "passive"; 7329 }; 7330 7331 cpu9_alert1: trip-point1 { 7332 temperature = <95000>; 7333 hysteresis = <2000>; 7334 type = "passive"; 7335 }; 7336 7337 cpu9_crit: cpu-crit { 7338 temperature = <110000>; 7339 hysteresis = <0>; 7340 type = "critical"; 7341 }; 7342 }; 7343 7344 cooling-maps { 7345 map0 { 7346 trip = <&cpu9_alert0>; 7347 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7348 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7349 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7350 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7351 }; 7352 map1 { 7353 trip = <&cpu9_alert1>; 7354 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7355 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7356 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7357 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7358 }; 7359 }; 7360 }; 7361 7362 cpu10-thermal { 7363 polling-delay-passive = <250>; 7364 7365 thermal-sensors = <&tsens0 13>; 7366 7367 trips { 7368 cpu10_alert0: trip-point0 { 7369 temperature = <90000>; 7370 hysteresis = <2000>; 7371 type = "passive"; 7372 }; 7373 7374 cpu10_alert1: trip-point1 { 7375 temperature = <95000>; 7376 hysteresis = <2000>; 7377 type = "passive"; 7378 }; 7379 7380 cpu10_crit: cpu-crit { 7381 temperature = <110000>; 7382 hysteresis = <0>; 7383 type = "critical"; 7384 }; 7385 }; 7386 7387 cooling-maps { 7388 map0 { 7389 trip = <&cpu10_alert0>; 7390 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7391 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7392 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7393 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7394 }; 7395 map1 { 7396 trip = <&cpu10_alert1>; 7397 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7398 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7399 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7400 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7401 }; 7402 }; 7403 }; 7404 7405 cpu11-thermal { 7406 polling-delay-passive = <250>; 7407 7408 thermal-sensors = <&tsens0 14>; 7409 7410 trips { 7411 cpu11_alert0: trip-point0 { 7412 temperature = <90000>; 7413 hysteresis = <2000>; 7414 type = "passive"; 7415 }; 7416 7417 cpu11_alert1: trip-point1 { 7418 temperature = <95000>; 7419 hysteresis = <2000>; 7420 type = "passive"; 7421 }; 7422 7423 cpu11_crit: cpu-crit { 7424 temperature = <110000>; 7425 hysteresis = <0>; 7426 type = "critical"; 7427 }; 7428 }; 7429 7430 cooling-maps { 7431 map0 { 7432 trip = <&cpu11_alert0>; 7433 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7434 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7435 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7436 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7437 }; 7438 map1 { 7439 trip = <&cpu11_alert1>; 7440 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7441 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7442 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7443 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7444 }; 7445 }; 7446 }; 7447 7448 aoss0-thermal { 7449 polling-delay-passive = <0>; 7450 7451 thermal-sensors = <&tsens0 0>; 7452 7453 trips { 7454 aoss0_alert0: trip-point0 { 7455 temperature = <90000>; 7456 hysteresis = <2000>; 7457 type = "hot"; 7458 }; 7459 7460 aoss0_crit: aoss0-crit { 7461 temperature = <110000>; 7462 hysteresis = <0>; 7463 type = "critical"; 7464 }; 7465 }; 7466 }; 7467 7468 aoss1-thermal { 7469 polling-delay-passive = <0>; 7470 7471 thermal-sensors = <&tsens1 0>; 7472 7473 trips { 7474 aoss1_alert0: trip-point0 { 7475 temperature = <90000>; 7476 hysteresis = <2000>; 7477 type = "hot"; 7478 }; 7479 7480 aoss1_crit: aoss1-crit { 7481 temperature = <110000>; 7482 hysteresis = <0>; 7483 type = "critical"; 7484 }; 7485 }; 7486 }; 7487 7488 cpuss0-thermal { 7489 polling-delay-passive = <0>; 7490 7491 thermal-sensors = <&tsens0 5>; 7492 7493 trips { 7494 cpuss0_alert0: trip-point0 { 7495 temperature = <90000>; 7496 hysteresis = <2000>; 7497 type = "hot"; 7498 }; 7499 cpuss0_crit: cluster0-crit { 7500 temperature = <110000>; 7501 hysteresis = <0>; 7502 type = "critical"; 7503 }; 7504 }; 7505 }; 7506 7507 cpuss1-thermal { 7508 polling-delay-passive = <0>; 7509 7510 thermal-sensors = <&tsens0 6>; 7511 7512 trips { 7513 cpuss1_alert0: trip-point0 { 7514 temperature = <90000>; 7515 hysteresis = <2000>; 7516 type = "hot"; 7517 }; 7518 cpuss1_crit: cluster0-crit { 7519 temperature = <110000>; 7520 hysteresis = <0>; 7521 type = "critical"; 7522 }; 7523 }; 7524 }; 7525 7526 gpuss0-thermal { 7527 polling-delay-passive = <100>; 7528 7529 thermal-sensors = <&tsens1 1>; 7530 7531 trips { 7532 gpuss0_alert0: trip-point0 { 7533 temperature = <95000>; 7534 hysteresis = <2000>; 7535 type = "passive"; 7536 }; 7537 7538 gpuss0_crit: gpuss0-crit { 7539 temperature = <110000>; 7540 hysteresis = <0>; 7541 type = "critical"; 7542 }; 7543 }; 7544 7545 cooling-maps { 7546 map0 { 7547 trip = <&gpuss0_alert0>; 7548 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7549 }; 7550 }; 7551 }; 7552 7553 gpuss1-thermal { 7554 polling-delay-passive = <100>; 7555 7556 thermal-sensors = <&tsens1 2>; 7557 7558 trips { 7559 gpuss1_alert0: trip-point0 { 7560 temperature = <95000>; 7561 hysteresis = <2000>; 7562 type = "passive"; 7563 }; 7564 7565 gpuss1_crit: gpuss1-crit { 7566 temperature = <110000>; 7567 hysteresis = <0>; 7568 type = "critical"; 7569 }; 7570 }; 7571 7572 cooling-maps { 7573 map0 { 7574 trip = <&gpuss1_alert0>; 7575 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7576 }; 7577 }; 7578 }; 7579 7580 nspss0-thermal { 7581 thermal-sensors = <&tsens1 3>; 7582 7583 trips { 7584 nspss0_alert0: trip-point0 { 7585 temperature = <90000>; 7586 hysteresis = <2000>; 7587 type = "hot"; 7588 }; 7589 7590 nspss0_crit: nspss0-crit { 7591 temperature = <110000>; 7592 hysteresis = <0>; 7593 type = "critical"; 7594 }; 7595 }; 7596 }; 7597 7598 nspss1-thermal { 7599 thermal-sensors = <&tsens1 4>; 7600 7601 trips { 7602 nspss1_alert0: trip-point0 { 7603 temperature = <90000>; 7604 hysteresis = <2000>; 7605 type = "hot"; 7606 }; 7607 7608 nspss1_crit: nspss1-crit { 7609 temperature = <110000>; 7610 hysteresis = <0>; 7611 type = "critical"; 7612 }; 7613 }; 7614 }; 7615 7616 video-thermal { 7617 thermal-sensors = <&tsens1 5>; 7618 7619 trips { 7620 video_alert0: trip-point0 { 7621 temperature = <90000>; 7622 hysteresis = <2000>; 7623 type = "hot"; 7624 }; 7625 7626 video_crit: video-crit { 7627 temperature = <110000>; 7628 hysteresis = <0>; 7629 type = "critical"; 7630 }; 7631 }; 7632 }; 7633 7634 ddr-thermal { 7635 thermal-sensors = <&tsens1 6>; 7636 7637 trips { 7638 ddr_alert0: trip-point0 { 7639 temperature = <90000>; 7640 hysteresis = <2000>; 7641 type = "hot"; 7642 }; 7643 7644 ddr_crit: ddr-crit { 7645 temperature = <110000>; 7646 hysteresis = <0>; 7647 type = "critical"; 7648 }; 7649 }; 7650 }; 7651 7652 mdmss0-thermal { 7653 thermal-sensors = <&tsens1 7>; 7654 7655 trips { 7656 mdmss0_alert0: trip-point0 { 7657 temperature = <90000>; 7658 hysteresis = <2000>; 7659 type = "hot"; 7660 }; 7661 7662 mdmss0_crit: mdmss0-crit { 7663 temperature = <110000>; 7664 hysteresis = <0>; 7665 type = "critical"; 7666 }; 7667 }; 7668 }; 7669 7670 mdmss1-thermal { 7671 thermal-sensors = <&tsens1 8>; 7672 7673 trips { 7674 mdmss1_alert0: trip-point0 { 7675 temperature = <90000>; 7676 hysteresis = <2000>; 7677 type = "hot"; 7678 }; 7679 7680 mdmss1_crit: mdmss1-crit { 7681 temperature = <110000>; 7682 hysteresis = <0>; 7683 type = "critical"; 7684 }; 7685 }; 7686 }; 7687 7688 mdmss2-thermal { 7689 thermal-sensors = <&tsens1 9>; 7690 7691 trips { 7692 mdmss2_alert0: trip-point0 { 7693 temperature = <90000>; 7694 hysteresis = <2000>; 7695 type = "hot"; 7696 }; 7697 7698 mdmss2_crit: mdmss2-crit { 7699 temperature = <110000>; 7700 hysteresis = <0>; 7701 type = "critical"; 7702 }; 7703 }; 7704 }; 7705 7706 mdmss3-thermal { 7707 thermal-sensors = <&tsens1 10>; 7708 7709 trips { 7710 mdmss3_alert0: trip-point0 { 7711 temperature = <90000>; 7712 hysteresis = <2000>; 7713 type = "hot"; 7714 }; 7715 7716 mdmss3_crit: mdmss3-crit { 7717 temperature = <110000>; 7718 hysteresis = <0>; 7719 type = "critical"; 7720 }; 7721 }; 7722 }; 7723 7724 camera0-thermal { 7725 thermal-sensors = <&tsens1 11>; 7726 7727 trips { 7728 camera0_alert0: trip-point0 { 7729 temperature = <90000>; 7730 hysteresis = <2000>; 7731 type = "hot"; 7732 }; 7733 7734 camera0_crit: camera0-crit { 7735 temperature = <110000>; 7736 hysteresis = <0>; 7737 type = "critical"; 7738 }; 7739 }; 7740 }; 7741 }; 7742 7743 timer { 7744 compatible = "arm,armv8-timer"; 7745 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 7746 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 7747 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 7748 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 7749 }; 7750}; 7751