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/freebsd/sys/contrib/device-tree/Bindings/iommu/
H A Darm,smmu.yaml4 $id: http://devicetree.org/schemas/iommu/arm,smmu.yaml#
18 The SMMU may also raise interrupts in response to various fault
26 - description: Qcom SoCs implementing "arm,smmu-v2"
29 - qcom,msm8996-smmu-v2
30 - qcom,msm8998-smmu-v2
31 - qcom,sdm630-smmu-v2
32 - qcom,sm6375-smmu-v2
33 - const: qcom,smmu-v2
35 - description: Qcom SoCs implementing "qcom,smmu-500" and "arm,mmu-500"
38 - qcom,milos-smmu-500
[all …]
H A Darm,smmu-v3.yaml4 $id: http://devicetree.org/schemas/iommu/arm,smmu-v3.yaml#
23 const: arm,smmu-v3
53 Present if page table walks made by the SMMU are cache coherent with the
56 NOTE: this only applies to the SMMU itself, not masters connected
57 upstream of the SMMU.
63 description: Avoid sending CMD_PREFETCH_* commands to the SMMU.
70 doesn't support SMMU page1 register space.
85 compatible = "arm,smmu-v3";
H A Dnvidia,tegra30-smmu.txt1 NVIDIA Tegra 30 IOMMU H/W, SMMU (System Memory Management Unit)
4 - compatible : "nvidia,tegra30-smmu"
6 of the SMMU register blocks.
10 - nvidia,ahb : phandle to the ahb bus connected to SMMU.
13 smmu {
14 compatible = "nvidia,tegra30-smmu";
H A Dqcom,tbu.yaml38 Phandle of a SMMU device and Stream ID range (address and size) that
43 - description: phandle of a smmu node
/freebsd/sys/contrib/device-tree/src/arm64/marvell/
H A Darmada-8040.dtsi14 <0x0 &smmu 0x480 0x20>,
15 <0x100 &smmu 0x4a0 0x20>,
16 <0x200 &smmu 0x4c0 0x20>;
30 iommus = <&smmu 0x444>;
34 iommus = <&smmu 0x445>;
38 iommus = <&smmu 0x440>;
42 iommus = <&smmu 0x441>;
46 iommus = <&smmu 0x454>;
50 iommus = <&smmu 0x450>;
54 iommus = <&smmu 0x451>;
H A Darmada-7040.dtsi14 <0x0 &smmu 0x480 0x20>,
15 <0x100 &smmu 0x4a0 0x20>,
16 <0x200 &smmu 0x4c0 0x20>;
21 iommus = <&smmu 0x444>;
25 iommus = <&smmu 0x445>;
29 iommus = <&smmu 0x440>;
33 iommus = <&smmu 0x441>;
H A Dcn9130-crb-A.dts22 <0x0 &smmu 0x480 0x20>,
23 <0x100 &smmu 0x4a0 0x20>,
24 <0x200 &smmu 0x4c0 0x20>;
H A Dcn9130-crb-B.dts19 <0x0 &smmu 0x480 0x20>,
20 <0x100 &smmu 0x4a0 0x20>,
21 <0x200 &smmu 0x4c0 0x20>;
/freebsd/sys/arm64/iommu/
H A Dsmmu_acpi.c67 ACPI_IORT_SMMU_V3 *smmu[MAX_SMMU]; member
88 if (iort_data->smmu[i] != NULL) { in iort_handler()
91 "smmu: Already have an SMMU table"); in iort_handler()
95 iort_data->smmu[i] = (ACPI_IORT_SMMU_V3 *)node->NodeData; in iort_handler()
119 device_printf(parent, "smmu: Unable to map the IORT\n"); in smmu_acpi_identify()
125 iort_data.smmu[i] = NULL; in smmu_acpi_identify()
131 device_printf(parent, "No SMMU found.\n"); in smmu_acpi_identify()
137 BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE, "smmu", -1); in smmu_acpi_identify()
139 device_printf(parent, "add smmu child failed\n"); in smmu_acpi_identify()
145 iort_data.smmu[i]->EventGsiv, 1); in smmu_acpi_identify()
[all …]
H A Dsmmu_fdt.c58 { "arm,smmu-v3", 1 },
71 device_set_desc(dev, "ARM System MMU (SMMU) v3"); in smmu_fdt_probe()
121 * by the SMMU driver. This IRQ line may or may not be provided by in smmu_fdt_attach()
172 device_printf(dev, "Failed to register SMMU.\n"); in smmu_fdt_attach()
199 DEFINE_CLASS_1(smmu, smmu_fdt_driver, smmu_fdt_methods,
202 EARLY_DRIVER_MODULE(smmu, simplebus, smmu_fdt_driver, 0, 0,
H A Dsmmu.c58 * Note that SMMU does not share TLB with a main CPU.
59 * Command queue is used by this driver to Invalidate SMMU TLB, STE cache.
61 * An arm64 SoC could have more than one SMMU instance.
62 * ACPI IORT table describes which SMMU unit is assigned for a particular
68 * to interface SMMU.
70 * These are a Command queue for commands to send to the SMMU and an Event
71 * queue for event/fault reports from the SMMU. Optionally PRI queue is
78 * All SMMU queues are arranged as circular buffers in memory. They are used
80 * produced by the SMMU and consumed by software.
81 * An input queue contains data produced by software, consumed by the SMMU.
[all …]
/freebsd/sys/contrib/device-tree/Bindings/display/
H A Darm,komeda.txt15 devicetree/bindings/iommu/arm,smmu-v3.txt,
49 iommus = <&smmu 0>, <&smmu 1>, <&smmu 2>, <&smmu 3>,
50 <&smmu 4>, <&smmu 5>, <&smmu 6>, <&smmu 7>,
51 <&smmu 8>, <&smmu 9>;
H A Darm,komeda.yaml102 iommus = <&smmu 0>, <&smmu 1>, <&smmu 2>, <&smmu 3>,
103 <&smmu 8>,
104 <&smmu 4>, <&smmu 5>, <&smmu 6>, <&smmu 7>,
105 <&smmu 9>;
/freebsd/sys/arm64/acpica/
H A Dacpi_iort.c104 ACPI_IORT_SMMU smmu; member
177 * Perform an additional lookup in case of SMMU node and ITS outtype.
186 /* Node can be SMMU or ITS. If SMMU, we need another lookup. */ in iort_smmu_trymap()
200 * Map a PCI RID to a SMMU node or an ITS node, based on outtype.
225 * Map a named component node to a SMMU node or an ITS node, based on outtype.
251 * Not implemented, map a PCIe device to the SMMU it is associated with.
254 acpi_iort_map_smmu(u_int seg, u_int devid, void **smmu, u_int *sid) in acpi_iort_map_smmu() argument
256 /* XXX: convert oref to SMMU device */ in acpi_iort_map_smmu()
324 ACPI_IORT_SMMU *smmu; in iort_add_nodes() local
343 smmu = (ACPI_IORT_SMMU *)node_entry->NodeData; in iort_add_nodes()
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dimx8qm-ss-conn.dtsi13 iommus = <&smmu 0x12 0x7f80>;
18 iommus = <&smmu 0x12 0x7f80>;
23 iommus = <&smmu 0x11 0x7f80>;
28 iommus = <&smmu 0x11 0x7f80>;
33 iommus = <&smmu 0x11 0x7f80>;
/freebsd/sys/contrib/device-tree/Bindings/perf/
H A Darm,smmu-v3-pmcg.yaml4 $id: http://devicetree.org/schemas/perf/arm,smmu-v3-pmcg.yaml#
25 - const: arm,smmu-v3-pmcg
26 - const: arm,smmu-v3-pmcg
57 compatible = "arm,smmu-v3-pmcg";
65 compatible = "arm,smmu-v3-pmcg";
/freebsd/sys/contrib/device-tree/src/arm64/xilinx/
H A Dzynqmp.dtsi586 /* iommus = <&smmu 0x14e8>; */
599 /* iommus = <&smmu 0x14e9>; */
612 /* iommus = <&smmu 0x14ea>; */
625 /* iommus = <&smmu 0x14eb>; */
638 /* iommus = <&smmu 0x14ec>; */
651 /* iommus = <&smmu 0x14ed>; */
664 /* iommus = <&smmu 0x14ee>; */
677 /* iommus = <&smmu 0x14ef>; */
722 /* iommus = <&smmu 0x868>; */
735 /* iommus = <&smmu 0x869>; */
[all …]
H A Dversal-net-vn-x-b2197-01-revA.dts79 iommus = <&smmu 0x235>;
93 iommus = <&smmu 0x245>;
100 iommus = <&smmu 0x243>;
114 &smmu {
/freebsd/sys/contrib/device-tree/src/arm64/nvidia/
H A Dtegra186.dtsi66 iommus = <&smmu TEGRA186_SID_EQOS>;
114 iommus = <&smmu TEGRA186_SID_GPCDMA_0>;
862 iommus = <&smmu TEGRA186_SID_SDMMC1>;
892 iommus = <&smmu TEGRA186_SID_SDMMC2>;
917 iommus = <&smmu TEGRA186_SID_SDMMC3>;
947 iommus = <&smmu TEGRA186_SID_SDMMC4>;
973 iommus = <&smmu TEGRA186_SID_SATA>;
1006 iommus = <&smmu TEGRA186_SID_HDA>;
1137 iommus = <&smmu TEGRA186_SID_XUSB_HOST>;
1159 iommus = <&smmu TEGRA186_SID_XUSB_DEV>;
[all …]
H A Dtegra194.dtsi159 iommus = <&smmu TEGRA194_SID_EQOS>;
208 iommus = <&smmu TEGRA194_SID_GPCDMA_0>;
592 iommus = <&smmu TEGRA194_SID_APE>;
1041 iommus = <&smmu TEGRA194_SID_SDMMC1>;
1080 iommus = <&smmu TEGRA194_SID_SDMMC3>;
1119 iommus = <&smmu TEGRA194_SID_SDMMC4>;
1155 iommus = <&smmu TEGRA194_SID_HDA>;
1281 iommus = <&smmu TEGRA194_SID_XUSB_DEV>;
1315 iommus = <&smmu TEGRA194_SID_XUSB_HOST>;
1738 compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500";
[all …]
H A Dtegra264.dtsi176 compatible = "arm,smmu-v3";
188 compatible = "arm,smmu-v3";
252 compatible = "arm,smmu-v3";
264 compatible = "arm,smmu-v3";
310 compatible = "arm,smmu-v3";
/freebsd/sys/contrib/device-tree/Bindings/misc/
H A Dfsl,qoriq-mc.txt28 For arm-smmu binding, see:
29 Documentation/devicetree/bindings/iommu/arm,smmu.yaml.
151 smmu: iommu@5000000 {
173 iommu-map = <23 &smmu 23 41>;
H A Dfsl,qoriq-mc.yaml38 For arm-smmu binding, see:
39 Documentation/devicetree/bindings/iommu/arm,smmu.yaml.
171 iommu-map = <23 &smmu 23 41>;
/freebsd/sys/contrib/device-tree/src/arm64/altera/
H A Dsocfpga_stratix10.dtsi187 iommus = <&smmu 1>;
205 iommus = <&smmu 2>;
223 iommus = <&smmu 3>;
335 iommus = <&smmu 5>;
405 smmu: iommu@fa000000 { label
406 compatible = "arm,mmu-500", "arm,smmu-v2";
525 iommus = <&smmu 6>;
539 iommus = <&smmu 7>;
/freebsd/sys/contrib/device-tree/src/arm64/intel/
H A Dsocfpga_agilex.dtsi183 iommus = <&smmu 1>;
201 iommus = <&smmu 2>;
219 iommus = <&smmu 3>;
333 iommus = <&smmu 5>;
402 smmu: iommu@fa000000 { label
403 compatible = "arm,mmu-500", "arm,smmu-v2";
553 iommus = <&smmu 6>;
565 iommus = <&smmu 7>;

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