Lines Matching full:smmu
58 * Note that SMMU does not share TLB with a main CPU.
59 * Command queue is used by this driver to Invalidate SMMU TLB, STE cache.
61 * An arm64 SoC could have more than one SMMU instance.
62 * ACPI IORT table describes which SMMU unit is assigned for a particular
68 * to interface SMMU.
70 * These are a Command queue for commands to send to the SMMU and an Event
71 * queue for event/fault reports from the SMMU. Optionally PRI queue is
78 * All SMMU queues are arranged as circular buffers in memory. They are used
80 * produced by the SMMU and consumed by software.
81 * An input queue contains data produced by software, consumed by the SMMU.
87 * the SMMU, which is only in a case of errors (e.g. translation fault).
161 MALLOC_DEFINE(M_SMMU, "SMMU", SMMU_DEVSTR);
188 "SMMU bypass is disallowed for this StreamID."},
1063 /* Disable SMMU */ in smmu_disable()
1068 device_printf(sc->dev, "Could not disable SMMU.\n"); in smmu_disable()
1108 device_printf(sc->dev, "SMMU Global Error\n"); in smmu_gerr_intr()
1183 * Configure SMMU interrupts as EDGE triggered manually in smmu_setup_interrupts()
1221 "%s: Warning: SMMU is enabled\n", __func__); in smmu_reset()
1226 "%s: Could not disable SMMU.\n", __func__); in smmu_reset()
1310 device_printf(sc->dev, "Could not enable SMMU.\n"); in smmu_reset()
1560 mtx_init(&sc->sc_mtx, device_get_nameunit(sc->dev), "smmu", MTX_DEF); in smmu_attach()
1591 device_printf(dev, "Couldn't reset SMMU.\n"); in smmu_attach()
1986 /* SMMU interface */
2007 DEFINE_CLASS_0(smmu, smmu_driver, smmu_methods, sizeof(struct smmu_softc));