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/freebsd/sys/contrib/device-tree/Bindings/mtd/partitions/
H A Dqcom,smem-part.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/partitions/qcom,smem-part.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SMEM NAND flash partition parser
10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
14 Memory (SMEM) based partition table scheme. The maximum partitions supported
22 const: qcom,smem-part
25 "^partition-[0-9a-z]+$":
26 $ref: nvmem-cells.yaml
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H A Dpartitions.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
14 - Miquel Raynal <miquel.raynal@bootlin.com>
17 - $ref: arm,arm-firmware-suite.yaml
18 - $ref: brcm,bcm4908-partitions.yaml
19 - $ref: brcm,bcm947xx-cfe-partitions.yaml
20 - $ref: fixed-partitions.yaml
21 - $ref: linksys,ns-partitions.yaml
22 - $ref: qcom,smem-part.yaml
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/freebsd/sys/contrib/device-tree/Bindings/net/
H A Dqcom,ipa.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alex Elder <elder@kernel.org>
20 The GSI is an integral part of the IPA, but it is logically isolated
21 and has a distinct interrupt and a separately-defined address space.
28 - |
29 -------- ---------
31 | AP +<---. .----+ Modem |
32 | +--. | | .->+ |
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DGCNHazardRecognizer.h1 //===-- GCNHazardRecognizers.h - GCN Hazard Recognizers ---------*- C++ -*-===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
81 int checkSoftClauseHazards(MachineInstr *SMEM);
117 /// line option '-amdgpu-mfma-padding-ratio'.
119 /// For example, with '-amdgpu-mfma-padding-ratio=100':
126 ///-->
H A DSIFormMemoryClauses.cpp1 //===-- SIFormMemoryClauses.cpp -------------------------------------------===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
10 /// sequences of adjacent SMEM and VMEM instructions if XNACK is enabled. A
13 /// implicit-def early-clobber operands throughout the soft clause.
15 //===----------------------------------------------------------------------===//
24 #define DEBUG_TYPE "si-form-memory-clauses"
29 MaxClause("amdgpu-max-memory-clause", cl::Hidden, cl::init(15),
106 // thus there is nothing to set early-clobber.
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H A DGCNHazardRecognizer.cpp1 //===-- GCNHazardRecognizers.cpp - GCN Hazard Recognizer Impls ------------===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
43 MFMAPaddingRatio("amdgpu-mfma-padding-ratio", cl::init(0), cl::Hidden,
47 //===----------------------------------------------------------------------===//
49 //===----------------------------------------------------------------------===//
73 EmitInstruction(SU->getInstr()); in EmitInstruction()
179 const MachineOperand *RegOp = TII->getNamedOperand(RegInstr, in getHWReg()
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H A DSIInstrFormats.td1 //===-- SIInstrFormats.td - SI Instruction Encodings ----------------------===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
16 // Low bits - basic encoding information.
58 // High bits - other information.
73 // SMEM instructions like the cache flush ones.
114 // Must be 0 for non-FLAT instructions.
134 // Must be 0 for non-FLAT instructions.
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H A DSMInstructions.td1 //===---- SMInstructions.td - Scalar Memory Instruction Definitions -------===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
22 //===----------------------------------------------------------------------===//
24 //===----------------------------------------------------------------------===//
169 // The constrained multi-dword load equivalents with early clobber flag at
252 //===----------------------------------------------------------------------===//
254 //===----------------------------------------------------------------------===//
308 //===----------------------------------------------------------------------===//
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H A DSIInsertWaitcnts.cpp1 //===- SIInsertWaitcnts.cpp - Insert Wait Instructions --------------------===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
17 /// finely-grained approach that keeps one timeline per event type could
19 /// example, when both SMEM and LDS are in flight and we need to wait for
20 /// the i-th-last LDS instruction, then an lgkmcnt(i) is actually sufficient,
24 //===----------------------------------------------------------------------===//
42 #define DEBUG_TYPE "si-insert-waitcnts"
44 DEBUG_COUNTER(ForceExpCounter, DEBUG_TYPE"-forceexp",
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H A DAMDGPU.td1 //===-- AMDGPU.td - AMDGPU Tablegen files --------*- tablegen -*-===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===------------------------------------------------------------===//
22 //===------------------------------------------------------------===//
24 //===------------------------------------------------------------===//
26 def FeatureFastFMAF32 : SubtargetFeature<"fast-fmaf",
32 def FeatureFastDenormalF32 : SubtargetFeature<"fast-denormal-f32",
38 def FeatureMIMG_R128 : SubtargetFeature<"mimg-r128",
41 "Support 128-bit texture resources"
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H A DSILoadStoreOptimizer.cpp1 //===- SILoadStoreOptimizer.cpp -------------------------------------------===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
16 // The same is done for certain SMEM and VMEM opcodes, e.g.:
45 // - This is currently missing stores of constants because loading
49 // - Live interval recomputing seems inefficient. This currently only matches
53 // - With a list of instructions to process, we can also merge more. If a
54 // cluster of loads have offsets that are too large to fit in the 8-bit
58 //===----------------------------------------------------------------------===//
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H A DSIInstrInfo.td1 //===-- SIInstrInfo.td -----------------------------------------------------===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 def isWave32 : Predicate<"Subtarget->getWavefrontSize() == 32">,
11 def isWave64 : Predicate<"Subtarget->getWavefrontSize() == 64">,
21 int NONE = -1;
36 //===----------------------------------------------------------------------===//
38 //===----------------------------------------------------------------------===//
51 //===----------------------------------------------------------------------===//
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H A DAMDGPUISelDAGToDAG.cpp1 //===-- AMDGPUISelDAGToDAG.cpp - A dag to dag inst selector for AMDGPU ----===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //==-----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
39 #define DEBUG_TYPE "amdgpu-isel"
43 //===----------------------------------------------------------------------===//
45 //===----------------------------------------------------------------------===//
52 // Figure out if this is really an extract of the high 16-bits of a dword.
58 if (!Idx->isOne()) in isExtractHiElt()
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H A DSIInstructions.td1 //===-- SIInstructions.td - SI Instruction Definitions --------------------===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
8 // This file was originally auto-generated from a GPU register header file and
11 //===----------------------------------------------------------------------===//
18 [{ return !N->isDivergent(); }]>;
23 [{ return N->isDivergent(); }]>;
34 //===----------------------------------------------------------------------===//
36 //===----------------------------------------------------------------------===//
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H A DAMDGPUInstructionSelector.cpp1 //===- AMDGPUInstructionSelector.cpp ----------------------------*- C++ -*-==//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
32 #define DEBUG_TYPE "amdgpu-isel"
66 Subtarget->checkSubtargetFeatures(MF.getFunction()); in setupMF()
72 return Def->getOpcode() == AMDGPU::G_AMDGPU_WAVE_ADDRESS in getWaveAddress()
73 ? Def->getOperand(1).getReg() in getWaveAddress()
91 return MRI.getVRegDef(Reg)->getOpcode() != AMDGPU::G_TRUNC && in isVCC()
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H A DSIISelLowering.cpp1 //===-- SIISelLowering.cpp - SI DAG Lowering Implementation ---------------===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
49 #define DEBUG_TYPE "si-lower"
54 "amdgpu-disable-loop-alignment",
59 "amdgpu-use-divergent-register-indexing",
66 return Info->getMode().FP32Denormals == DenormalMode::getPreserveSign(); in denormalModeIsFlushAllF32()
71 return Info->getMode().FP64FP16Denormals == DenormalMode::getPreserveSign(); in denormalModeIsFlushAllF64F16()
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/freebsd/sys/contrib/dev/iwlwifi/fw/
H A Dfile.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * Copyright (C) 2008-2014, 2018-2024 Intel Corporation
4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2016-2017 Intel Deutschland GmbH
55 IWL_UCODE_TLV_PAN = 7, /* deprecated -
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/freebsd/sys/contrib/device-tree/src/arm64/qcom/
H A Dsm8450.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,gcc-sm8450.h>
8 #include <dt-bindings/clock/qcom,rpmh.h>
9 #include <dt-bindings/clock/qcom,sm8450-camcc.h>
10 #include <dt-bindings/clock/qcom,sm8450-dispcc.h>
11 #include <dt-bindings/clock/qcom,sm8450-gpucc.h>
12 #include <dt-bindings/clock/qcom,sm8450-videocc.h>
13 #include <dt-bindings/dma/qcom-gpi.h>
14 #include <dt-bindings/firmware/qcom,scm.h>
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H A Dsm8550.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,rpmh.h>
7 #include <dt-bindings/clock/qcom,sm8450-videocc.h>
8 #include <dt-bindings/clock/qcom,sm8550-camcc.h>
9 #include <dt-bindings/clock/qcom,sm8550-gcc.h>
10 #include <dt-bindings/clock/qcom,sm8550-gpucc.h>
11 #include <dt-bindings/clock/qcom,sm8550-tcsr.h>
12 #include <dt-bindings/clock/qcom,sm8550-dispcc.h>
13 #include <dt-bindings/dma/qcom-gpi.h>
14 #include <dt-bindings/firmware/qcom,scm.h>
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H A Dsm8650.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,rpmh.h>
7 #include <dt-bindings/clock/qcom,sm8650-camcc.h>
8 #include <dt-bindings/clock/qcom,sm8650-dispcc.h>
9 #include <dt-bindings/clock/qcom,sm8650-gcc.h>
10 #include <dt-bindings/clock/qcom,sm8650-gpucc.h>
11 #include <dt-bindings/clock/qcom,sm8650-tcsr.h>
12 #include <dt-bindings/clock/qcom,sm8650-videocc.h>
13 #include <dt-bindings/dma/qcom-gpi.h>
14 #include <dt-bindings/firmware/qcom,scm.h>
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/freebsd/sys/contrib/dev/iwlwifi/
H A Diwl-config.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * Copyright (C) 2005-2014, 2018-2021 Intel Corporation
4 * Copyright (C) 2016-2017 Intel Deutschland GmbH
5 * Copyright (C) 2018-2024 Intel Corporation
15 #include "iwl-cs
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/freebsd/contrib/llvm-project/llvm/include/llvm/Frontend/OpenMP/
H A DOMPIRBuilder.h1 //===- IR/OpenMPIRBuilder.h - OpenMP encoding builder for LLVM IR - C++ -*-===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
55 /// llvm::SplitBasicBlock and BasicBlock::splitBasicBlock require a well-formed
81 /// Captures attributes that affect generating LLVM-IR using the
90 /// is set when the -fopenmp-is-target-device compiler frontend option is
98 /// if `IsGPU` is true. This restriction might be lifted if an accelerator-
316 return Info->getKind() == OffloadingEntryInfoTargetRegion; in classof()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/Utils/
H A DAMDGPUBaseInfo.cpp1 //===- AMDGPUBaseInfo.cpp - AMDGPU Base encoding information --------------===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
37 "amdhsa-code-object-version", llvm::cl::Hidden,
46 return ((1 << Width) - 1) << Shift; in getBitMask()
176 return (unsigned)Ver->getZExtValue() / 100; in getAMDHSACodeObjectVersion()
278 return Info ? Info->Opcode : -1; in getMIMGOpcode()
283 return Info ? getMIMGBaseOpcodeInfo(Info->BaseOpcode) : nullptr; in getMIMGBaseOpcode()
289 getMIMGOpcodeHelper(OrigInfo->BaseOpcode, OrigInfo->MIMGEncoding, in getMaskedMIMGOp()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/
H A DAMDGPUAsmParser.cpp1 //===- AMDGPUAsmParser.cpp - Parse SI asm to MCInst instructions ----------===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
55 //===----------------------------------------------------------------------===//
57 //===----------------------------------------------------------------------===//
180 // ignore mandatory literals because they are part of the instruction and
464 // TODO: Find out how SALU supports extension of 32-bit literals to 64 bits. in isSSrc_b64()
1066 // clang-format off in printImmTy()
1130 // clang-format on in printImmTy()
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/freebsd/contrib/sqlite3/
H A Dsqlite3.c17 ** language. The code for the "sqlite3" command-line shell is also in a
20 ** The content in this amalgamation comes from Fossil check-in
51 ** NO_TEST - The branches on this line are not
56 ** OPTIMIZATION-IF-TRUE - This branch is allowed to always be false
60 ** OPTIMIZATION-IF-FALSE - This branch is allowed to always be true
64 ** PREVENTS-HARMLESS-OVERREAD - This branch prevents a buffer overread
69 ** slash-asterisk...asterisk-slash comment marks, with no spaces between the
144 ** 2015-03-02
182 ** large file support, or if the OS is windows, these should be no-ops.
188 ** Large file support can be disabled using the -DSQLITE_DISABLE_LFS switch
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