Lines Matching +full:smem +full:- +full:part
1 //===---- SMInstructions.td - Scalar Memory Instruction Definitions -------===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
22 //===----------------------------------------------------------------------===//
24 //===----------------------------------------------------------------------===//
169 // The constrained multi-dword load equivalents with early clobber flag at
252 //===----------------------------------------------------------------------===//
254 //===----------------------------------------------------------------------===//
308 //===----------------------------------------------------------------------===//
310 //===----------------------------------------------------------------------===//
312 // We are using the SReg_32_XM0 and not the SReg_32 register class for 32-bit
316 // XXX - SMEM instructions do not allow exec for data operand, but
333 // SI/CI, bit disallowed for SMEM on VI.
474 //===----------------------------------------------------------------------===//
476 //===----------------------------------------------------------------------===//
478 //===----------------------------------------------------------------------===//
480 //===----------------------------------------------------------------------===//
490 let Inst{7-0} = !if(ps.has_offset, offset{7-0}, !if(ps.has_soffset, soffset, ?));
492 let Inst{14-9} = !if(ps.has_sbase, sbase{6-1}, ?);
493 let Inst{21-15} = !if(ps.has_sdst, sdst{6-0}, ?);
494 let Inst{26-22} = op;
495 let Inst{31-27} = 0x18; //encoding
524 //===----------------------------------------------------------------------===//
526 //===----------------------------------------------------------------------===//
536 let Inst{5-0} = !if(ps.has_sbase, sbase{6-1}, ?);
537 let Inst{12-6} = !if(ps.has_sdst, sdst{6-0}, ?);
541 // meaning GFX9 is not perfectly backward-compatible with GFX8, despite
555 let Inst{25-18} = op;
556 let Inst{31-26} = 0x30; //encoding
558 // VI supports 20-bit unsigned offsets while GFX9+ supports 21-bit signed.
560 // TODO: Forbid non-M0 register offsets for GFX8 stores and atomics.
562 let Offset{6-0} = !if(ps.has_offset, offset{6-0},
563 !if(ps.has_soffset, soffset{6-0}, ?));
564 let Offset{20-7} = !if(ps.has_offset, offset{20-7}, ?);
565 let Inst{52-32} = Offset;
568 let Inst{63-57} = !if(!and(IsGFX9SpecificEncoding, ps.has_soffset),
569 soffset{6-0}, ?);
601 let Inst{12-6} = !if(ps.has_sdst, sdata{6-0}, ?);
667 //===----------------------------------------------------------------------===//
669 //===----------------------------------------------------------------------===//
680 let Inst{12-6} = !if(ps.glc, sdst{6-0}, sdata{6-0});
772 //===----------------------------------------------------------------------===//
774 //===----------------------------------------------------------------------===//
786 let Inst{7-0} = 0xff;
788 let Inst{14-9} = sbase{6-1};
789 let Inst{21-15} = sdst{6-0};
790 let Inst{26-22} = op;
791 let Inst{31-27} = 0x18; //encoding
792 let Inst{63-32} = offset{31-0};
814 let Inst{7-0} = !if(ps.has_offset, offset{7-0}, !if(ps.has_soffset, soffset, ?));
816 let Inst{14-9} = !if(ps.has_sbase, sbase{6-1}, ?);
817 let Inst{21-15} = !if(ps.has_sdst, sdst{6-0}, ?);
818 let Inst{26-22} = op;
819 let Inst{31-27} = 0x18; //encoding
824 //===----------------------------------------------------------------------===//
826 //===----------------------------------------------------------------------===//
855 [{ return !N->getOperand(1)->isDivergent();}]> {
870 // Returns true if it is a single dword load or naturally aligned multi-dword load.
872 unsigned Size = Ld->getMemoryVT().getStoreSize();
873 return Size <= 4 || Ld->getAlign().value() >= Size;
891 // 2. 32-bit IMM offset on CI
947 // 2. 32-bit IMM offset on CI
968 // 4. Offset as an 32-bit SGPR + immediate
1017 // 2. Offset as an 32-bit SGPR
1024 // 3. Offset as an 32-bit SGPR + immediate
1102 (S_GETREG_B32 getHwRegImm<HWREG.SHADER_CYCLES, 0, -12>.ret), sub0,
1151 //===----------------------------------------------------------------------===//
1153 //===----------------------------------------------------------------------===//
1158 let Inst{5-0} = !if(ps.has_sbase, sbase{6-1}, ?);
1159 let Inst{12-6} = !if(ps.has_sdst, sdst{6-0}, ?);
1160 let Inst{25-18} = op;
1161 let Inst{31-26} = 0x3d;
1162 // There are SMEM instructions that do not employ any of the offset
1164 let Inst{52-32} = !if(ps.has_offset, offset{20-0}, !if(ps.has_soffset, 0, ?));
1165 let Inst{63-57} = !if(ps.has_soffset, soffset{6-0},
1166 !if(ps.has_offset, sgpr_null.HWEncoding{6-0}, ?));
1192 let Inst{12-6} = !if(ps.has_sdst, sdata{6-0}, ?);
1263 let Inst{12-6} = !if(ps.glc, sdst{6-0}, sdata{6-0});
1351 //===----------------------------------------------------------------------===//
1353 //===----------------------------------------------------------------------===//
1397 let Inst{12-6} = !if(ps.has_sdst, sdata{6-0}, ?);
1411 //===----------------------------------------------------------------------===//
1413 //===----------------------------------------------------------------------===//
1419 let Inst{18-13} = op;
1420 let Inst{31-26} = 0x3d;
1422 let Inst{55-32} = !if(ps.has_offset, offset{23-0}, !if(ps.has_soffset, 0, ?));
1423 let Inst{63-57} = !if(ps.has_soffset, soffset{6-0},
1424 !if(ps.has_offset, sgpr_null.HWEncoding{6-0}, ?));
1433 let Inst{5-0} = !if(ps.has_sbase, sbase{6-1}, ?);
1434 let Inst{12-6} = !if(ps.has_sdst, sdst{6-0}, ?);
1442 let Inst{12-11} = 0; // Unused sdata bits.
1443 let Inst{10-6} = !if(ps.has_sdst, sdata{4-0}, ?);
1451 let Inst{22-21} = cpol{4-3}; // scope
1452 let Inst{24-23} = cpol{1-0}; // th - only lower 2 bits are supported