slew\-rate (full) in projects: linux - OpenGrok search results

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Searched +full:slew +full:- +full:rate (Results 1 – 12 of 12) sorted by relevance

/illumos-gate/usr/src/lib/libjedec/common/
H A D	spd_ddr5.h	21 * Standard JESD400-5A.01 DDR5 Serial Presence Detect (SPD) Contents. Release 27 * o Base Configuration and DRAM parameters (0x00-0x7f) 28 * o Common Module Parameters (0xc0-0xef) 29 * o Standard Module Parameters (0xf0-0x1bf) which vary on whether something 31 * o A CRC check for the first 510 bytes (0x1fe-0x1ff) 32 * o Manufacturing Information (0x200-0x27f) 33 * o Optional end-user programmable regions (0x280-0x3ff) 407 * SPD_DDR5_SPD_REV, but covers all of the module-specific information, which 408 * includes both the common area and type-specific areas. 415 * JEDS316-5. [all …]
H A D	libjedec.h	23 * o JEDEC JEP-106 vendor data 25 * (JESD402-1) 47 * JEDEC operating temperature ranges. These are defined in JESD402-1B 127 * parse the overall SPD data structure. These represent a top-level failure and 162 * categories. Fatal errors set a value in the spd_error_t below. Non-fatal 166 * The keys are all dot delineated to create a few different top-level 169 * "meta" -- Which includes information about the SPD, encoding, and things like 172 * "dram" -- Parameters that are specific to the SDRAM dies present. What one 177 * "channel" -- Parameters that are tied to an implementation of a channel. DDR4 179 * sub-channels. [all …]
/illumos-gate/usr/src/uts/common/dtrace/
H A D	profile.c	62 * optimizes away tail-calls -- so the following frames are optimized away: 68 * frame cannot be tail-call eliminated, yielding four frames in this case. 71 * provider should ideally figure this out on-the-fly by hitting one of its own 92 #define PROF_PREFIX_PROFILE "profile-" 93 #define PROF_PREFIX_TICK "tick-" 128 * system resources by creating a slew of profile probes). At mod load time, 129 * this gets its value from PROFILE_MAX_DEFAULT or profile-max-probes if it's 140 profile_probe_t *prof = pcpu->profc_probe; in profile_fire() 143 late = dtrace_gethrtime() - pcpu->profc_expected; in profile_fire() 144 pcpu->profc_expected += pcpu->profc_interval; in profile_fire() [all …]
/illumos-gate/usr/src/uts/common/sys/
H A D	timex.h	18 * Copyright 1996-1997, 2002 Sun Microsystems, Inc. All rights reserved. 36 * phase-lock loop (PLL) model used in the kernel implementation. These 62 * possible without overflow of a 32-bit word. 65 * which serves as a an extension to the low-order bits of the system 100 * oscillator plus the maximum slew rate allowed by the protocol. It 119 * The following defines are used only if a pulse-per-second (PPS) 122 * asynch driver. They establish the design parameters of the frequency- 165 #define STA_FLL 0x0008 /* select frequency-lock mode (rw) / 180 STA_PPSERROR \| STA_CLOCKERR) / read-only bits / 193 NTP user interface (ntp_gettime()) - used to read kernel clock values [all …]
/illumos-gate/usr/src/common/acpica/utilities/
H A D	utresdecode.c	3 * Module Name: utresdecode - Resource descriptor keyword strings 11 * Some or all of this work - Copyright (c) 1999 - 2018, Intel Corp. 28 * 2.3. Intel grants Licensee a non-exclusive and non-transferable patent 104 * re-exports any such software from a foreign destination, Licensee shall 105 * ensure that the distribution and export/re-export of the software is in 108 * any of its subsidiaries will export/re-export any technical data, process, 130 * 3. Neither the names of the above-listed copyright holders nor the names 177 "0 - Good Configuration", 178 "1 - Acceptable Configuration", 179 "2 - Suboptimal Configuration", [all …]
/illumos-gate/usr/src/uts/common/io/hxge/
H A D	hxge_peu_hw.h	230 * Master Data Parity Error - set if all the following conditions 234 * Fast Back-to-Back Capable (N/A in PCIE) 236 * Capabilities List - presence of extended capability item. 239 * Fast Back-to-Back Enable (N/A in PCIE) 244 * The device can issue Memory Write-and-Invalidate commands (N/A 346 * Multi-Function Device: dbi writeable 374 * Description: PIO BAR0 - For Hydra PIO space PIO BAR1 & PIO BAR0 432 * Description: MSIX BAR0 - For MSI-X Tables and PBA MSIX BAR1 & MSIX 489 * Description: Virtualization BAR0 - Previously for Hydra 566 * Subsystem ID as assigned by PCI-SIG : dbi writeable [all …]
/illumos-gate/usr/src/uts/common/io/qede/579xx/hsi/hw/
H A D	reg_addr_bb.h	9 * or http://opensource.org/licenses/CDDL-1.0. 23 * Copyright 2014-2017 Cavium, Inc. 30 * at http://opensource.org/licenses/CDDL-1.0 84 …- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl… 85 … DataWidth:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW hea… 86 …s:R DataWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header syn… 87 …ataWidth:0x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW hea… 89 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of … 91 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… 99 …l has_io_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… [all …]
H A D	reg_addr_k2.h	9 * or http://opensource.org/licenses/CDDL-1.0. 23 * Copyright 2014-2017 Cavium, Inc. 30 * at http://opensource.org/licenses/CDDL-1.0 84 …- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl… 85 … DataWidth:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW hea… 86 …s:R DataWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header syn… 87 …ataWidth:0x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW hea… 89 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of … 91 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… 99 …l has_io_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… [all …]
H A D	reg_addr_e5.h	9 * or http://opensource.org/licenses/CDDL-1.0. 23 * Copyright 2014-2017 Cavium, Inc. 30 * at http://opensource.org/licenses/CDDL-1.0 84 …- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl… 85 … DataWidth:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW hea… 86 …s:R DataWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header syn… 87 …ataWidth:0x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW hea… 89 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of … 91 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… 99 …l has_io_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… [all …]
H A D	reg_addr.h	9 * or http://opensource.org/licenses/CDDL-1.0. 23 * Copyright 2014-2017 Cavium, Inc. 30 * at http://opensource.org/licenses/CDDL-1.0 85 …- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl… 86 … DataWidth:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW hea… 87 …s:R DataWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header syn… 88 …ataWidth:0x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW hea… 90 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of … 92 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… 100 …l has_io_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… [all …]
H A D	reg_addr_ah_compile15.h	9 * or http://opensource.org/licenses/CDDL-1.0. 23 * Copyright 2014-2017 Cavium, Inc. 30 * at http://opensource.org/licenses/CDDL-1.0 85 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of … 87 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… 96 …l has_io_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… 98 … has_mem_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… 144 …_SYS_ERR (0x1<<30) // Fatal or Non-Fatal Error Message s… 148 …:0x20 This is the PCIE compliant status/command register (bits 31-16: status, bits 15-0: command)… 149 …:0x20 This is the PCIE compliant status/command register (bits 31-16: status, bits 15-0: command)… [all …]
/illumos-gate/usr/src/uts/common/io/sfxge/common/
H A D	efx_regs_mcdi.h	2 * Copyright 2008-2013 Solarflare Communications Inc. All rights reserved. 33 /* Power-on reset state / 55 / The 'doorbell' addresses are hard-wired to alert the MC when written / 58 / The rest of these are firmware-defined / 66 / Values to be written to the per-port status dword in shared 95 * \| \| \--- Response 96 * \| \------- Error 97 * \------------------------------ Resync (always set) 152 * - To complete a shared memory request if XFLAGS_EVREQ was set 153 * - As a notification (link state, i2c event), controlled [all …]