| /freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/ |
| H A D | fsl,ls-msi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/fsl,ls-msi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 This interrupt controller hardware is a second level interrupt controller that
11 is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based
12 platforms. If interrupt-parent is not provided, the default parent interrupt
15 Each PCIe node needs to have property msi-parent that points to
19 - Frank Li <Frank.Li@nxp.com>
24 - fsl,ls1012a-msi
[all …]
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| H A D | st,spear3xx-shirq.txt | 1 * SPEAr Shared IRQ layer (shirq)
3 SPEAr3xx architecture includes shared/multiplexed irqs for certain set
4 of devices. The multiplexor provides a single interrupt to parent
5 interrupt controller (VIC) on behalf of a group of devices.
13 A single node in the device tree is used to describe the shared
14 interrupt multiplexor (one node for all groups). A group in the
15 interrupt controller shares config/control registers with other groups.
16 For example, a 32-bit interrupt enable/disable config register can
17 accommodate up to 4 interrupt groups.
20 - compatible: should be, either of
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| H A D | marvell,icu.txt | 1 Marvell ICU Interrupt Controller
2 --------------------------------
4 The Marvell ICU (Interrupt Consolidation Unit) controller is
5 responsible for collecting all wired-interrupt sources in the CP and
6 communicating them to the GIC in the AP, the unit translates interrupt
13 - compatible: Should be "marvell,cp110-icu"
15 - reg: Should contain ICU registers location and length.
17 Subnodes: Each group of interrupt is declared as a subnode of the ICU,
22 - compatible: Should be one of:
23 * "marvell,cp110-icu-nsr"
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| /freebsd/sys/contrib/device-tree/Bindings/mfd/ |
| H A D | axp20x.txt | 4 axp152 (X-Powers)
5 axp202 (X-Powers)
6 axp209 (X-Powers)
7 axp221 (X-Powers)
8 axp223 (X-Powers)
9 axp803 (X-Powers)
10 axp806 (X-Powers)
11 axp809 (X-Powers)
12 axp813 (X-Powers)
20 - compatible: should be one of:
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| /freebsd/sys/contrib/device-tree/Bindings/mailbox/ |
| H A D | nvidia,tegra186-hsp.txt | 9 The features that HSP supported are shared mailboxes, shared semaphores,
13 - name : Should be hsp
14 - compatible
17 - "nvidia,tegra186-hsp"
18 - "nvidia,tegra194-hsp", "nvidia,tegra186-hsp"
19 - reg : Offset and length of the register set for the device.
20 - interrupt-names
22 Contains a list of names for the interrupts described by the interrupt
24 - "doorbell"
25 - "sharedN", where 'N' is a number from zero up to the number of
[all …]
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| H A D | nvidia,tegra186-hsp.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mailbox/nvidia,tegra186-hsp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 The features that HSP supported are shared mailboxes, shared
29 For shared mailboxes, the first cell composed of two fields:
30 - bits 15..8:
31 A bit mask of flags that further specifies the type of shared
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| H A D | arm,mhuv3.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sudeep Holla <sudeep.holla@arm.com>
11 - Cristian Marussi <cristian.marussi@arm.com>
27 - Configure the MHU
28 - Send Transfers to the Receiver
29 - Optionally receive acknowledgment of a Transfer from the Receiver
32 - Configure the MHU
33 - Receive Transfers from the Sender
[all …]
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| /freebsd/share/man/man9/ |
| H A D | locking.9 | 1 .\" Copyright (c) 2007 Julian Elischer (julian - freebsd org )
40 A thread acquires (locks) a mutex before accessing data shared with other
41 threads (including interrupt threads), and releases (unlocks) it afterwards.
61 e.g. to protect data shared
62 with interrupt filter code (see
78 Reader/writer locks allow shared access to protected data by multiple threads
80 The threads with shared access are known as
89 with shared/exclusive semantics.
92 This limitation comes from the fact that shared owners
98 .Ss Read-Mostly Locks
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| /freebsd/sys/contrib/device-tree/Bindings/dma/ |
| H A D | brcm,bcm2835-dma.txt | 11 - compatible: Should be "brcm,bcm2835-dma".
12 - reg: Should contain DMA registers location and length.
13 - interrupts: Should contain the DMA interrupts associated
15 - interrupt-names: Should contain the names of the interrupt
17 Use "dma-shared-all" for the common interrupt line
18 that is shared by all dma channels.
19 - #dma-cells: Must be <1>, the cell in the dmas property of the
21 - brcm,dma-channel-mask: Bit mask representing the channels
28 compatible = "brcm,bcm2835-dma";
41 /* dma channel 11-14 share one irq */
[all …]
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| /freebsd/sys/dev/iavf/ |
| H A D | iavf_sysctls_common.h | 1 /* SPDX-License-Identifier: BSD-3-Clause */
36 * Contains global sysctl definitions which are shared between the legacy and
55 * @remark Head writeback has been deprecated and will only work on 700-series
73 "Display debug statements that are printed in non-shared code");
77 * @brief Debug mask for shared code messages
80 * Used by messages in shared device logic code.
85 "Display debug statements that are printed in shared code");
89 * @brief Rx interrupt throttling rate
91 * Controls the default interrupt throttling rate for receive interrupts.
95 &iavf_rx_itr, 0, "RX Interrupt Rate");
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/display/ti/ |
| H A D | ti,j721e-dss.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/display/ti/ti,j721e-dss.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Jyri Sarha <jsarha@ti.com>
12 - Tomi Valkeinen <tomi.valkeinen@ti.com>
22 const: ti,j721e-dss
26 - description: common_m DSS Master common
27 - description: common_s0 DSS Shared common 0
28 - description: common_s1 DSS Shared common 1
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/soc/qcom/ |
| H A D | qcom,smsm.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Shared Memory State Machine
10 - Andy Gross <agross@kernel.org>
11 - Bjorn Andersson <bjorn.andersson@linaro.org>
12 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
15 The Shared Memory State Machine facilitates broadcasting of single bit state
25 '#address-cells':
28 qcom,local-host:
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| H A D | qcom,smp2p.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Shared Memory Point 2 Point
10 - Andy Gross <agross@kernel.org>
11 - Bjorn Andersson <bjorn.andersson@linaro.org>
12 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
15 The Shared Memory Point to Point (SMP2P) protocol facilitates communication
16 of a single 32-bit value between two processors. Each value has a single
35 $ref: /schemas/types.yaml#/definitions/phandle-array
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| /freebsd/sys/contrib/device-tree/Bindings/gpio/ |
| H A D | gpio-sprd.txt | 3 The controller's registers are organized as sets of sixteen 16-bit
5 interrupt is shared for all of the banks handled by the controller.
8 - compatible: Should be "sprd,sc9860-gpio".
9 - reg: Define the base and range of the I/O address space containing
11 - gpio-controller: Marks the device node as a GPIO controller.
12 - #gpio-cells: Should be <2>. The first cell is the gpio number and
14 - interrupt-controller: Marks the device node as an interrupt controller.
15 - #interrupt-cells: Should be <2>. Specifies the number of cells needed
16 to encode interrupt source.
17 - interrupts: Should be the port interrupt shared by all the gpios.
[all …]
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| H A D | sprd,gpio.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Orson Zhai <orsonzhai@gmail.com>
12 - Baolin Wang <baolin.wang7@gmail.com>
13 - Chunyan Zhang <zhang.lyra@gmail.com>
16 The controller's registers are organized as sets of sixteen 16-bit
18 interrupt is shared for all of the banks handled by the controller.
23 - const: sprd,sc9860-gpio
24 - items:
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| H A D | brcm,brcmstb-gpio.txt | 3 The controller's registers are organized as sets of eight 32-bit
5 interrupt is shared for all of the banks handled by the controller.
9 - compatible:
10 Must be "brcm,brcmstb-gpio"
12 - reg:
16 - #gpio-cells:
19 bit[0]: polarity (0 for active-high, 1 for active-low)
21 - gpio-controller:
24 - brcm,gpio-bank-widths:
30 - interrupts:
[all …]
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| H A D | brcm,brcmstb-gpio.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/brcm,brcmstb-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The controller's registers are organized as sets of eight 32-bit
12 interrupt is shared for all of the banks handled by the controller.
15 - Doug Berger <opendmb@gmail.com>
16 - Florian Fainelli <f.fainelli@gmail.com>
21 - enum:
22 - brcm,bcm7445-gpio
[all …]
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| H A D | fsl-imx-gpio.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/gpio/fsl-imx-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Guo <shawnguo@kernel.org>
11 - Sascha Hauer <s.hauer@pengutronix.de>
12 - Fabio Estevam <festevam@gmail.com>
17 - enum:
18 - fsl,imx1-gpio
19 - fsl,imx21-gpio
[all …]
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| /freebsd/sys/contrib/device-tree/src/arm/st/ |
| H A D | stm32mp15xx-osd32.dtsi | 1 /* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) */
3 * Copyright (C) 2020 STMicroelectronics - All Rights Reserved
7 #include "stm32mp15-pinctrl.dtsi"
9 #include <dt-bindings/mfd/st,stpmic1.h>
12 reserved-memory {
13 #address-cells = <1>;
14 #size-cells = <1>;
18 compatible = "shared-dma-pool";
20 no-map;
24 compatible = "shared-dma-pool";
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| H A D | stm32mp157c-odyssey-som.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
6 /dts-v1/;
10 #include "stm32mp15-pinctrl.dtsi"
11 #include "stm32mp15xxac-pinctrl.dtsi"
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-binding
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| H A D | stm32mp15xx-dhcor-som.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
3 * Copyright (C) Linaro Ltd 2019 - All Rights Reserved
8 #include "stm32mp15-pinctrl.dtsi"
9 #include "stm32mp15xxac-pinctrl.dtsi"
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-binding
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| H A D | ste-href-tvk1281618-r2.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/input/input.h>
11 compatible = "gpio-key
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| /freebsd/sys/contrib/device-tree/Bindings/soc/ti/ |
| H A D | ti,pruss.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 TI Programmable Real-Time Unit and Industrial Communication Subsystem
11 - Suman Anna <s-anna@ti.com>
15 The Programmable Real-Time Unit and Industrial Communication Subsystem
16 (PRU-ICSS a.k.a. PRUSS) is present on various TI SoCs such as AM335x, AM437x,
17 Keystone 66AK2G, OMAP-L138/DA850 etc. A PRUSS consists of dual 32-bit RISC
18 cores (Programmable Real-Time Units, or PRUs), shared RAM, data and
20 communication, and an interrupt controller.
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/thermal/ |
| H A D | exynos-thermal.txt | 5 - compatible : One of the following:
6 "samsung,exynos3250-tmu"
7 "samsung,exynos4412-tmu"
8 "samsung,exynos4210-tmu"
9 "samsung,exynos5250-tmu"
10 "samsung,exynos5260-tmu"
11 "samsung,exynos5420-tmu" for TMU channel 0, 1 on Exynos5420
12 "samsung,exynos5420-tmu-ext-triminfo" for TMU channels 2, 3 and 4
14 "samsung,exynos5433-tmu"
15 "samsung,exynos7-tmu"
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/net/ |
| H A D | cavium-mix.txt | 4 - compatible: "cavium,octeon-5750-mix"
9 - reg: The base addresses of four separate register banks. The first
11 AGL registers. The third bank are the AGL registers shared by all
12 MIX devices present. The fourth bank is the AGL_PRT_CTL shared by
15 - cell-index: A single cell specifying which portion of the shared
18 - interrupts: Two interrupt specifiers. The first is the MIX
19 interrupt routing and the second the routing for the AGL interrupts.
21 - phy-handle: Optional, see ethernet.txt file in the same directory.
25 compatible = "cavium,octeon-5750-mix";
30 cell-index = <1>;
[all …]
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