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Searched +full:sg2042 +full:- +full:reset (Results 1 – 7 of 7) sorted by relevance

/linux/Documentation/devicetree/bindings/reset/
H A Dsophgo,sg2042-reset.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/reset/sophgo,sg2042-reset.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Sophgo SG2042 SoC Reset Controller
10 - Chen Wang <unicorn_wang@outlook.com>
14 const: sophgo,sg2042-reset
19 "#reset-cells":
23 - compatible
24 - reg
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/linux/arch/riscv/boot/dts/sophgo/
H A Dsg2042.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 /dts-v1/;
7 #include <dt-bindings/clock/sophgo,sg2042-clkgen.h>
8 #include <dt-bindings/clock/sophgo,sg2042-pll.h>
9 #include <dt-bindings/clock/sophgo,sg2042-rpgate.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/reset/sophgo,sg2042-reset.h>
13 #include "sg2042-cpus.dtsi"
16 compatible = "sophgo,sg2042";
17 #address-cells = <2>;
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/linux/Documentation/hwmon/
H A Dsg2042-mcu.rst1 .. SPDX-License-Identifier: GPL-2.0
3 Kernel driver sg2042-mcu
8 * Onboard MCU for sg2042
10 Addresses scanned: -
12 Prefix: 'sg2042-mcu'
16 - Inochi Amaoto <inochiama@outlook.com>
19 -----------
25 -----------
27 This driver does not auto-detect devices. You will have to instantiate
29 Please see Documentation/i2c/instantiating-devices.rst for details.
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/linux/Documentation/devicetree/bindings/mmc/
H A Dsnps,dwcmshc-sdhci.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/mmc/snps,dwcmshc-sdhci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ulf Hansson <ulf.hansson@linaro.org>
11 - Jisheng Zhang <Jisheng.Zhang@synaptics.com>
16 - items:
17 - const: rockchip,rk3576-dwcmshc
18 - const: rockchip,rk3588-dwcmshc
19 - enum:
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/linux/drivers/clk/sophgo/
H A Dclk-sg2042-clkgen.c1 // SPDX-License-Identifier: GPL-2.0
3 * Sophgo SG2042 Clock Generator Driver
12 #include <linux/clk-provider.h>
17 #include <dt-bindings/clock/sophgo,sg2042-clkgen.h>
19 #include "clk-sg2042.h"
23 #define R_PLL_STAT (0xC0 - R_PLL_BEGIN)
24 #define R_PLL_CLKEN_CONTROL (0xC4 - R_PLL_BEGIN)
25 #define R_MPLL_CONTROL (0xE8 - R_PLL_BEGIN)
26 #define R_FPLL_CONTROL (0xF4 - R_PLL_BEGIN)
27 #define R_DPLL0_CONTROL (0xF8 - R_PLL_BEGIN)
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/linux/drivers/reset/
H A Dreset-simple.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Simple Reset Controller Driver
7 * Based on Allwinner SoCs Reset Controller driver
11 * Maxime Ripard <maxime.ripard@free-electrons.com>
20 #include <linux/reset-controller.h>
21 #include <linux/reset/reset-simple.h>
40 spin_lock_irqsave(&data->lock, flags); in reset_simple_update()
42 reg = readl(data->membase + (bank * reg_width)); in reset_simple_update()
43 if (assert ^ data->active_low) in reset_simple_update()
47 writel(reg, data->membase + (bank * reg_width)); in reset_simple_update()
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/linux/drivers/mmc/host/
H A Dsdhci-of-dwcmshc.c1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/arm-smccc.h>
14 #include <linux/dma-mapping.h>
21 #include <linux/reset.h>
24 #include "sdhci-pltfm.h"
41 /* Tuning and auto-tuning fields in AT_CTRL_R control register */
51 #define AT_CTRL_PRE_CHANGE_DLY 0x1 /* 2-cycle latency */
53 #define AT_CTRL_POST_CHANGE_DLY 0x3 /* 4-cycle latency */
118 #define PHY_CNFG_RSTN_DEASSERT 0x1 /* Deassert PHY reset */
122 #define PHY_CNFG_PAD_SP_SG2042 0x09 /* PMOS TX drive strength for SG2042 */
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