Lines Matching +full:sg2042 +full:- +full:reset
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 /dts-v1/;
7 #include <dt-bindings/clock/sophgo,sg2042-clkgen.h>
8 #include <dt-bindings/clock/sophgo,sg2042-pll.h>
9 #include <dt-bindings/clock/sophgo,sg2042-rpgate.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/reset/sophgo,sg2042-reset.h>
13 #include "sg2042-cpus.dtsi"
16 compatible = "sophgo,sg2042";
17 #address-cells = <2>;
18 #size-cells = <2>;
19 dma-noncoherent;
26 compatible = "fixed-clock";
27 clock-output-names = "cgi_main";
28 #clock-cells = <0>;
32 compatible = "fixed-clock";
33 clock-output-names = "cgi_dpll0";
34 #clock-cells = <0>;
38 compatible = "fixed-clock";
39 clock-output-names = "cgi_dpll1";
40 #clock-cells = <0>;
44 compatible = "simple-bus";
45 #address-cells = <2>;
46 #size-cells = <2>;
47 interrupt-parent = <&intc>;
51 compatible = "snps,designware-i2c";
53 #address-cells = <1>;
54 #size-cells = <0>;
56 clock-names = "ref";
57 clock-frequency = <100000>;
64 compatible = "snps,designware-i2c";
66 #address-cells = <1>;
67 #size-cells = <0>;
69 clock-names = "ref";
70 clock-frequency = <100000>;
77 compatible = "snps,designware-i2c";
79 #address-cells = <1>;
80 #size-cells = <0>;
82 clock-names = "ref";
83 clock-frequency = <100000>;
90 compatible = "snps,designware-i2c";
92 #address-cells = <1>;
93 #size-cells = <0>;
95 clock-names = "ref";
96 clock-frequency = <100000>;
103 compatible = "snps,dw-apb-gpio";
105 #address-cells = <1>;
106 #size-cells = <0>;
109 clock-names = "bus", "db";
111 port0a: gpio-controller@0 {
112 compatible = "snps,dw-apb-gpio-port";
113 gpio-controller;
114 #gpio-cells = <2>;
117 interrupt-controller;
118 #interrupt-cells = <2>;
119 interrupt-parent = <&intc>;
125 compatible = "snps,dw-apb-gpio";
127 #address-cells = <1>;
128 #size-cells = <0>;
131 clock-names = "bus", "db";
133 port1a: gpio-controller@0 {
134 compatible = "snps,dw-apb-gpio-port";
135 gpio-controller;
136 #gpio-cells = <2>;
139 interrupt-controller;
140 #interrupt-cells = <2>;
141 interrupt-parent = <&intc>;
147 compatible = "snps,dw-apb-gpio";
149 #address-cells = <1>;
150 #size-cells = <0>;
153 clock-names = "bus", "db";
155 port2a: gpio-controller@0 {
156 compatible = "snps,dw-apb-gpio-port";
157 gpio-controller;
158 #gpio-cells = <2>;
161 interrupt-controller;
162 #interrupt-cells = <2>;
163 interrupt-parent = <&intc>;
168 pllclk: clock-controller@70300100c0 {
169 compatible = "sophgo,sg2042-pll";
172 clock-names = "cgi_main", "cgi_dpll0", "cgi_dpll1";
173 #clock-cells = <1>;
176 rpgate: clock-controller@7030010368 {
177 compatible = "sophgo,sg2042-rpgate";
180 clock-names = "rpgate";
181 #clock-cells = <1>;
184 clkgen: clock-controller@7030012000 {
185 compatible = "sophgo,sg2042-clkgen";
191 clock-names = "mpll",
195 #clock-cells = <1>;
198 clint_mswi: interrupt-controller@7094000000 {
199 compatible = "sophgo,sg2042-aclint-mswi", "thead,c900-aclint-mswi";
201 interrupts-extended = <&cpu0_intc 3>,
268 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
270 reg-names = "mtimecmp";
271 interrupts-extended = <&cpu0_intc 7>,
278 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
280 reg-names = "mtimecmp";
281 interrupts-extended = <&cpu4_intc 7>,
288 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
290 reg-names = "mtimecmp";
291 interrupts-extended = <&cpu8_intc 7>,
298 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
300 reg-names = "mtimecmp";
301 interrupts-extended = <&cpu12_intc 7>,
308 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
310 reg-names = "mtimecmp";
311 interrupts-extended = <&cpu16_intc 7>,
318 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
320 reg-names = "mtimecmp";
321 interrupts-extended = <&cpu20_intc 7>,
328 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
330 reg-names = "mtimecmp";
331 interrupts-extended = <&cpu24_intc 7>,
338 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
340 reg-names = "mtimecmp";
341 interrupts-extended = <&cpu28_intc 7>,
348 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
350 reg-names = "mtimecmp";
351 interrupts-extended = <&cpu32_intc 7>,
358 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
360 reg-names = "mtimecmp";
361 interrupts-extended = <&cpu36_intc 7>,
368 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
370 reg-names = "mtimecmp";
371 interrupts-extended = <&cpu40_intc 7>,
378 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
380 reg-names = "mtimecmp";
381 interrupts-extended = <&cpu44_intc 7>,
388 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
390 reg-names = "mtimecmp";
391 interrupts-extended = <&cpu48_intc 7>,
398 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
400 reg-names = "mtimecmp";
401 interrupts-extended = <&cpu52_intc 7>,
408 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
410 reg-names = "mtimecmp";
411 interrupts-extended = <&cpu56_intc 7>,
418 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
420 reg-names = "mtimecmp";
421 interrupts-extended = <&cpu60_intc 7>,
427 intc: interrupt-controller@7090000000 {
428 compatible = "sophgo,sg2042-plic", "thead,c900-plic";
429 #address-cells = <0>;
430 #interrupt-cells = <2>;
432 interrupt-controller;
433 interrupts-extended =
501 rstgen: reset-controller@7030013000 {
502 compatible = "sophgo,sg2042-reset";
504 #reset-cells = <1>;
508 compatible = "snps,dw-apb-uart";
511 clock-frequency = <500000000>;
514 clock-names = "baudclk", "apb_pclk";
515 reg-shift = <2>;
516 reg-io-width = <4>;
522 compatible = "sophgo,sg2042-dwcmshc";
524 interrupt-parent = <&intc>;
529 clock-names = "core",
536 compatible = "sophgo,sg2042-dwcmshc";
538 interrupt-parent = <&intc>;
543 clock-names = "core",