| /linux/drivers/char/ipmi/ |
| H A D | ipmi_si_hardcode.c | 1 // SPDX-License-Identifier: GPL-2.0+
11 * There can be 4 IO ports passed in (with or without IRQs), 4 addresses,
12 * a default IO port, and 1 ACPI/SPMI address. That sets SI_MAX_DRIVERS.
21 static unsigned int ports[SI_MAX_PARMS]; variable
36 …"Defines the type of each interface, each interface separated by commas. The types are 'kcs', 'sm…
39 …"Sets the memory address of each interface, the addresses separated by commas. Only use if an int…
40 module_param_hw_array(ports, uint, ioport, &num_ports, 0);
41 MODULE_PARM_DESC(ports,
42 …"Sets the port address of each interface, the addresses separated by commas. Only use if an inter…
45 …"Sets the interrupt of each interface, the addresses separated by commas. Only use if an interfac…
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| /linux/Documentation/networking/ |
| H A D | generic-hdlc.rst | 1 .. SPDX-License-Identifier: GPL-2.0
14 - Normal (routed) and Ethernet-bridged (Ethernet device emulation)
16 - ARP support (no InARP support in the kernel - there is an
17 experimental InARP user-space daemon available on:
20 2. raw HDLC - either IP (IPv4) interface or Ethernet device emulation
25 Generic HDLC is a protocol driver only - it needs a low-level driver
28 Ethernet device emulation (using HDLC or Frame-Relay PVC) is compatible
33 create a number of "hdlc" (hdlc0 etc) network devices, one for each
40 gcc -O2 -Wall -o sethdlc sethdlc.c
42 Make sure you're using a correct version of sethdlc for your kernel.
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| H A D | ppp_generic.rst | 1 .. SPDX-License-Identifier: GPL-2.0
12 The generic PPP driver in linux-2.4 provides an implementation of the
13 functionality which is of use in any PPP implementation, including:
26 the services of PPP ``channels``. A PPP channel encapsulates a
32 implementations for asynchronous serial ports, synchronous serial
33 ports, and for PPP over ethernet.
43 ---------------
45 See include/linux/ppp_channel.h for the declaration of the types and
53 send. The channel has the option of rejecting the frame for
54 flow-control reasons. In this case, start_xmit() should return 0
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| /linux/Documentation/driver-api/tty/ |
| H A D | moxa-smartio.rst | 25 - 2 ports multiport board
26 CP-102U, CP-102UL, CP-102UF
27 CP-132U-I, CP-132UL,
28 CP-132, CP-132I, CP132S, CP-132IS,
29 (CP-102, CP-102S)
31 - 4 ports multiport board
32 CP-104EL,
33 CP-104UL, CP-104JU,
34 CP-134U, CP-134U-I,
36 CP-114, CP-114I, CP-114S, CP-114IS, CP-114UL,
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| /linux/include/media/i2c/ |
| H A D | tc358743.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * tc358743 - Toshiba HDMI to CSI-2 bridge
10 * REF_01 - Toshiba, TC358743XBG (H2C), Functional Specification, Rev 0.60
11 * REF_02 - Toshiba, TC358743XBG_HDMI-CSI_Tv11p_nm.xls
37 * Sets DDC5V_MODE in register DDC_CTL.
47 * mismatches in input and output ports.
57 * CSI interface can handle. The driver will adjust the number of CSI
60 * The values in brackets are calculated with REF_02 when the number of
73 /* DVI->HDMI detection delay to avoid unnecessary switching between DVI
75 * Sets HDMI_DET_V in register HDMI_DET.
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|
| /linux/Documentation/networking/device_drivers/ethernet/3com/ |
| H A D | vortex.rst | 1 .. SPDX-License-Identifier: GPL-2.0
12 This document describes the usage and errata of the 3Com "Vortex" device
17 Don is no longer the prime maintainer of this version of the driver.
18 Please report problems to one or more of:
20 - Andrew Morton
21 - Netdev mailing list <netdev@vger.kernel.org>
22 - Linux kernel mailing list <linux-kernel@vger.kernel.org>
25 of this file.
28 Since kernel 2.3.99-pre6, this driver incorporates the support for the
29 3c575-series Cardbus cards which used to be handled by 3c575_cb.c.
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| /linux/Documentation/devicetree/bindings/pinctrl/ |
| H A D | renesas,rza1-ports.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/renesas,rza1-ports.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jacopo Mondi <jacopo+renesas@jmondi.org>
11 - Geert Uytterhoeven <geert+renesas@glider.be>
14 The Renesas SoCs of the RZ/A1 family feature a combined Pin and GPIO
15 controller, named "Ports" in the hardware reference manual.
16 Pin multiplexing and GPIO configuration is performed on a per-pin basis
17 writing configuration values to per-port register sets.
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| /linux/drivers/s390/scsi/ |
| H A D | zfcp_ccw.c | 1 // SPDX-License-Identifier: GPL-2.0
27 adapter = dev_get_drvdata(&cdev->dev); in zfcp_ccw_adapter_by_cdev()
29 kref_get(&adapter->ref); in zfcp_ccw_adapter_by_cdev()
39 kref_put(&adapter->ref, zfcp_adapter_release); in zfcp_ccw_adapter_put()
44 * zfcp_ccw_activate - activate adapter and wait for it to finish
62 * We want to scan ports here, with some random backoff and without in zfcp_ccw_activate()
70 * point in waiting a random delay on top of the time consumed by in zfcp_ccw_activate()
75 flush_delayed_work(&adapter->scan_work); in zfcp_ccw_activate()
90 * zfcp_ccw_probe - probe function of zfcp driver
104 * zfcp_ccw_remove - remove function of zfcp driver
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| /linux/Documentation/networking/device_drivers/ethernet/intel/ |
| H A D | iavf.rst | 1 .. SPDX-License-Identifier: GPL-2.0+
8 Copyright(c) 2013-2018 Intel Corporation.
13 - Overview
14 - Identifying Your Adapter
15 - Additional Configurations
16 - Known Issues/Troubleshooting
17 - Support
30 The guest OS loading the iavf driver must support MSI-X interrupts.
53 ---------------------
58 # dmesg -n 8
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| /linux/drivers/usb/host/ |
| H A D | xhci-hub.c | 1 // SPDX-License-Identifier: GPL-2.0
18 #include "xhci-trace.h"
24 /* Default sublink speed attribute of each lane */
54 bos->bLength = USB_DT_BOS_SIZE; in xhci_create_usb3x_bos_desc()
55 bos->bDescriptorType = USB_DT_BOS; in xhci_create_usb3x_bos_desc()
56 bos->wTotalLength = cpu_to_le16(USB_DT_BOS_SIZE + in xhci_create_usb3x_bos_desc()
58 bos->bNumDeviceCaps = 1; in xhci_create_usb3x_bos_desc()
61 for (i = 0; i < xhci->num_port_caps; i++) { in xhci_create_usb3x_bos_desc()
62 u8 major = xhci->port_caps[i].maj_rev; in xhci_create_usb3x_bos_desc()
63 u8 minor = xhci->port_caps[i].min_rev; in xhci_create_usb3x_bos_desc()
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| /linux/arch/mips/mm/ |
| H A D | sc-mips.c | 1 // SPDX-License-Identifier: GPL-2.0
10 #include <asm/cpu-type.h>
17 #include <asm/mips-cps.h>
38 unsigned long almask = ~(lsize - 1); in mips_sc_inv()
41 cache_op(Hit_Writeback_Inv_SD, (addr + size - 1) & almask); in mips_sc_inv()
64 * prefetching for both code & data, for all ports. in mips_sc_prefetch_enable()
113 * MTI's L2 controller and the L2 cache controller of Broadcom's BMIPS
116 * true on all platforms. In an act of stupidity the spec defined bits
143 c->scache.linesz = 2 << tmp; in mips_sc_is_activated()
153 unsigned long sets, line_sz, assoc; in mips_sc_probe_cm3() local
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| /linux/drivers/net/ethernet/chelsio/cxgb4vf/ |
| H A D | cxgb4vf_main.c | 2 * This file is part of the Chelsio T4 PCI-E SR-IOV Virtual Function Ethernet
5 * Copyright (c) 2009-2010 Chelsio Communications, Inc. All rights reserved.
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
10 * COPYING in the main directory of this source tree, or the
17 * - Redistributions of source code must retain the above
18 * copyright notice, this list of conditions and the following
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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|
| H A D | adapter.h | 2 * This file is part of the Chelsio T4 PCI-E SR-IOV Virtual Function Ethernet
5 * Copyright (c) 2009-2010 Chelsio Communications, Inc. All rights reserved.
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
10 * COPYING in the main directory of this source tree, or the
17 * - Redistributions of source code must retain the above
18 * copyright notice, this list of conditions and the following
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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|
| /linux/Documentation/devicetree/bindings/display/samsung/ |
| H A D | samsung,exynos-hdmi.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/display/samsung/samsung,exynos-hdmi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Inki Dae <inki.dae@samsung.com>
11 - Seung-Woo Kim <sw0312.kim@samsung.com>
12 - Kyungmin Park <kyungmin.park@samsung.com>
13 - Krzysztof Kozlowski <krzk@kernel.org>
18 - samsung,exynos4210-hdmi
19 - samsung,exynos4212-hdmi
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|
| /linux/drivers/platform/mellanox/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
36 which are the part of SN4280 Ethernet smart switch systems
38 Centers (EDC) for building Ethernet based clusters, High-Performance
49 This driver handles hot-plug events for the power suppliers, power
58 space through sysfs interface. The sets of registers for sysfs access
61 kinds of mux selection.
69 This driver provides support for the Mellanox MSN4800-XX line cards,
70 which are the part of MSN4800 Ethernet modular switch systems
72 Centers (EDC) for building Ethernet based clusters, High-Performance
96 device driver to do necessary initial swap of the boot partition.
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|
| /linux/drivers/net/dsa/microchip/ |
| H A D | ksz9477_acl.c | 1 // SPDX-License-Identifier: GPL-2.0
6 * There are multiple groups of registers involved in ACL configuration:
8 * - Matching Rules: These registers define the criteria for matching incoming
13 * - Action Rules: These registers define how the ACL should modify the packet's
18 * - Processing Rules: These registers control the overall behavior of the ACL,
23 * +----------------------+
24 * +----------------------+ | (optional) |
27 * +----------------------+ +----------------------+
31 * +----------------------+
35 * +----------------------+
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|
| /linux/Documentation/scsi/ |
| H A D | libsas.rst | 1 .. SPDX-License-Identifier: GPL-2.0
32 Most of it is used by the SAS Layer but a few fields need to
47 ------------------
58 And then all the phys are an array of my_phy in your HA
65 In general, the phys are managed by the LLDD and the ports
67 and updated by the LLDD and the ports are initialized and
75 - must be set (0/1)
78 - must be set [0,MAX_PHYS)]
81 - must be set
84 - you set this when OOB has finished and then notify
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| /linux/arch/arm64/boot/dts/mediatek/ |
| H A D | mt8365.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
10 #include <dt-bindings/clock/mediatek,mt8365-clk.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/memory/mediatek,mt8365-larb-port.h>
14 #include <dt-bindings/phy/phy.h>
15 #include <dt-bindings/power/mediatek,mt8365-power.h>
19 interrupt-parent = <&sysirq>;
20 #address-cells = <2>;
21 #size-cells = <2>;
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|
| /linux/Documentation/arch/m68k/ |
| H A D | buddha-driver.rst | 5 The Amiga Buddha and Catweasel IDE Driver (part of ide.c) was written by
8 ------------------------------------------------------------------------
10 Register map of the Buddha IDE controller and the
11 Buddha-part of the Catweasel Zorro-II version
15 example leaving some address lines out of the equations...).
21 product number: 0 (42 for Catweasel Z-II)
23 Rom-vector: $1000
25 The card should be a Z-II board, size 64K, not for freemem
26 list, Rom-Vektor is valid, no second Autoconfig-board on the
30 as the Amiga Kickstart does: The lower nibble of the 8-Bit
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| /linux/Documentation/driver-api/cxl/ |
| H A D | theory-of-operation.rst | 1 .. SPDX-License-Identifier: GPL-2.0
5 Compute Express Link Driver Theory of Operation
9 CXL.mem protocol. It contains some amount of volatile memory, persistent memory,
14 range across multiple devices underneath a host-bridge or interleaved
15 across host-bridges.
22 of the CXL.mem topology is also similar to RAID in that different environments
28 Platform firmware enumerates a menu of interleave options at the "CXL root port"
29 (Linux term for the top of the CXL decode topology). From there, PCIe topology
34 interleave cycles across multiple Root Ports. An intervening Switch between a
36 Ports, etc.
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| /linux/tools/testing/selftests/drivers/net/hw/ |
| H A D | devlink_rate_tc_bw.py | 2 # SPDX-License-Identifier: GPL-2.0
8 This test suite verifies the functionality of devlink-rate traffic class (TC)
14 ----------------
15 - Creates 1 VF
16 - Establishes a bridge connecting the VF representor and the uplink representor
17 - Sets up 2 VLAN interfaces on the VF with different VLAN IDs (101, 102)
18 - Configures different traffic classes (TC3 and TC4) for each VLAN
21 ----------
23 - Verifies that without TC mapping, bandwidth is NOT distributed according to
25 - This test should fail if bandwidth matches the 80/20 split without TC
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| /linux/arch/arm64/boot/dts/nvidia/ |
| H A D | tegra234.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/clock/tegra234-clock.h>
4 #include <dt-bindings/gpio/tegra234-gpio.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/mailbox/tegra186-hsp.h>
7 #include <dt-bindings/memory/tegra234-mc.h>
8 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
9 #include <dt-bindings/power/tegra234-powergate.h>
10 #include <dt-bindings/reset/tegra234-reset.h>
11 #include <dt-bindings/thermal/tegra234-bpmp-thermal.h>
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|
| /linux/Documentation/devicetree/bindings/media/ |
| H A D | ti,omap3isp.txt | 4 The DT definitions can be found in include/dt-bindings/media/omap3-isp.h.
9 compatible : must contain "ti,omap3-isp"
11 reg : the two registers sets (physical address and length) for the
13 the end of the SBL block. The second set contains the
17 syscon : the phandle and register offset to the Complex I/O or CSI-PHY
19 ti,phy-type : 0 -- OMAP3ISP_PHY_TYPE_COMPLEX_IO (e.g. 3430)
20 1 -- OMAP3ISP_PHY_TYPE_CSIPHY (e.g. 3630)
21 #clock-cells : Must be 1 --- the ISP provides two external clocks,
24 clock bindings in ../clock/clock-bindings.txt.
27 ---------------------
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|
| /linux/drivers/parport/ |
| H A D | parport_gsc.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Low-level parallel-support for PC-style hardware integrated in the
4 * LASI-Controller (on GSC-Bus) for HP-PARISC Workstations
6 * (C) 1999-2001 by Helge Deller <deller@gmx.de>
36 #include <asm/parisc-device.h>
42 MODULE_DESCRIPTION("HP-PARISC PC-style parallel port driver");
71 * Most of these aren't static because they may be used by the
72 * parport_xxx_yyy macros. extern __inline__ versions of several
73 * of these are in parport_gsc.h.
78 s->u.pc.ctr = 0xc | (dev->irq_func ? 0x10 : 0x0); in parport_gsc_init_state()
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| /linux/Documentation/driver-api/cxl/linux/ |
| H A D | cxl-driver.rst | 1 .. SPDX-License-Identifier: GPL-2.0
12 The :code:`cxl-cli` library, maintained as part of the NDTCL project, may
17 The CXL driver is split into a number of drivers.
19 * cxl_core - fundamental init interface and core object creation
20 * cxl_port - initializes root and provides port enumeration interface.
21 * cxl_acpi - initializes root decoders and interacts with ACPI data.
22 * cxl_p/mem - initializes memory devices
23 * cxl_pci - uses cxl_port to enumerate the actual fabric hierarchy.
27 Here is an example from a single-socket system with 4 host bridges. Two host
38 .. kernel-render:: DOT
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|