| /linux/drivers/clk/ |
| H A D | clk_test.c | 1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/clk-provider.h>
7 #include <linux/clk/clk-conf.h>
30 unsigned long rate; member
39 return ctx->rate; in clk_dummy_recalc_rate()
45 /* Just return the same rate without modifying it */ in clk_dummy_determine_rate()
53 * If there's a maximum set, always run the clock at the maximum in clk_dummy_maximize_rate()
56 if (req->max_rate < ULONG_MAX) in clk_dummy_maximize_rate()
57 req->rate = req->max_rate; in clk_dummy_maximize_rate()
66 * If there's a minimum set, always run the clock at the minimum in clk_dummy_minimize_rate()
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| H A D | clk.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
4 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
6 * Standard functionality for the common clock API. See Documentation/driver-api/clk.rst
10 #include <linux/clk-provider.h>
11 #include <linux/clk/clk-conf.h>
68 struct clk_core *parent; member
72 unsigned long rate; member
116 if (!core->rpm_enabled) in clk_pm_runtime_get()
119 return pm_runtime_resume_and_get(core->dev); in clk_pm_runtime_get()
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| /linux/drivers/clk/ti/ |
| H A D | dpll3xxx.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * OMAP3/4 - specific DPLL control functions
5 * Copyright (C) 2009-2010 Texas Instruments, Inc.
6 * Copyright (C) 2009-2010 Nokia Corporation
46 /* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */
52 dd = clk->dpll_data; in _omap3_dpll_write_clken()
54 v = ti_clk_ll_ops->clk_readl(&dd->control_reg); in _omap3_dpll_write_clken()
55 v &= ~dd->enable_mask; in _omap3_dpll_write_clken()
56 v |= clken_bits << __ffs(dd->enable_mask); in _omap3_dpll_write_clken()
57 ti_clk_ll_ops->clk_writel(v, &dd->control_reg); in _omap3_dpll_write_clken()
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| /linux/drivers/clk/samsung/ |
| H A D | clk-cpu.c | 1 // SPDX-License-Identifier: GPL-2.0-only
15 * CPU clock rate and this relation is usually specified in the hardware manual
18 * The below implementation of the CPU clock allows the rate changes of the CPU
19 * clock and the corresponding rate changes of the auxiliary clocks of the CPU
21 * for each configurable rate which is then used to program the clock hardware
22 * registers to achieve a fast coordinated rate change for all the CPU domain
25 * On a rate change request for the CPU clock, the rate change is propagated
29 * down in order to keep the output clock rate within the previous OPP limits.
37 #include <linux/clk-provider.h>
40 #include "clk-cpu.h"
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| /linux/drivers/clk/imx/ |
| H A D | clk-scu.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2021 NXP
7 #include <dt-bindings/firmware/imx/rsrc.h>
8 #include <linux/arm-smccc.h>
10 #include <linux/clk-provider.h>
20 #include "clk-scu.h"
44 * struct clk_scu - Description of one SCU clock
55 struct clk_hw *parent; member
58 u32 rate; member
62 * struct clk_gpr_scu - Description of one SCU GPR clock
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| /linux/tools/testing/selftests/drivers/net/netdevsim/ |
| H A D | devlink.sh | 2 # SPDX-License-Identifier: GPL-2.0
22 "$@" | grep -q $DL_HANDLE
34 DUMMYFILE=$(find /lib/firmware -type f -printf '%P\n' | head -1)
37 if [ -z "$DUMMYFILE" ]
80 cmd_jq "devlink dev param show $DL_HANDLE name $name -j" \
89 devlink dev param set $DL_HANDLE name $name cmode driverinit value $value
121 check_err $? "Failed to set max_macs param value"
123 check_err $? "Failed to set test1 param value"
125 check_value max_macs post-set 16 32
126 check_value test1 post-set false Y
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| /linux/drivers/clk/tegra/ |
| H A D | clk-tegra210-emc.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2015-2020, NVIDIA CORPORATION. All rights reserved.
8 #include <linux/clk-provider.h>
57 value = readl_relaxed(emc->regs + CLK_SOURCE_EMC); in tegra210_clk_emc_get_parent()
70 * CCF assumes that neither the parent nor its rate will change during in tegra210_clk_emc_recalc_rate()
71 * ->set_rate(), so the parent rate passed in here was cached from the in tegra210_clk_emc_recalc_rate()
72 * parent before the ->set_rate() call. in tegra210_clk_emc_recalc_rate()
75 * the parent and/or parent rate have changed as part of the EMC rate in tegra210_clk_emc_recalc_rate()
76 * change sequence. Fix this by overriding the parent clock with what in tegra210_clk_emc_recalc_rate()
77 * we know to be the correct value after the rate change. in tegra210_clk_emc_recalc_rate()
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| H A D | clk-tegra124-emc.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/clk/tegra/clk-emc.c
11 #include <linux/clk-provider.h>
48 * When we change the timing to a timing with a parent that has the same
49 * clock source as the current parent, we must first change to a backup
66 unsigned long rate, parent_rate; member
68 struct clk *parent; member
100 * CCF wrongly assumes that the parent won't change during set_rate, in emc_recalc_rate()
101 * so get the parent rate explicitly. in emc_recalc_rate()
105 val = readl(tegra->clk_regs + CLK_SOURCE_EMC); in emc_recalc_rate()
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| /linux/drivers/clk/zynqmp/ |
| H A D | divider.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2019 Xilinx
11 #include <linux/clk-provider.h>
13 #include "clk-zynqmp.h"
19 * prepare - clk_prepare only ensures that parents are prepared
20 * enable - clk_enable only ensures that parents are enabled
21 * rate - rate is adjustable. clk->rate = ceiling(parent->rate / divisor)
22 * parent - fixed parent. No clk_set_parent support
28 #define CLK_FRAC BIT(13) /* has a fractional parent */
29 #define CUSTOM_FLAG_CLK_FRAC BIT(0) /* has a fractional parent in custom type flag */
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| /linux/drivers/clk/rockchip/ |
| H A D | clk-cpu.c | 1 // SPDX-License-Identifier: GPL-2.0-only
6 * based on clk/samsung/clk-cpu.c
15 * CPU clock rate and this relation is usually specified in the hardware manual
18 * The below implementation of the CPU clock allows the rate changes of the CPU
19 * clock and the corresponding rate changes of the auxillary clocks of the CPU
21 * for each configurable rate which is then used to program the clock hardware
22 * registers to acheive a fast co-oridinated rate change for all the CPU domain
25 * On a rate change request for the CPU clock, the rate change is propagated
29 * down in order to keep the output clock rate within the previous OPP limits.
36 #include <linux/clk-provider.h>
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| /linux/drivers/clk/sunxi/ |
| H A D | clk-factors.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Adjustable factor-based clock implementation
8 #include <linux/clk-provider.h>
16 #include "clk-factors.h"
19 * DOC: basic adjustable factor-based clock
22 * prepare - clk_prepare only ensures that parents are prepared
23 * enable - clk_enable only ensures that parents are enabled
24 * rate - rate is adjustable.
25 * clk->rate = (parent->rate * N * (K + 1) >> P) / (M + 1)
26 * parent - fixed parent. No clk_set_parent support
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| /linux/drivers/clk/renesas/ |
| H A D | rcar-gen3-cpg.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * R-Car Gen3 Clock Pulse Generator
5 * Copyright (C) 2015-2018 Glider bvba
8 * Based on clk-rcar-gen3.c
16 #include <linux/clk-provider.h>
25 #include "renesas-cpg-mssr.h"
26 #include "rcar-cpg-lib.h"
27 #include "rcar-gen3-cpg.h"
59 val = readl(pll_clk->pllcr_reg) & CPG_PLLnCR_STC_MASK; in cpg_pll_clk_recalc_rate()
62 return parent_rate * mult * pll_clk->fixed_mult; in cpg_pll_clk_recalc_rate()
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| H A D | rcar-gen4-cpg.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * R-Car Gen4 Clock Pulse Generator
7 * Based on rcar-gen3-cpg.c
9 * Copyright (C) 2015-2018 Glider bvba
15 #include <linux/clk-provider.h>
23 #include "renesas-cpg-mssr.h"
24 #include "rcar-gen4-cpg.h"
25 #include "rcar-cpg-lib.h"
33 #define CPG_PLLECR_PLLST(n) BIT(8 + ((n) < 3 ? (n) - 1 : \
67 #define CPG_SD0CKCR1 0x8a4 /* SD-IF0 Clock Freq. Control Reg. 1 */
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| /linux/include/linux/ |
| H A D | clk-provider.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com>
4 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
14 * top-level framework. custom flags for dealing with hardware specifics
19 #define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */
20 #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */
21 #define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */
25 #define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */
26 #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
29 #define CLK_SET_RATE_UNGATE BIT(10) /* clock needs to run to set rate */
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| H A D | clk.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
7 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
24 * PRE_RATE_CHANGE - called immediately before the clk rate is changed,
25 * to indicate that the rate change will proceed. Drivers must
27 * rate change. Callbacks may either return NOTIFY_DONE, NOTIFY_OK,
30 * ABORT_RATE_CHANGE: called if the rate change failed for some reason
35 * POST_RATE_CHANGE - called after the clk rate change has successfully
44 * struct clk_notifier - associate a clk with a notifier
61 * struct clk_notifier_data - rate data to pass to the notifier callback
63 * @old_rate: previous rate of this clk
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| /linux/drivers/clk/at91/ |
| H A D | clk-generated.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Based on clk-programmable & clk-peripheral drivers by Boris BREZILLON.
10 #include <linux/clk-provider.h>
43 spin_lock_irqsave(gck->lock, flags); in clk_generated_set()
44 regmap_write(gck->regmap, gck->layout->offset, in clk_generated_set()
45 (gck->id & gck->layout->pid_mask)); in clk_generated_set()
46 regmap_update_bits(gck->regmap, gck->layout->offset, in clk_generated_set()
47 AT91_PMC_PCR_GCKDIV_MASK | gck->layout->gckcss_mask | in clk_generated_set()
48 gck->layout->cmd | enable, in clk_generated_set()
49 field_prep(gck->layout->gckcss_mask, gck->parent_id) | in clk_generated_set()
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| /linux/drivers/clk/bcm/ |
| H A D | clk-kona.c | 1 // SPDX-License-Identifier: GPL-2.0-only
7 #include "clk-kona.h"
12 #include <linux/clk-provider.h>
27 /* Produces a mask of set bits covering a range of a 32-bit value */
30 return ((1 << width) - 1) << shift; in bitfield_mask()
52 return (u64)reg_div + ((u64)1 << div->u.s.frac_width); in scaled_div_value()
68 combined <<= div->u.s.frac_width; in scaled_div_build()
78 return (u64)div->u.fixed; in scaled_div_min()
89 return (u64)div->u.fixed; in scaled_div_max()
91 reg_div = ((u32)1 << div->u.s.width) - 1; in scaled_div_max()
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| /linux/Documentation/networking/devlink/ |
| H A D | ice.rst | 1 .. SPDX-License-Identifier: GPL-2.0
13 .. list-table:: Generic parameters implemented
16 * - Name
17 - Mode
18 - Notes
19 * - ``enable_roce``
20 - runtime
21 - mutually exclusive with ``enable_iwarp``
22 * - ``enable_iwarp``
23 - runtime
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| /linux/drivers/clk/sunxi-ng/ |
| H A D | ccu_mp.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
7 #include <linux/clk-provider.h>
13 static unsigned long ccu_mp_find_best(unsigned long parent, unsigned long rate, in ccu_mp_find_best() argument
23 unsigned long tmp_rate = parent / _p / _m; in ccu_mp_find_best()
25 if (tmp_rate > rate) in ccu_mp_find_best()
28 if ((rate - tmp_rate) < (rate - best_rate)) { in ccu_mp_find_best()
43 unsigned long *parent, in ccu_mp_find_best_with_parent_adj() argument
44 unsigned long rate, in ccu_mp_find_best_with_parent_adj() argument
54 parent_rate_saved = *parent; in ccu_mp_find_best_with_parent_adj()
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| /linux/drivers/clk/mvebu/ |
| H A D | dove-divider.c | 1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
15 #include "dove-divider.h"
56 val = readl_relaxed(dc->base + DIV_CTRL0); in dove_get_divider()
57 val >>= dc->div_bit_start; in dove_get_divider()
59 divider = val & ~(~0 << dc->div_bit_size); in dove_get_divider()
61 if (dc->divider_table) in dove_get_divider()
62 divider = dc->divider_table[divider]; in dove_get_divider()
67 static int dove_calc_divider(const struct dove_clk *dc, unsigned long rate, in dove_calc_divider() argument
68 unsigned long parent_rate, bool set) in dove_calc_divider() argument
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| /linux/drivers/devfreq/ |
| H A D | imx8m-ddrc.c | 1 // SPDX-License-Identifier: GPL-2.0
13 #include <linux/clk-provider.h>
14 #include <linux/arm-smccc.h>
27 unsigned long rate; member
40 * +----------+ |\ +------+
41 * | dram_pll |-------|M| dram_core | |
42 * +----------+ |U|---------->| D |
43 * /--|X| | D |
46 * +---------+ | |
48 * +---------+ | |
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| /linux/Documentation/devicetree/bindings/clock/ti/ |
| H A D | ti,mux-clock.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/clock/ti/ti,mux-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tero Kristo <kristo@kernel.org>
13 This clock assumes a register-mapped multiplexer with multiple inpt clock
15 not gate or adjust the parent rate via a divider or multiplier.
24 register value selected parent clock
31 "index-starts-at-one" modified the scheme as follows:
33 register value selected clock parent
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| /linux/arch/mips/alchemy/common/ |
| H A D | clock.c | 1 // SPDX-License-Identifier: GPL-2.0
8 * - Root source, usually 12MHz supplied by an external crystal
9 * - 3 PLLs which generate multiples of root rate [AUX, CPU, AUX2]
12 * - 6 clock dividers with:
18 * - up to 6 "internal" (fixed) consumers which:
24 * - sysbus clock: CPU core clock (CPUPLL) divided by 2, 3 or 4.
25 * depends on board design and should be set by bootloader, read-only.
26 * - peripheral clock: half the rate of sysbus clock, source for a lot
27 * of peripheral blocks, read-only.
28 * - memory clock: clk rate to main memory chips, depends on board
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| /linux/drivers/sh/clk/ |
| H A D | core.c | 4 * Copyright (C) 2005 - 2010 Paul Mundt
8 * Copyright (C) 2004 - 2008 Nokia Corporation
49 clk->nr_freqs = nr_freqs; in clk_rate_table_build()
55 if (src_table->divisors && i < src_table->nr_divisors) in clk_rate_table_build()
56 div = src_table->divisors[i]; in clk_rate_table_build()
58 if (src_table->multipliers && i < src_table->nr_multipliers) in clk_rate_table_build()
59 mult = src_table->multipliers[i]; in clk_rate_table_build()
64 freq = clk->parent->rate * mult / div; in clk_rate_table_build()
78 unsigned long rate; member
85 for (pos = r->min, freq = r->func(pos, r); \
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| /linux/Documentation/networking/device_drivers/ethernet/ti/ |
| H A D | cpsw.rst | 1 .. SPDX-License-Identifier: GPL-2.0
26 - TX queues must be rated starting from txq0 that has highest priority
27 - Traffic classes are used starting from 0, that has highest priority
28 - CBS shapers should be used with rated queues
29 - The bandwidth for CBS shapers has to be set a little bit more then
30 potential incoming rate, thus, rate of all incoming tx queues has
32 - Real rates can differ, due to discreetness
33 - Map skb-priority to txq is not enough, also skb-priority to l2 prio
35 - Any l2/socket prio (0 - 7) for classes can be used, but for
37 - only 2 classes tested: A and B, but checked and can work with more,
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