| /linux/drivers/clk/ti/ |
| H A D | dpll3xxx.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * OMAP3/4 - specific DPLL control functions
5 * Copyright (C) 2009-2010 Texas Instruments, Inc.
6 * Copyright (C) 2009-2010 Nokia Corporation
46 /* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */
52 dd = clk->dpll_data; in _omap3_dpll_write_clken()
54 v = ti_clk_ll_ops->clk_readl(&dd->control_reg); in _omap3_dpll_write_clken()
55 v &= ~dd->enable_mask; in _omap3_dpll_write_clken()
56 v |= clken_bits << __ffs(dd->enable_mask); in _omap3_dpll_write_clken()
57 ti_clk_ll_ops->clk_writel(v, &dd->control_reg); in _omap3_dpll_write_clken()
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| /linux/drivers/clk/samsung/ |
| H A D | clk-cpu.c | 1 // SPDX-License-Identifier: GPL-2.0-only
15 * CPU clock rate and this relation is usually specified in the hardware manual
18 * The below implementation of the CPU clock allows the rate changes of the CPU
19 * clock and the corresponding rate changes of the auxiliary clocks of the CPU
21 * for each configurable rate which is then used to program the clock hardware
22 * registers to achieve a fast coordinated rate change for all the CPU domain
25 * On a rate change request for the CPU clock, the rate change is propagated
29 * down in order to keep the output clock rate within the previous OPP limits.
37 #include <linux/clk-provider.h>
40 #include "clk-cpu.h"
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| /linux/net/devlink/ |
| H A D | rate.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
12 return devlink_rate->type == DEVLINK_RATE_TYPE_LEAF; in devlink_rate_is_leaf()
18 return devlink_rate->type == DEVLINK_RATE_TYPE_NODE; in devlink_rate_is_node()
27 devlink_port = devlink_port_get_from_attrs(devlink, info->attrs); in devlink_rate_leaf_get_from_info()
30 devlink_rate = devlink_port->devlink_rate; in devlink_rate_leaf_get_from_info()
31 return devlink_rate ?: ERR_PTR(-ENODEV); in devlink_rate_leaf_get_from_info()
39 list_for_each_entry(devlink_rate, &devlink->rate_list, list) { in devlink_rate_node_get_by_name()
41 !strcmp(node_name, devlink_rate->name)) in devlink_rate_node_get_by_name()
44 return ERR_PTR(-ENODEV); in devlink_rate_node_get_by_name()
54 return ERR_PTR(-EINVAL); in devlink_rate_node_get_from_attrs()
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| /linux/drivers/clk/tegra/ |
| H A D | clk-tegra210-emc.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2015-2020, NVIDIA CORPORATION. All rights reserved.
8 #include <linux/clk-provider.h>
57 value = readl_relaxed(emc->regs + CLK_SOURCE_EMC); in tegra210_clk_emc_get_parent()
70 * CCF assumes that neither the parent nor its rate will change during in tegra210_clk_emc_recalc_rate()
71 * ->set_rate(), so the parent rate passed in here was cached from the in tegra210_clk_emc_recalc_rate()
72 * parent before the ->set_rate() call. in tegra210_clk_emc_recalc_rate()
75 * the parent and/or parent rate have changed as part of the EMC rate in tegra210_clk_emc_recalc_rate()
76 * change sequence. Fix this by overriding the parent clock with what in tegra210_clk_emc_recalc_rate()
77 * we know to be the correct value after the rate change. in tegra210_clk_emc_recalc_rate()
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| H A D | clk-tegra124-emc.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/clk/tegra/clk-emc.c
11 #include <linux/clk-provider.h>
48 * When we change the timing to a timing with a parent that has the same
49 * clock source as the current parent, we must first change to a backup
66 unsigned long rate, parent_rate; member
68 struct clk *parent; member
100 * CCF wrongly assumes that the parent won't change during set_rate, in emc_recalc_rate()
101 * so get the parent rate explicitly. in emc_recalc_rate()
105 val = readl(tegra->clk_regs + CLK_SOURCE_EMC); in emc_recalc_rate()
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| /linux/tools/testing/selftests/drivers/net/netdevsim/ |
| H A D | devlink.sh | 2 # SPDX-License-Identifier: GPL-2.0
22 "$@" | grep -q $DL_HANDLE
34 DUMMYFILE=$(find /lib/firmware -type f -printf '%P\n' | head -1)
37 if [ -z "$DUMMYFILE" ]
82 cmd_jq "devlink dev param show $DL_HANDLE name $name -j" \
91 devlink dev param set $DL_HANDLE name $name cmode driverinit value $value
123 check_err $? "Failed to set max_macs param value"
125 check_err $? "Failed to set test1 param value"
127 check_value max_macs post-set 16 32
128 check_value test1 post-set false Y
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| /linux/drivers/clk/zynqmp/ |
| H A D | divider.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2019 Xilinx
11 #include <linux/clk-provider.h>
13 #include "clk-zynqmp.h"
19 * prepare - clk_prepare only ensures that parents are prepared
20 * enable - clk_enable only ensures that parents are enabled
21 * rate - rate is adjustable. clk->rate = ceiling(parent->rate / divisor)
22 * parent - fixed parent. No clk_set_parent support
28 #define CLK_FRAC BIT(13) /* has a fractional parent */
29 #define CUSTOM_FLAG_CLK_FRAC BIT(0) /* has a fractional parent in custom type flag */
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| H A D | pll.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2018 Xilinx
9 #include <linux/clk-provider.h>
11 #include "clk-zynqmp.h"
14 * struct zynqmp_pll - PLL clock
15 * @hw: Handle between common and hardware-specific interfaces
44 * zynqmp_pll_get_mode() - Get mode of PLL
45 * @hw: Handle between common and hardware-specific interfaces
52 u32 clk_id = clk->clk_id; in zynqmp_pll_get_mode()
68 * zynqmp_pll_set_mode() - Set the PLL mode
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| /linux/drivers/clk/sunxi/ |
| H A D | clk-factors.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Adjustable factor-based clock implementation
8 #include <linux/clk-provider.h>
16 #include "clk-factors.h"
19 * DOC: basic adjustable factor-based clock
22 * prepare - clk_prepare only ensures that parents are prepared
23 * enable - clk_enable only ensures that parents are enabled
24 * rate - rate is adjustable.
25 * clk->rate = (parent->rate * N * (K + 1) >> P) / (M + 1)
26 * parent - fixed parent. No clk_set_parent support
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| H A D | clk-sun9i-cpus.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2015 Chen-Yu Tsai
5 * Chen-Yu Tsai <wens@csie.org>
12 #include <linux/clk-provider.h>
53 unsigned long rate; in sun9i_a80_cpus_clk_recalc_rate() local
57 reg = readl(cpus->reg); in sun9i_a80_cpus_clk_recalc_rate()
59 /* apply pre-divider first if parent is pll4 */ in sun9i_a80_cpus_clk_recalc_rate()
64 rate = parent_rate / (SUN9I_CPUS_DIV_GET(reg) + 1); in sun9i_a80_cpus_clk_recalc_rate()
66 return rate; in sun9i_a80_cpus_clk_recalc_rate()
69 static long sun9i_a80_cpus_clk_round(unsigned long rate, u8 *divp, u8 *pre_divp, in sun9i_a80_cpus_clk_round() argument
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| /linux/Documentation/networking/devlink/ |
| H A D | ice.rst | 1 .. SPDX-License-Identifier: GPL-2.0
13 .. list-table:: Generic parameters implemented
16 * - Name
17 - Mode
18 - Notes
19 * - ``enable_roce``
20 - runtime
21 - mutually exclusive with ``enable_iwarp``
22 * - ``enable_iwarp``
23 - runtime
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| H A D | devlink-port.rst | 1 .. SPDX-License-Identifier: GPL-2.0
9 ``devlink-port`` is a port that exists on the device. It has a logically
19 .. list-table:: List of devlink port flavours
22 * - Flavour
23 - Description
24 * - ``DEVLINK_PORT_FLAVOUR_PHYSICAL``
25 - Any kind of physical port. This can be an eswitch physical port or any
27 * - ``DEVLINK_PORT_FLAVOUR_DSA``
28 - This indicates a DSA interconnect port.
29 * - ``DEVLINK_PORT_FLAVOUR_CPU``
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| /linux/drivers/clk/ |
| H A D | clk.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
4 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
6 * Standard functionality for the common clock API. See Documentation/driver-api/clk.rst
9 #include <linux/clk/clk-conf.h>
12 #include <linux/clk-provider.h>
74 struct clk_core *parent; member
78 unsigned long rate; member
123 if (!core->rpm_enabled) in clk_pm_runtime_get()
126 return pm_runtime_resume_and_get(core->dev); in clk_pm_runtime_get()
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| /linux/drivers/clk/at91/ |
| H A D | clk-generated.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Based on clk-programmable & clk-peripheral drivers by Boris BREZILLON.
10 #include <linux/clk-provider.h>
43 spin_lock_irqsave(gck->lock, flags); in clk_generated_set()
44 regmap_write(gck->regmap, gck->layout->offset, in clk_generated_set()
45 (gck->id & gck->layout->pid_mask)); in clk_generated_set()
46 regmap_update_bits(gck->regmap, gck->layout->offset, in clk_generated_set()
47 AT91_PMC_PCR_GCKDIV_MASK | gck->layout->gckcss_mask | in clk_generated_set()
48 gck->layout->cmd | enable, in clk_generated_set()
49 field_prep(gck->layout->gckcss_mask, gck->parent_id) | in clk_generated_set()
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| /linux/drivers/clk/bcm/ |
| H A D | clk-kona.c | 1 // SPDX-License-Identifier: GPL-2.0-only
7 #include "clk-kona.h"
12 #include <linux/clk-provider.h>
28 /* Produces a mask of set bits covering a range of a 32-bit value */
31 return ((1 << width) - 1) << shift; in bitfield_mask()
53 return (u64)reg_div + ((u64)1 << div->u.s.frac_width); in scaled_div_value()
61 return (u64)div->u.fixed; in scaled_div_min()
72 return (u64)div->u.fixed; in scaled_div_max()
74 reg_div = ((u32)1 << div->u.s.width) - 1; in scaled_div_max()
89 return (u32)(scaled_div - ((u64)1 << div->u.s.frac_width)); in divider()
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| /linux/tools/testing/selftests/tc-testing/tc-tests/infra/ |
| H A D | qdiscs.json | 12 "$IP link set dev $DUMMY up || true",
15 "$TC filter add dev $DUMMY parent 1: basic classid 1:1",
16 "$TC class add dev $DUMMY parent 1: classid 1:1 drr",
17 "$TC qdisc add dev $DUMMY parent 1:1 handle ffff: drr",
18 "$TC filter add dev $DUMMY parent ffff: basic classid ffff:1",
19 "$TC class add dev $DUMMY parent ffff: classid ffff:1 drr",
20 "$TC qdisc add dev $DUMMY parent ffff:1 netem delay 1s",
21 "ping -c1 -W0.01 -I $DUMMY 10.10.10.1 || true",
23 "$TC class add dev $DUMMY parent ffff: classid ffff:1 drr"
25 "cmdUnderTest": "ping -c1 -W0.01 -I $DUMMY 10.10.10.1",
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| /linux/drivers/clk/sunxi-ng/ |
| H A D | ccu_mp.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
7 #include <linux/clk-provider.h>
20 static unsigned long ccu_mp_find_best(unsigned long parent, unsigned long rate, in ccu_mp_find_best() argument
31 unsigned long tmp_rate = parent / _p / _m; in ccu_mp_find_best()
33 if (tmp_rate > rate) in ccu_mp_find_best()
36 if ((rate - tmp_rate) < (rate - best_rate)) { in ccu_mp_find_best()
51 unsigned long *parent, in ccu_mp_find_best_with_parent_adj() argument
52 unsigned long rate, in ccu_mp_find_best_with_parent_adj() argument
63 parent_rate_saved = *parent; in ccu_mp_find_best_with_parent_adj()
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| H A D | ccu_phase.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
7 #include <linux/clk-provider.h>
16 struct clk_hw *parent, *grandparent; in ccu_phase_get_phase() local
22 reg = readl(phase->common.base + phase->common.reg); in ccu_phase_get_phase()
23 delay = (reg >> phase->shift); in ccu_phase_get_phase()
24 delay &= (1 << phase->width) - 1; in ccu_phase_get_phase()
29 /* Get our parent clock, it's the one that can adjust its rate */ in ccu_phase_get_phase()
30 parent = clk_hw_get_parent(hw); in ccu_phase_get_phase()
31 if (!parent) in ccu_phase_get_phase()
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| /linux/Documentation/devicetree/bindings/clock/ti/ |
| H A D | ti,mux-clock.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/clock/ti/ti,mux-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tero Kristo <kristo@kernel.org>
13 This clock assumes a register-mapped multiplexer with multiple inpt clock
15 not gate or adjust the parent rate via a divider or multiplier.
24 register value selected parent clock
31 "index-starts-at-one" modified the scheme as follows:
33 register value selected clock parent
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| /linux/drivers/devfreq/ |
| H A D | imx8m-ddrc.c | 1 // SPDX-License-Identifier: GPL-2.0
13 #include <linux/clk-provider.h>
14 #include <linux/arm-smccc.h>
27 unsigned long rate; member
40 * +----------+ |\ +------+
41 * | dram_pll |-------|M| dram_core | |
42 * +----------+ |U|---------->| D |
43 * /--|X| | D |
46 * +---------+ | |
48 * +---------+ | |
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| /linux/arch/mips/alchemy/common/ |
| H A D | clock.c | 1 // SPDX-License-Identifier: GPL-2.0
8 * - Root source, usually 12MHz supplied by an external crystal
9 * - 3 PLLs which generate multiples of root rate [AUX, CPU, AUX2]
12 * - 6 clock dividers with:
18 * - up to 6 "internal" (fixed) consumers which:
24 * - sysbus clock: CPU core clock (CPUPLL) divided by 2, 3 or 4.
25 * depends on board design and should be set by bootloader, read-only.
26 * - peripheral clock: half the rate of sysbus clock, source for a lot
27 * of peripheral blocks, read-only.
28 * - memory clock: clk rate to main memory chips, depends on board
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| /linux/drivers/sh/clk/ |
| H A D | core.c | 4 * Copyright (C) 2005 - 2010 Paul Mundt
8 * Copyright (C) 2004 - 2008 Nokia Corporation
49 clk->nr_freqs = nr_freqs; in clk_rate_table_build()
55 if (src_table->divisors && i < src_table->nr_divisors) in clk_rate_table_build()
56 div = src_table->divisors[i]; in clk_rate_table_build()
58 if (src_table->multipliers && i < src_table->nr_multipliers) in clk_rate_table_build()
59 mult = src_table->multipliers[i]; in clk_rate_table_build()
64 freq = clk->parent->rate * mult / div; in clk_rate_table_build()
78 unsigned long rate; member
85 for (pos = r->min, freq = r->func(pos, r); \
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| /linux/drivers/clk/versatile/ |
| H A D | clk-icst.c | 1 // SPDX-License-Identifier: GPL-2.0-only
7 * Copyright (C) 2012-2015 Linus Walleij
17 #include <linux/clk-provider.h>
23 #include "clk-icst.h"
37 * struct clk_icst - ICST VCO clock wrapper
43 * @rate: current rate
52 unsigned long rate; member
59 * vco_get() - get ICST VCO settings from a certain ICST
68 ret = regmap_read(icst->map, icst->vcoreg_off, &val); in vco_get()
77 * "Integrator CM926EJ-S, CM946E-S, CM966E-S, CM1026EJ-S and in vco_get()
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| /linux/drivers/clk/keystone/ |
| H A D | sci-clk.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2015-2016 Texas Instruments Incorporated - https://www.ti.com/
6 * Tero Kristo <t-kristo@ti.com>
8 #include <linux/clk-provider.h>
24 * struct sci_clk_provider - TI SCI clock provider representation
40 * struct sci_clk - TI SCI clock representation
48 * @cached_req: Cached requested freq for determine rate calls
49 * @cached_res: Cached result freq for determine rate calls
66 * sci_clk_prepare - Prepare (enable) a TI SCI clock
74 bool enable_ssc = clk->flags & SCI_CLK_SSC_ENABLE; in sci_clk_prepare()
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| /linux/drivers/clk/mvebu/ |
| H A D | dove-divider.c | 1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
15 #include "dove-divider.h"
56 val = readl_relaxed(dc->base + DIV_CTRL0); in dove_get_divider()
57 val >>= dc->div_bit_start; in dove_get_divider()
59 divider = val & ~(~0 << dc->div_bit_size); in dove_get_divider()
61 if (dc->divider_table) in dove_get_divider()
62 divider = dc->divider_table[divider]; in dove_get_divider()
67 static int dove_calc_divider(const struct dove_clk *dc, unsigned long rate, in dove_calc_divider() argument
68 unsigned long parent_rate, bool set) in dove_calc_divider() argument
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