1 // SPDX-License-Identifier: GPL-2.0-or-later
4  * Maxime Ripard <maxime.ripard@free-electrons.com>
7 #include <linux/clk-provider.h>
13 static unsigned long ccu_mp_find_best(unsigned long parent, unsigned long rate,  in ccu_mp_find_best()  argument
23 			unsigned long tmp_rate = parent / _p / _m;  in ccu_mp_find_best()
25 			if (tmp_rate > rate)  in ccu_mp_find_best()
28 			if ((rate - tmp_rate) < (rate - best_rate)) {  in ccu_mp_find_best()
43 						      unsigned long *parent,  in ccu_mp_find_best_with_parent_adj()  argument
44 						      unsigned long rate,  in ccu_mp_find_best_with_parent_adj()  argument
54 	parent_rate_saved = *parent;  in ccu_mp_find_best_with_parent_adj()
58 	 * unsigned long in rate * m * p below  in ccu_mp_find_best_with_parent_adj()
61 	maxdiv = min(ULONG_MAX / rate, maxdiv);  in ccu_mp_find_best_with_parent_adj()
70 			if (rate * div == parent_rate_saved) {  in ccu_mp_find_best_with_parent_adj()
73 				 * rate can be divided from parent clock without  in ccu_mp_find_best_with_parent_adj()
74 				 * needing to change parent rate, so return the  in ccu_mp_find_best_with_parent_adj()
77 				*parent = parent_rate_saved;  in ccu_mp_find_best_with_parent_adj()
78 				return rate;  in ccu_mp_find_best_with_parent_adj()
81 			parent_rate = clk_hw_round_rate(hw, rate * div);  in ccu_mp_find_best_with_parent_adj()
84 			if (now <= rate && now > best_rate) {  in ccu_mp_find_best_with_parent_adj()
86 				*parent = parent_rate;  in ccu_mp_find_best_with_parent_adj()
88 				if (now == rate)  in ccu_mp_find_best_with_parent_adj()
89 					return rate;  in ccu_mp_find_best_with_parent_adj()
100 				       unsigned long rate,  in ccu_mp_round_rate()  argument
107 	if (cmp->common.features & CCU_FEATURE_FIXED_POSTDIV)  in ccu_mp_round_rate()
108 		rate *= cmp->fixed_post_div;  in ccu_mp_round_rate()
110 	max_m = cmp->m.max ?: 1 << cmp->m.width;  in ccu_mp_round_rate()
111 	max_p = cmp->p.max ?: 1 << ((1 << cmp->p.width) - 1);  in ccu_mp_round_rate()
113 	if (!clk_hw_can_set_rate_parent(&cmp->common.hw)) {  in ccu_mp_round_rate()
114 		rate = ccu_mp_find_best(*parent_rate, rate, max_m, max_p, &m, &p);  in ccu_mp_round_rate()
116 		rate = ccu_mp_find_best_with_parent_adj(hw, parent_rate, rate,  in ccu_mp_round_rate()
120 	if (cmp->common.features & CCU_FEATURE_FIXED_POSTDIV)  in ccu_mp_round_rate()
121 		rate /= cmp->fixed_post_div;  in ccu_mp_round_rate()
123 	return rate;  in ccu_mp_round_rate()
130 	return ccu_gate_helper_disable(&cmp->common, cmp->enable);  in ccu_mp_disable()
137 	return ccu_gate_helper_enable(&cmp->common, cmp->enable);  in ccu_mp_enable()
144 	return ccu_gate_helper_is_enabled(&cmp->common, cmp->enable);  in ccu_mp_is_enabled()
151 	unsigned long rate;  in ccu_mp_recalc_rate()  local
155 	/* Adjust parent_rate according to pre-dividers */  in ccu_mp_recalc_rate()
156 	parent_rate = ccu_mux_helper_apply_prediv(&cmp->common, &cmp->mux, -1,  in ccu_mp_recalc_rate()
159 	reg = readl(cmp->common.base + cmp->common.reg);  in ccu_mp_recalc_rate()
161 	m = reg >> cmp->m.shift;  in ccu_mp_recalc_rate()
162 	m &= (1 << cmp->m.width) - 1;  in ccu_mp_recalc_rate()
163 	m += cmp->m.offset;  in ccu_mp_recalc_rate()
167 	p = reg >> cmp->p.shift;  in ccu_mp_recalc_rate()
168 	p &= (1 << cmp->p.width) - 1;  in ccu_mp_recalc_rate()
170 	rate = (parent_rate >> p) / m;  in ccu_mp_recalc_rate()
171 	if (cmp->common.features & CCU_FEATURE_FIXED_POSTDIV)  in ccu_mp_recalc_rate()
172 		rate /= cmp->fixed_post_div;  in ccu_mp_recalc_rate()
174 	return rate;  in ccu_mp_recalc_rate()
182 	return ccu_mux_helper_determine_rate(&cmp->common, &cmp->mux,  in ccu_mp_determine_rate()
186 static int ccu_mp_set_rate(struct clk_hw *hw, unsigned long rate,  in ccu_mp_set_rate()  argument
195 	/* Adjust parent_rate according to pre-dividers */  in ccu_mp_set_rate()
196 	parent_rate = ccu_mux_helper_apply_prediv(&cmp->common, &cmp->mux, -1,  in ccu_mp_set_rate()
199 	max_m = cmp->m.max ?: 1 << cmp->m.width;  in ccu_mp_set_rate()
200 	max_p = cmp->p.max ?: 1 << ((1 << cmp->p.width) - 1);  in ccu_mp_set_rate()
202 	/* Adjust target rate according to post-dividers */  in ccu_mp_set_rate()
203 	if (cmp->common.features & CCU_FEATURE_FIXED_POSTDIV)  in ccu_mp_set_rate()
204 		rate = rate * cmp->fixed_post_div;  in ccu_mp_set_rate()
206 	ccu_mp_find_best(parent_rate, rate, max_m, max_p, &m, &p);  in ccu_mp_set_rate()
208 	spin_lock_irqsave(cmp->common.lock, flags);  in ccu_mp_set_rate()
210 	reg = readl(cmp->common.base + cmp->common.reg);  in ccu_mp_set_rate()
211 	reg &= ~GENMASK(cmp->m.width + cmp->m.shift - 1, cmp->m.shift);  in ccu_mp_set_rate()
212 	reg &= ~GENMASK(cmp->p.width + cmp->p.shift - 1, cmp->p.shift);  in ccu_mp_set_rate()
213 	reg |= (m - cmp->m.offset) << cmp->m.shift;  in ccu_mp_set_rate()
214 	reg |= ilog2(p) << cmp->p.shift;  in ccu_mp_set_rate()
216 	writel(reg, cmp->common.base + cmp->common.reg);  in ccu_mp_set_rate()
218 	spin_unlock_irqrestore(cmp->common.lock, flags);  in ccu_mp_set_rate()
227 	return ccu_mux_helper_get_parent(&cmp->common, &cmp->mux);  in ccu_mp_get_parent()
234 	return ccu_mux_helper_set_parent(&cmp->common, &cmp->mux, index);  in ccu_mp_set_parent()
256  * and set the timing mode on supported SoCs.
260  * mode is active, the clock output rate is halved. This new class
263  * if the new timing mode bit is set, to account for the post
265  * are halved if the mode bit is set.
271 	unsigned long rate = ccu_mp_recalc_rate(hw, parent_rate);  in ccu_mp_mmc_recalc_rate()  local
273 	u32 val = readl(cm->base + cm->reg);  in ccu_mp_mmc_recalc_rate()
276 		return rate / 2;  in ccu_mp_mmc_recalc_rate()
277 	return rate;  in ccu_mp_mmc_recalc_rate()
284 	u32 val = readl(cm->base + cm->reg);  in ccu_mp_mmc_determine_rate()
287 	/* adjust the requested clock rate */  in ccu_mp_mmc_determine_rate()
289 		req->rate *= 2;  in ccu_mp_mmc_determine_rate()
290 		req->min_rate *= 2;  in ccu_mp_mmc_determine_rate()
291 		req->max_rate *= 2;  in ccu_mp_mmc_determine_rate()
296 	/* re-adjust the requested clock rate back */  in ccu_mp_mmc_determine_rate()
298 		req->rate /= 2;  in ccu_mp_mmc_determine_rate()
299 		req->min_rate /= 2;  in ccu_mp_mmc_determine_rate()
300 		req->max_rate /= 2;  in ccu_mp_mmc_determine_rate()
306 static int ccu_mp_mmc_set_rate(struct clk_hw *hw, unsigned long rate,  in ccu_mp_mmc_set_rate()  argument
310 	u32 val = readl(cm->base + cm->reg);  in ccu_mp_mmc_set_rate()
313 		rate *= 2;  in ccu_mp_mmc_set_rate()
315 	return ccu_mp_set_rate(hw, rate, parent_rate);  in ccu_mp_mmc_set_rate()