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/freebsd/sys/dev/qcom_clk/
H A Dqcom_clk_rcg2.c1 /*-
52 ((sc)->cmd_rcgr + (sc)->cfg_offset + QCOM_CLK_RCG2_CFG_REG)
54 ((sc)->cmd_rcgr + QCOM_CLK_RCG2_CMD_REG)
56 ((sc)->cmd_rcgr + (sc)->cfg_offset + QCOM_CLK_RCG2_M_REG)
58 ((sc)->cmd_rcgr + (sc)->cfg_offset + QCOM_CLK_RCG2_N_REG)
60 ((sc)->cmd_rcgr + (sc)->cfg_offset + QCOM_CLK_RCG2_D_REG)
88 CLKDEV_READ_4(clknode_get_device(sc->clknode), in qcom_clk_rcg2_update_config_locked()
91 CLKDEV_WRITE_4(clknode_get_device(sc->clknode), in qcom_clk_rcg2_update_config_locked()
99 CLKDEV_READ_4(clknode_get_device(sc->clknode), in qcom_clk_rcg2_update_config_locked()
108 CLKDEV_READ_4(clknode_get_device(sc->clknode), in qcom_clk_rcg2_update_config_locked()
[all …]
/freebsd/sys/contrib/device-tree/Bindings/clock/ti/
H A Dti,mux-clock.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/clock/ti/ti,mux-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tero Kristo <kristo@kernel.org>
13 This clock assumes a register-mapped multiplexer with multiple inpt clock
15 not gate or adjust the parent rate via a divider or multiplier.
24 register value selected parent clock
31 "index-starts-at-one" modified the scheme as follows:
33 register value selected clock parent
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H A Ddivider.txt4 register-mapped adjustable clock rate divider that does not gate and has
5 only one input clock or parent. By default the value programmed into
15 ti,index-starts-at-one - valid divisor values start at 1, not the default
22 ti,index-power-of-two - valid divisor values are powers of two. E.g:
39 Any zero value in this array means the corresponding bit-value is invalid
50 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
54 - compatible : shall be "ti,divider-clock" or "ti,composite-divider-clock".
55 - #clock-cells : from common clock binding; shall be set to 0.
56 - clocks : link to phandle of parent clock
57 - reg : offset for register controlling adjustable divider
[all …]
H A Dmux.txt4 register-mapped multiplexer with multiple input clock signals or
6 gate or adjust the parent rate via a divider or multiplier.
15 register value selected parent clock
22 "index-starts-at-one" modified the scheme as follows:
24 register value selected clock parent
34 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
37 - compatible : shall be "ti,mux-clock" or "ti,composite-mux-clock".
38 - #clock-cells : from common clock binding; shall be set to 0.
39 - clocks : link phandles of parent clocks
40 - reg : register offset for register controlling adjustable mux
[all …]
H A Dfixed-factor-clock.txt1 Binding for TI fixed factor rate clock sources.
6 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
10 - compatible : shall be "ti,fixed-factor-clock".
11 - #clock-cells : from common clock binding; shall be set to 0.
12 - ti,clock-div: fixed divider.
13 - ti,clock-mult: fixed multiplier.
14 - clocks: parent clock.
17 - clock-output-names : from common clock binding.
18 - ti,autoidle-shift: bit shift of the autoidle enable bit for the clock,
20 - reg: offset for the autoidle register of this clock, see [2]
[all …]
H A Dti,fixed-factor-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/ti/ti,fixed-factor-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI fixed factor rate clock sources
10 - Tero Kristo <kristo@kernel.org>
11 - Sukrut Bellary <sbellary@baylibre.com>
14 This consists of a divider and a multiplier used to generate a fixed rate
18 - $ref: ti,autoidle.yaml#
22 const: ti,fixed-factor-clock
[all …]
H A Dti,divider-clock.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/clock/ti/ti,divider-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tero Kristo <kristo@kernel.org>
13 This clock It assumes a register-mapped adjustable clock rate divider
14 that does not gate and has only one input clock or parent. By default the
25 ti,index-starts-at-one - valid divisor values start at 1, not the default
32 ti,index-power-of-two - valid divisor values are powers of two. E.g:
49 Any zero value in this array means the corresponding bit-value is invalid
[all …]
H A Ddpll.txt4 register-mapped DPLL with usually two selectable input clocks
9 sub-types, which effectively result in slightly different setup
12 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
15 - compatible : shall be one of:
16 "ti,omap3-dpll-clock",
17 "ti,omap3-dpll-core-clock",
18 "ti,omap3-dpll-per-clock",
19 "ti,omap3-dpll-per-j-type-clock",
20 "ti,omap4-dpll-clock",
21 "ti,omap4-dpll-x2-clock",
[all …]
/freebsd/sys/dev/cpufreq/
H A Dichss.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2004-2005 Nate Lawson (SDG)
47 * The SpeedStep ICH feature is a chipset-initiated voltage and frequency
49 * the newer Pentium-M SpeedStep feature. It offers only two levels of
51 * SMM code during the power-on process (i.e., choose a lower level if the
57 int bm_rid; /* Bus-mastering control (PM2REG). */
93 static void ichss_identify(driver_t *driver, device_t parent);
99 static int ichss_set(device_t dev, const struct cf_setting *set);
100 static int ichss_get(device_t dev, struct cf_setting *set);
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/freebsd/sys/dev/ice/
H A Dice_sched.c1 /* SPDX-License-Identifier: BSD-3-Clause */
35 * ice_sched_add_root_node - Insert the Tx scheduler root node in SW DB
52 hw = pi->hw; in ice_sched_add_root_node()
58 root->children = (struct ice_sched_node **) in ice_sched_add_root_node()
59 ice_calloc(hw, hw->max_children[0], sizeof(*root->children)); in ice_sched_add_root_node()
60 if (!root->childre in ice_sched_add_root_node()
183 struct ice_sched_node *parent; ice_sched_add_node() local
264 ice_sched_remove_elems(struct ice_hw * hw,struct ice_sched_node * parent,u16 num_nodes,u32 * node_teids) ice_sched_remove_elems() argument
302 ice_sched_get_first_node(struct ice_port_info * pi,struct ice_sched_node * parent,u8 layer) ice_sched_get_first_node() argument
337 struct ice_sched_node *parent; ice_free_sched_node() local
985 ice_sched_add_elems(struct ice_port_info * pi,struct ice_sched_node * tc_node,struct ice_sched_node * parent,u8 layer,u16 num_nodes,u16 * num_nodes_added,u32 * first_node_teid,struct ice_sched_node ** prealloc_nodes) ice_sched_add_elems() argument
1090 ice_sched_add_nodes_to_hw_layer(struct ice_port_info * pi,struct ice_sched_node * tc_node,struct ice_sched_node * parent,u8 layer,u16 num_nodes,u32 * first_node_teid,u16 * num_nodes_added) ice_sched_add_nodes_to_hw_layer() argument
1134 ice_sched_add_nodes_to_layer(struct ice_port_info * pi,struct ice_sched_node * tc_node,struct ice_sched_node * parent,u8 layer,u16 num_nodes,u32 * first_node_teid,u16 * num_nodes_added) ice_sched_add_nodes_to_layer() argument
1786 struct ice_sched_node *parent, *node; ice_sched_add_vsi_child_nodes() local
1890 struct ice_sched_node *parent = tc_node; ice_sched_add_vsi_support_nodes() local
2356 struct ice_sched_node *parent; ice_sched_get_free_vsi_parent() local
2410 ice_sched_move_nodes(struct ice_port_info * pi,struct ice_sched_node * parent,u16 num_items,u32 * list) ice_sched_move_nodes() argument
2476 struct ice_sched_node *vsi_node, *agg_node, *tc_node, *parent; ice_sched_move_vsi_to_agg() local
2640 struct ice_sched_node *parent = agg_node->parent; ice_sched_rm_agg_cfg() local
2725 struct ice_sched_node *parent, *agg_node, *tc_node; ice_sched_add_agg_cfg() local
[all...]
/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dnvidia,tegra124-car.txt4 Documentation/devicetree/bindings/clock/clock-bindings.txt
10 - compatible : Should be "nvidia,tegra124-car" or "nvidia,tegra132-car"
11 - reg : Should contain CAR registers location and length
12 - clocks : Should contain phandle and clock specifiers for two clocks:
13 the 32 KHz "32k_in", and the board-specific oscillator "osc".
14 - #clock-cells : Should be 1.
17 <dt-bindings/clock/tegra124-car-common.h> (which covers IDs common
18 to Tegra124 and Tegra132) and <dt-bindings/clock/tegra124-car.h>
19 (for Tegra124-specific clocks).
20 - #reset-cells : Should be 1.
[all …]
H A Dnvidia,tegra124-car.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/nvidia,tegra124-car.yaml#
5 $schema: http://devicetree.org/meta-schema
[all...]
/freebsd/sys/contrib/device-tree/Bindings/regulator/
H A Dregulator-max77620.txt3 Device has multiple DCDC(sd[0-3] and LDOs(ldo[0-8]). The input supply
4 of these regulators are defined under parent device node.
6 sub-node "regulators" which is child node of device node.
11 Following are properties of parent node related to regulators.
14 -----
[all...]
/freebsd/sys/arm/broadcom/bcm2835/
H A Dbcm2835_cpufreq.c1 /*-
2 * Copyright (C) 2013-2015 Daisuke Aoyama <aoyama@peach.ne.jp>
71 #define MIN_OVER_VOLTAGE -16
73 #define MSG_ERROR -999999999
85 /* ARM->VC mailbox property semaphore */
115 { "broadcom,bcm2835-vc", 1 },
116 { "broadcom,bcm2708-vc", 1 },
154 int rate; in bcm2835_cpufreq_get_clock_rate() local
158 * Get clock rate in bcm2835_cpufreq_get_clock_rate()
168 * u32: rate (in Hz) in bcm2835_cpufreq_get_clock_rate()
[all …]
/freebsd/sys/contrib/device-tree/Bindings/phy/
H A Dphy-mtk-tphy.txt1 MediaTek T-PHY binding
2 --------------------------
4 T-phy controller supports physical layer functionality for a number of
7 Required properties (controller (parent) node):
8 - compatible : should be one of
9 "mediatek,generic-tphy-v1"
10 "mediatek,generic-tphy-v2"
11 "mediatek,mt2701-u3phy" (deprecated)
12 "mediatek,mt2712-u3phy" (deprecated)
13 "mediatek,mt8173-u3phy";
[all …]
/freebsd/sys/dev/acpica/
H A Dacpi_perf.c1 /*-
2 * Copyright (c) 2003-2005 Nate Lawson (SDG)
65 /* Offsets in struct cf_setting array for storing driver-specific values. */
74 struct resource *perf_ctrl; /* Set new performance state. */
83 int info_only; /* Can we set new states? */
95 static void acpi_perf_identify(driver_t *driver, device_t parent);
101 struct cf_setting *set);
107 static int acpi_px_set(device_t dev, const struct cf_setting *set);
108 static int acpi_px_get(device_t dev, struct cf_setting *set);
139 acpi_perf_identify(driver_t *driver, device_t parent) in acpi_perf_identify() argument
[all …]
/freebsd/sys/contrib/device-tree/Bindings/sound/
H A Dcs35l33.txt5 - compatible : "cirrus,cs35l33"
7 - reg : the I2C address of the device for I2C
9 - VA-supply, VP-supply : power supplies for the device,
15 - reset-gpios : gpio used to reset the amplifier
17 - interrupts : IRQ line info CS35L33.
18 (See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
21 - cirrus,boost-ctl : Booster voltage use to supply the amp. If the value is
26 - cirrus,ramp-rate : On power up, it affects the time from when the power
27 up sequence begins to the time the audio reaches a full-scale output.
28 On power down, it affects the time from when the power-down sequence
[all …]
H A Dnuvoton,nau8821.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Seven Lee <wtli@nuvoton.com>
13 - $ref: dai-common.yaml#
25 nuvoton,jkdet-enable:
29 nuvoton,jkdet-pull-enable:
30 description: Enable JKDET pin pull. If set - pin pull enabled,
34 nuvoton,jkdet-pull-up:
35 description: Pull-up JKDET pin. If set then JKDET pin is pull up,
[all …]
/freebsd/sbin/ifconfig/
H A Difconfig.81 .\"-
2 .\" SPDX-License-Identifier: BSD-3-Clause
93 .Bl -tag -width indent
120 The format is specified as a comma-separated list of
141 .Bl -tag -width default
145 .Bl -tag -width default -compact
158 Adjust the display of link-level ethernet (MAC) addresses:
160 .Bl -tag -width default -compact
175 .Bl -tag -width default -compact
192 .Bl -tag -width default -compact
[all …]
/freebsd/sys/x86/cpufreq/
H A Dsmist.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
28 * This driver is based upon information found by examining speedstep-0.5
78 static void smist_identify(driver_t *driver, device_t parent);
84 static int smist_set(device_t dev, const struct cf_setting *set);
85 static int smist_get(device_t dev, struct cf_setting *set);
143 *sig = -1; in int15_gsic_call()
144 *smi_cmd = -1; in int15_gsic_call()
145 *command = -1; in int15_gsic_call()
146 *smi_data = -1; in int15_gsic_call()
[all …]
/freebsd/sys/arm64/nvidia/tegra210/
H A Dmax77620_regulators.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
43 #include <dt-bindings/mfd/max77620.h>
121 REG_RANGE_INIT(0, 64, 600000, 12500), /* 0.6V - 1.4V / 12.5mV */
125 REG_RANGE_INIT(0, 76, 600000, 12500), /* 0.6V - 1.55V / 12.5mV */
129 REG_RANGE_INIT(0, 255, 600000, 12500), /* 0.6V - 3.7875V / 12.5mV */
133 REG_RANGE_INIT(0, 63, 800000, 25000), /* 0.8V - 2.375V / 25mV */
137 REG_RANGE_INIT(0, 63, 800000, 12500), /* 0.8V - 1.5875V / 12.5mV */
141 REG_RANGE_INIT(0, 63, 800000, 50000), /* 0.8V - 3.95V / 50mV */
148 .supply_name = "in-sd0",
[all …]
/freebsd/sys/dev/clk/rockchip/
H A Drk_clk_armclk.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
88 READ4(clk, sc->muxdiv_offset, &val); in rk_clk_armclk_init()
91 idx = (val & sc->mux_mask) >> sc->mux_shift; in rk_clk_armclk_init()
106 dprintf("Set mux to %d\n", index); in rk_clk_armclk_set_mux()
108 val |= index << sc->mux_shift; in rk_clk_armclk_set_mux()
109 val |= sc->mux_mask << RK_ARMCLK_WRITE_MASK_SHIFT; in rk_clk_armclk_set_mux()
110 dprintf("Write: muxdiv_offset=%x, val=%x\n", sc->muxdiv_offset, val); in rk_clk_armclk_set_mux()
111 WRITE4(clk, sc->muxdiv_offset, val); in rk_clk_armclk_set_mux()
127 READ4(clk, sc->muxdiv_offset, &reg); in rk_clk_armclk_recalc()
[all …]
/freebsd/usr.sbin/sndctl/
H A Dsndctl.81 .\"-
2 .\" SPDX-License-Identifier: BSD-2-Clause
4 .\" Copyright (c) 2024-2025 The FreeBSD Foundation
44 utility is used to set and display sound card properties, using a
45 control-driven interface, in order to filter and/or set specific properties.
48 .Bl -tag -width "-f device"
65 .Bl -column xxxxxxxxxxxxxxx xxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxx -offset indent
74 .It bitperfect Ta Boolean Ta Read/Write Ta Bit-perfect mode enabled
75 .It autoconv Ta Boolean Ta Read/Write Ta Auto-conversions enabled
76 .It realtime Ta Boolean Ta Read/Write Ta Real-time mode enabled
[all …]
/freebsd/sbin/pfctl/
H A Dpfctl_altq.c55 #define is_sc_null(sc) (((sc) == NULL) || ((sc)->m1 == 0 && (sc)->m2 == 0))
135 memcpy(&altq->pa, a, sizeof(struct pf_altq)); in pfaltq_store()
136 memset(&altq->meta, 0, sizeof(altq->meta)); in pfaltq_store()
138 if (a->qname[0] == 0) { in pfaltq_store()
139 item.key = altq->pa.ifname; in pfaltq_store()
145 key_size = sizeof(a->ifname) + sizeof(a->qname); in pfaltq_store()
148 snprintf(item.key, key_size, "%s:%s", a->ifname, a->qname); in pfaltq_store()
153 item.key = altq->pa.qname; in pfaltq_store()
154 item.data = &altq->pa.qid; in pfaltq_store()
170 return (ret_item->data); in pfaltq_lookup()
[all …]
/freebsd/sys/kern/
H A Dkern_cpu.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2004-2007 Nate Lawson (SDG)
52 * attach this interface to allow users to get/set the CPU frequency.
114 struct cf_level *dup, struct cf_setting *set);
162 device_t parent; in cpufreq_attach() local
163 uint64_t rate; in cpufreq_attach() local
167 parent = device_get_parent(dev); in cpufreq_attach()
168 sc->dev = dev; in cpufreq_attach()
169 sysctl_ctx_init(&sc->sysctl_ctx); in cpufreq_attach()
[all …]

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