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/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Drenesas,intc-irqpin.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/renesas,intc-irqpin.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Geert Uytterhoeven <geert+renesas@glider.be>
15 - enum:
16 - renesas,intc-irqpin-r8a7740 # R-Mobile A1
17 - renesas,intc-irqpin-r8a7778 # R-Car M1A
18 - renesas,intc-irqpin-r8a7779 # R-Car H1
19 - renesas,intc-irqpin-sh73a0 # SH-Mobile AG5
[all …]
/linux/drivers/net/ethernet/aquantia/atlantic/hw_atl/
H A Dhw_atl_llh_internal.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright (C) 2014-2019 aQuantia Corporation
5 * Copyright (C) 2019-2020 Marvell International Ltd.
15 /* COM Temperature Sense Reset Bitfield Definitions */
21 /* COM Temperature Sense Power Down Bitfield Definitions */
27 /* COM Temperature Sense Ready Bitfield Definitions */
33 /* COM Temperature Sense Ready Latch High Bitfield Definitions */
39 /* COM Temperature Sense Data Out [B:0] Bitfield Definitions */
50 /* register address for bitfield rx dma good octet counter lsw [1f:0] */
52 /* register address for bitfield rx dma good packet counter lsw [1f:0] */
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/linux/drivers/irqchip/
H A Dirq-renesas-intc-irqpin.c1 // SPDX-License-Identifier: GPL-2.0
35 * SENSE is read-write 32-bit with 2-bits or 4-bits per IRQ (*)
36 * PRIO is read-write 32-bit with 4-bits per IRQ (**)
37 * SOURCE is read-only 32-bit or 8-bit with 1-bit per IRQ (***)
38 * MASK is write-only 32-bit or 8-bit with 1-bit per IRQ (***)
39 * CLEAR is write-only 32-bit or 8-bit with 1-bit per IRQ (***)
41 * (*) May be accessed by more than one driver instance - lock needed
42 * (**) Read-modify-write access by one driver instance - lock needed
43 * (***) Accessed by one driver instance only - no locking needed
50 int width; member
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/linux/drivers/clk/bcm/
H A Dclk-kona-setup.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include "clk-kona.h"
13 #define selector_clear_exists(sel) ((sel)->width = 0)
20 struct ccu_policy *ccu_policy = &ccu->policy; in ccu_data_offsets_valid()
23 limit = ccu->range - sizeof(u32); in ccu_data_offsets_valid()
26 if (ccu_policy->enable.offset > limit) { in ccu_data_offsets_valid()
29 ccu->name, ccu_policy->enable.offset, limit); in ccu_data_offsets_valid()
32 if (ccu_policy->control.offset > limit) { in ccu_data_offsets_valid()
35 ccu->name, ccu_policy->control.offset, limit); in ccu_data_offsets_valid()
45 struct peri_clk_data *peri = bcm_clk->u.peri; in clk_requires_trigger()
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H A Dclk-kona.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include "clk-kona.h"
12 #include <linux/clk-provider.h>
25 /* Bitfield operations */
27 /* Produces a mask of set bits covering a range of a 32-bit value */
28 static inline u32 bitfield_mask(u32 shift, u32 width) in bitfield_mask() argument
30 return ((1 << width) - 1) << shift; in bitfield_mask()
33 /* Extract the value of a bitfield found within a given register value */
34 static inline u32 bitfield_extract(u32 reg_val, u32 shift, u32 width) in bitfield_extract() argument
36 return (reg_val & bitfield_mask(shift, width)) >> shift; in bitfield_extract()
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/linux/drivers/gpu/drm/msm/registers/adreno/
H A Da2xx.xml1 <?xml version="1.0" encoding="UTF-8"?>
3 xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
4 xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
1028 <domain name="A2XX" width="32">
1031 <bitfield name="COLUMN" low="0" high="2" type="uint"/>
1032 <bitfield name="ROW" low="3" high="5" type="uint"/>
1033 <bitfield name="GUARD_BAND_MASK" low="6" high="8" type="uint"/>
1048 <!--
1051 it doesn't make sense, so I think offset 0x40 must be a different
1053 -->
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H A Da6xx.xml1 <?xml version="1.0" encoding="UTF-8"?>
3 xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
4 xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
9 <!--
12 - "cmd" - the register is used outside of renderpass and blits,
14 - "rp_blit" - the register is used inside renderpass or blits
21 -->
23 <!-- these might be same as a5xx -->
39 <value value="0x0c" name="FMT6_1_5_5_5_UNORM"/> <!-- read only -->
60 <value value="0x31" name="FMT6_8_8_8_X8_UNORM"/> <!-- samples 1 for alpha -->
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/linux/drivers/staging/media/tegra-video/
H A Dtegra20.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Tegra20-specific VI implementation
14 #include <linux/bitfield.h>
19 #include <linux/v4l2-mediabus.h>
26 /* This are just good-sense numbers. The actual min/max is not documented. */
32 /* --------------------------------------------------------------------------
147 /* --------------------------------------------------------------------------
153 writel(val, chan->vi->iomem + addr); in tegra20_vi_write()
164 unsigned int input_mbus_code = chan->fmtinfo->code; in tegra20_vi_get_input_formats()
193 u32 output_fourcc = chan->format.pixelformat; in tegra20_vi_get_output_formats()
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/linux/include/linux/ssb/
H A Dssb_regs.h1 /* SPDX-License-Identifier: GPL-2.0 */
33 #define SSB_MAX_NR_CORES ((SSB_ENUM_LIMIT - SSB_ENUM_BASE) / SSB_CORE_SIZE)
108 #define SSB_TMSHIGH_SERR 0x00000001 /* S-error */
144 #define SSB_IDLOW_CCW 0x000C0000 /* Cycle counter width */
168 * in two-byte quantities.
202 #define SSB_SPROM1_BINF_ANTBG 0x3000 /* Available B-PHY and G-PHY antennas */
204 #define SSB_SPROM1_BINF_ANTA 0xC000 /* Available A-PHY antennas */
218 #define SSB_SPROM1_MAXPWR_BG 0x00FF /* B-PHY and G-PHY (in dBm Q5.2) */
219 #define SSB_SPROM1_MAXPWR_A 0xFF00 /* A-PHY (in dBm Q5.2) */
225 #define SSB_SPROM1_ITSSI_BG 0x00FF /* B-PHY and G-PHY*/
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/linux/Documentation/ABI/testing/
H A Dsysfs-class-hwmon16 The contents of the label are free-form.
135 this voltage channel is being used for, and user-space
137 user-space.
145 When disabled the sensor read will return -ENODATA.
147 - 1: Enable
148 - 0: Disable
156 - 1: Failed
157 - 0: Ok
262 Only makes sense if the chip supports closed-loop fan speed
272 this fan channel is being used for, and user-space doesn't.
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/linux/drivers/gpu/drm/udl/
H A Dudl_modeset.c1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/bitfield.h>
120 * same actual count. This makes sense once you read above a couple of
127 while (actual_count--) { in udl_lfsr16()
151 u16 reg01 = mode->crtc_htotal - mode->crtc_hsync_start; in udl_set_display_mode()
152 u16 reg03 = reg01 + mode->crtc_hdisplay; in udl_set_display_mode()
153 u16 reg05 = mode->crtc_vtotal - mode->crtc_vsync_start; in udl_set_display_mode()
154 u16 reg07 = reg05 + mode->crtc_vdisplay; in udl_set_display_mode()
155 u16 reg09 = mode->crtc_htotal - 1; in udl_set_display_mode()
157 u16 reg0d = mode->crtc_hsync_end - mode->crtc_hsync_start + 1; in udl_set_display_mode()
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/linux/drivers/net/ethernet/cadence/
H A Dmacb.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2004-2006 Atmel Corporation
114 #define GEM_TX65CNT 0x011c /* 65-127 byte Frames TX counter */
115 #define GEM_TX128CNT 0x0120 /* 128-255 byte Frames TX counter */
116 #define GEM_TX256CNT 0x0124 /* 256-511 byte Frames TX counter */
117 #define GEM_TX512CNT 0x0128 /* 512-1023 byte Frames TX counter */
118 #define GEM_TX1024CNT 0x012c /* 1024-1518 byte Frames TX counter */
126 #define GEM_TXCSENSECNT 0x014c /* Carrier Sense Error Counter */
135 #define GEM_RX65CNT 0x016c /* 65-127 byte Frames RX Counter */
136 #define GEM_RX128CNT 0x0170 /* 128-255 byte Frames RX Counter */
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/linux/include/xen/interface/
H A Dxen.h1 /* SPDX-License-Identifier: MIT */
69 /* Architecture-specific hypercall definitions. */
83 * In the side comments, 'V.' denotes a per-VCPU VIRQ while 'G.' denotes a
84 * global VIRQ. The former can be bound once per VCPU and cannot be re-bound.
86 * allocated to VCPU0 but can subsequently be re-bound.
102 /* Architecture-specific VIRQ definitions. */
127 * x != 0 => PFD == x - 1
129 * Sub-commands: ptr[1:0] specifies the appropriate MMU_* command.
130 * -------------
138 * ptr[:2] -- Machine address of the page-table entry to modify.
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/linux/drivers/pwm/
H A Dpwm-meson.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
13 * Setting the duty cycle will disable and re-enable the PWM output.
19 * https://dl.khadas.com/Hardware/VIM2/Datasheet/S912_Datasheet_V0.220170314publicversion-Wesion.pdf
23 * https://dn.odroid.com/S922X/ODROID-N2/Datasheet/S922X_Public_Datasheet_V0.2.pdf
30 #include <linux/bitfield.h>
33 #include <linux/clk-provider.h>
123 struct meson_pwm_channel *channel = &meson->channels[pwm->hwpwm]; in meson_pwm_request()
127 err = clk_prepare_enable(channel->clk); in meson_pwm_request()
130 __clk_get_name(channel->clk), err); in meson_pwm_request()
140 struct meson_pwm_channel *channel = &meson->channels[pwm->hwpwm]; in meson_pwm_free()
[all …]
/linux/arch/arm/boot/dts/renesas/
H A Dr8a7778.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Car M1A (R8A77781) SoC
14 #include <dt-bindings/clock/r8a7778-clock.h>
15 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #include <dt-bindings/interrupt-controller/irq.h>
20 interrupt-parent = <&gic>;
21 #address-cells = <1>;
22 #size-cells = <1>;
25 #address-cells = <1>;
26 #size-cells = <0>;
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H A Dr8a7779.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Car H1 (R8A77790) SoC
9 #include <dt-bindings/clock/r8a7779-clock.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/power/r8a7779-sysc.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <1>;
18 #size-cells = <1>;
21 #address-cells = <1>;
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/linux/drivers/mmc/host/
H A Dcavium.c9 * Copyright (C) 2012-2017 Cavium Inc.
16 #include <linux/bitfield.h>
18 #include <linux/dma-direction.h>
19 #include <linux/dma-mapping.h>
23 #include <linux/mmc/slot-gpio.h>
46 * being used. However, non-MMC devices like SD use command and
128 cr = cvm_mmc_cr_types + (cmd->opcode & 0x3f); in cvm_mmc_get_cr_mods()
129 hardware_ctype = cr->ctype; in cvm_mmc_get_cr_mods()
130 hardware_rtype = cr->rtype; in cvm_mmc_get_cr_mods()
131 if (cmd->opcode == MMC_GEN_CMD) in cvm_mmc_get_cr_mods()
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/linux/drivers/media/i2c/
H A Dadv7511-v4l2.c1 // SPDX-License-Identifier: GPL-2.0-only
9 * This file is named adv7511-v4l2.c so it doesn't conflict with the Analog
22 #include <linux/v4l2-dv-timings.h>
23 #include <media/v4l2-device.h>
24 #include <media/v4l2-common.h>
25 #include <media/v4l2-ctrls.h>
26 #include <media/v4l2-dv-timings.h>
32 MODULE_PARM_DESC(debug, "debug level (0-2)");
94 /* Did we receive hotplug and rx-sense signals? */
147 return &container_of(ctrl->handler, struct adv7511_state, hdl)->sd; in to_sd()
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/linux/Documentation/gpu/
H A Dtodo.rst11 ----------
29 Subsystem-wide refactorings
33 ---------------------------------------------
45 --------------------------------------------------
53 non-converted driver. The "Atomic mode setting design overview" series [2]_
60 .. [1] https://blog.ffwll.ch/2014/11/atomic-modeset-support-for-kms-drivers.html
69 ---------------------------------------------------------
75 avoid confusion - the other helpers in that file are all deprecated legacy
83 ----------------------------------
88 - drm_plane_helper_funcs->atomic_check gets called for enabled or disabled
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/linux/include/uapi/linux/
H A Dvideodev2.h1 /* SPDX-License-Identifier: ((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) */
5 * Copyright (C) 1999-2012 the contributors
47 * All kernel-specific stuff were moved to media/v4l2-dev.h, so
66 #include <linux/v4l2-common.h>
67 #include <linux/v4l2-controls.h>
80 /* Four-character-code (FOURCC) */
98 buffer, top-bottom order */
99 V4L2_FIELD_SEQ_BT = 6, /* same as above + bottom-top order */
205 /* Obsolete pre-1998 SMPTE 240M HDTV standard, superseded by Rec 709 */
218 * NTSC 1953 colorspace. This only makes sense when dealing with
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/linux/drivers/net/phy/
H A Dmarvell.c1 // SPDX-License-Identifier: GPL-2.0+
33 #include <linux/bitfield.h>
188 /* RGMII to 1000BASE-X */
190 /* RGMII to 100BASE-FX */
390 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { in marvell_config_intr()
454 err = marvell_set_polarity(phydev, phydev->mdix_ctrl); in marvell_config_aneg()
469 if (phydev->autoneg != AUTONEG_ENABLE || changed) { in marvell_config_aneg()
519 * marvell,reg-init property stored in the of_node for the phydev.
521 * marvell,reg-init = <reg-page reg mask value>,...;
523 * There may be one or more sets of <reg-page reg mask value>:
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/linux/drivers/gpu/drm/bridge/
H A Dti-sn65dsi86.c1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/bitfield.h>
134 * struct ti_sn65dsi86 - Platform data for ti-sn65dsi86 driver.
135 * @bridge_aux: AUX-bus sub device for MIPI-to-eDP bridge functionality.
136 * @gpio_aux: AUX-bus sub device for GPIO controller functionality.
137 * @aux_aux: AUX-bus sub device for eDP AUX channel functionality.
138 * @pwm_aux: AUX-bus sub device for PWM controller functionality.
153 * @ln_polrs: Value for the 4-bit LN_POLRS field of SN_ENH_FRAME_REG.
159 * serves double-duty of keeping track of the direction and
165 * each other's read-modify-write.
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/linux/drivers/gpu/drm/radeon/
H A Dr300_reg.h95 /* State based - direct writes to registers trigger vertex
107 /* index size - when not set the indices are assumed to be 16 bit */
147 /* BEGIN: Vertex data assembly - lots of uncertainties */
207 * - always set up to produce at least two attributes:
209 * - INPUT_CNTL_0_COLOR and INPUT_CNTL_COLOR bits are always equal.
307 /* These seem to be per-pixel and per-vertex X and Y clipping planes. The first
308 * plane is per-pixel and the second plane is per-vertex.
330 # define R300_2288_R300 0x00750000 /* -- nh */
331 # define R300_2288_RV350 0x0000FFFF /* -- Vladimir */
381 /* These are values from r300_reg/r300_reg.h - they are known to be correct
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/linux/drivers/net/wireless/ath/ath10k/
H A Dmac.c1 // SPDX-License-Identifier: ISC
3 * Copyright (c) 2005-2011 Atheros Communications Inc.
4 * Copyright (c) 2011-2017 Qualcomm Atheros, Inc.
5 * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
6 * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved.
16 #include <linux/bitfield.h>
25 #include "wmi-tlv.h"
26 #include "wmi-ops.h"
100 #define ath10k_a_rates_size (ARRAY_SIZE(ath10k_rates) - \
135 for (i = 0; i < sband->n_bitrates; i++) { in ath10k_mac_hw_rate_to_idx()
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/linux/Documentation/
H A Dmemory-barriers.txt19 documentation at tools/memory-model/. Nevertheless, even this memory
37 Note also that it is possible that a barrier may be a no-op for an
48 - Device operations.
49 - Guarantees.
53 - Varieties of memory barrier.
54 - What may not be assumed about memory barriers?
55 - Address-dependency barriers (historical).
56 - Control dependencies.
57 - SMP barrier pairing.
58 - Examples of memory barrier sequences.
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