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/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Drenesas,intc-irqpin.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/renesas,intc-irqpin.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Geert Uytterhoeven <geert+renesas@glider.be>
15 - enum:
16 - renesas,intc-irqpin-r8a7740 # R-Mobile A1
17 - renesas,intc-irqpin-r8a7778 # R-Car M1A
18 - renesas,intc-irqpin-r8a7779 # R-Car H1
19 - renesas,intc-irqpin-sh73a0 # SH-Mobile AG5
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/linux/drivers/irqchip/
H A Dirq-renesas-intc-irqpin.c1 // SPDX-License-Identifier: GPL-2.0
35 * SENSE is read-write 32-bit with 2-bits or 4-bits per IRQ (*)
36 * PRIO is read-write 32-bit with 4-bits per IRQ (**)
37 * SOURCE is read-only 32-bit or 8-bit with 1-bit per IRQ (***)
38 * MASK is write-only 32-bit or 8-bit with 1-bit per IRQ (***)
39 * CLEAR is write-only 32-bit or 8-bit with 1-bit per IRQ (***)
41 * (*) May be accessed by more than one driver instance - lock needed
42 * (**) Read-modify-write access by one driver instance - lock needed
43 * (***) Accessed by one driver instance only - no locking needed
50 int width; member
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H A Dirq-renesas-rzv2h.c1 // SPDX-License-Identifier: GPL-2.0
5 * Based on irq-renesas-rzg2l.c
12 #include <linux/bitfield.h>
17 #include <linux/irqchip/irq-renesas-rzv2h.h>
71 ICU_TSSR_TSSEL_PREP((GENMASK(((_field_width) - 2), 0)), (n), _field_width); \
77 BIT((_field_width) - 1) << ((n) * (_field_width)); \
93 * struct rzv2h_hw_info - Interrupt Control Unit controller hardware info structure.
97 * @field_width: TSSR field width
116 * struct rzv2h_icu_priv - Interrupt Control Unit controller private data structure.
142 guard(raw_spinlock_irqsave)(&priv->lock); in rzv2h_icu_register_dma_req()
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/linux/drivers/clk/bcm/
H A Dclk-kona-setup.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include "clk-kona.h"
13 #define selector_clear_exists(sel) ((sel)->width = 0)
20 struct ccu_policy *ccu_policy = &ccu->policy; in ccu_data_offsets_valid()
23 limit = ccu->range - sizeof(u32); in ccu_data_offsets_valid()
26 if (ccu_policy->enable.offset > limit) { in ccu_data_offsets_valid()
29 ccu->name, ccu_policy->enable.offset, limit); in ccu_data_offsets_valid()
32 if (ccu_policy->control.offset > limit) { in ccu_data_offsets_valid()
35 ccu->name, ccu_policy->control.offset, limit); in ccu_data_offsets_valid()
45 struct peri_clk_data *peri = bcm_clk->u.peri; in clk_requires_trigger()
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H A Dclk-kona.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include "clk-kona.h"
12 #include <linux/clk-provider.h>
26 /* Bitfield operations */
28 /* Produces a mask of set bits covering a range of a 32-bit value */
29 static inline u32 bitfield_mask(u32 shift, u32 width) in bitfield_mask() argument
31 return ((1 << width) - 1) << shift; in bitfield_mask()
34 /* Extract the value of a bitfield found within a given register value */
35 static inline u32 bitfield_extract(u32 reg_val, u32 shift, u32 width) in bitfield_extract() argument
37 return (reg_val & bitfield_mask(shift, width)) >> shift; in bitfield_extract()
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/linux/drivers/gpu/drm/msm/registers/adreno/
H A Da2xx.xml1 <?xml version="1.0" encoding="UTF-8"?>
3 xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
4 xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
1028 <domain name="A2XX" width="32">
1031 <bitfield name="COLUMN" low="0" high="2" type="uint"/>
1032 <bitfield name="ROW" low="3" high="5" type="uint"/>
1033 <bitfield name="GUARD_BAND_MASK" low="6" high="8" type="uint"/>
1048 <!--
1051 it doesn't make sense, so I think offset 0x40 must be a different
1053 -->
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H A Da6xx.xml1 <?xml version="1.0" encoding="UTF-8"?>
3 xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
4 xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
14 <!--
17 - "cmd" - the register is used outside of renderpass and blits,
19 - "rp_blit" - the register is used inside renderpass or blits
26 -->
28 <domain name="A6XX" width="32" prefix="variant" varset="chip">
30 <bitfield name="RBBM_GPU_IDLE" pos="0" type="boolean"/>
31 <bitfield name="CP_AHB_ERROR" pos="1" type="boolean"/>
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/linux/include/linux/ssb/
H A Dssb_regs.h1 /* SPDX-License-Identifier: GPL-2.0 */
33 #define SSB_MAX_NR_CORES ((SSB_ENUM_LIMIT - SSB_ENUM_BASE) / SSB_CORE_SIZE)
108 #define SSB_TMSHIGH_SERR 0x00000001 /* S-error */
144 #define SSB_IDLOW_CCW 0x000C0000 /* Cycle counter width */
168 * in two-byte quantities.
202 #define SSB_SPROM1_BINF_ANTBG 0x3000 /* Available B-PHY and G-PHY antennas */
204 #define SSB_SPROM1_BINF_ANTA 0xC000 /* Available A-PHY antennas */
218 #define SSB_SPROM1_MAXPWR_BG 0x00FF /* B-PHY and G-PHY (in dBm Q5.2) */
219 #define SSB_SPROM1_MAXPWR_A 0xFF00 /* A-PHY (in dBm Q5.2) */
225 #define SSB_SPROM1_ITSSI_BG 0x00FF /* B-PHY and G-PHY*/
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/linux/Documentation/ABI/testing/
H A Dsysfs-class-hwmon16 The contents of the label are free-form.
135 this voltage channel is being used for, and user-space
137 user-space.
145 When disabled the sensor read will return -ENODATA.
147 - 1: Enable
148 - 0: Disable
156 - 1: Failed
157 - 0: Ok
262 Only makes sense if the chip supports closed-loop fan speed
272 this fan channel is being used for, and user-space doesn't.
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/linux/include/xen/interface/
H A Dxen.h1 /* SPDX-License-Identifier: MIT */
69 /* Architecture-specific hypercall definitions. */
83 * In the side comments, 'V.' denotes a per-VCPU VIRQ while 'G.' denotes a
84 * global VIRQ. The former can be bound once per VCPU and cannot be re-bound.
86 * allocated to VCPU0 but can subsequently be re-bound.
102 /* Architecture-specific VIRQ definitions. */
127 * x != 0 => PFD == x - 1
129 * Sub-commands: ptr[1:0] specifies the appropriate MMU_* command.
130 * -------------
138 * ptr[:2] -- Machine address of the page-table entry to modify.
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/linux/drivers/pwm/
H A Dpwm-meson.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
13 * Setting the duty cycle will disable and re-enable the PWM output.
19 * https://dl.khadas.com/Hardware/VIM2/Datasheet/S912_Datasheet_V0.220170314publicversion-Wesion.pdf
23 * https://dn.odroid.com/S922X/ODROID-N2/Datasheet/S922X_Public_Datasheet_V0.2.pdf
30 #include <linux/bitfield.h>
33 #include <linux/clk-provider.h>
137 struct meson_pwm_channel *channel = &meson->channels[pwm->hwpwm]; in meson_pwm_request()
141 err = clk_prepare_enable(channel->clk); in meson_pwm_request()
144 __clk_get_name(channel->clk), err); in meson_pwm_request()
154 struct meson_pwm_channel *channel = &meson->channels[pwm->hwpwm]; in meson_pwm_free()
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/linux/drivers/mmc/host/
H A Dcavium.c9 * Copyright (C) 2012-2017 Cavium Inc.
16 #include <linux/bitfield.h>
18 #include <linux/dma-direction.h>
19 #include <linux/dma-mapping.h>
23 #include <linux/mmc/slot-gpio.h>
46 * being used. However, non-MMC devices like SD use command and
128 cr = cvm_mmc_cr_types + (cmd->opcode & 0x3f); in cvm_mmc_get_cr_mods()
129 hardware_ctype = cr->ctype; in cvm_mmc_get_cr_mods()
130 hardware_rtype = cr->rtype; in cvm_mmc_get_cr_mods()
131 if (cmd->opcode == MMC_GEN_CMD) in cvm_mmc_get_cr_mods()
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/linux/drivers/gpu/drm/radeon/
H A Dr300_reg.h95 /* State based - direct writes to registers trigger vertex
107 /* index size - when not set the indices are assumed to be 16 bit */
147 /* BEGIN: Vertex data assembly - lots of uncertainties */
207 * - always set up to produce at least two attributes:
209 * - INPUT_CNTL_0_COLOR and INPUT_CNTL_COLOR bits are always equal.
307 /* These seem to be per-pixel and per-vertex X and Y clipping planes. The first
308 * plane is per-pixel and the second plane is per-vertex.
330 # define R300_2288_R300 0x00750000 /* -- nh */
331 # define R300_2288_RV350 0x0000FFFF /* -- Vladimir */
381 /* These are values from r300_reg/r300_reg.h - they are known to be correct
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/linux/Documentation/
H A Dmemory-barriers.txt19 documentation at tools/memory-model/. Nevertheless, even this memory
37 Note also that it is possible that a barrier may be a no-op for an
48 - Device operations.
49 - Guarantees.
53 - Varieties of memory barrier.
54 - What may not be assumed about memory barriers?
55 - Address-dependency barriers (historical).
56 - Control dependencies.
57 - SMP barrier pairing.
58 - Examples of memory barrier sequences.
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/linux/drivers/net/wireless/ath/ath11k/
H A Dmac.c1 // SPDX-License-Identifier: BSD-3-Clause-Clear
3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2025 Qualcomm Innovation Center, Inc. All rights reserved.
10 #include <linux/bitfield.h>
164 /* new addition in IEEE Std 802.11ax-2021 */
244 #define ath11k_a_rates_size (ARRAY_SIZE(ath11k_legacy_rates) - 4)
405 return -EINVAL; in ath11k_mac_hw_ratecode_to_legacy_rate()
426 for (i = 0; i < sband->n_bitrates; i++) in ath11k_mac_bitrate_to_idx()
427 if (sband->bitrates[i].bitrate == bitrate) in ath11k_mac_bitrate_to_idx()
438 for (nss = IEEE80211_HT_MCS_MASK_LEN - 1; nss >= 0; nss--) in ath11k_mac_max_ht_nss()
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/linux/net/wireless/
H A Dnl80211.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * This is the new netlink-based wireless configuration interface.
5 * Copyright 2006-2010 Johannes Berg <johannes@sipsolutions.net>
6 * Copyright 2013-2014 Intel Mobile Communications GmbH
7 * Copyright 2015-2017 Intel Deutschland GmbH
8 * Copyright (C) 2018-2025 Intel Corporation
32 #include "rdev-ops.h"
50 NL80211_MCGRP_TESTMODE /* keep last - ifdef! */
74 int wiphy_idx = -1; in __cfg80211_wdev_from_attrs()
75 int ifidx = -1; in __cfg80211_wdev_from_attrs()
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/linux/Documentation/virt/kvm/
H A Dapi.rst1 .. SPDX-License-Identifier: GPL-2.0
4 The Definitive KVM (Kernel-based Virtual Machine) API Documentation
24 - System ioctls: These query and set global attributes which affect the
28 - VM ioctls: These query and set attributes that affect an entire virtual
35 - vcpu ioctls: These query and set attributes that control the operation
43 - device ioctls: These query and set attributes that control the operation
92 facility that allows backward-compatible extensions to the API to be
133 -----------------------
150 -----------------
188 identifier, where IPA_Bits is the maximum width of any physical
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/linux/drivers/net/ethernet/sfc/
H A Dmcdi_pcol.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright 2009-2018 Solarflare Communications Inc.
5 * Copyright 2019-2020 Xilinx Inc.
13 /* Power-on reset state */
35 /* The 'doorbell' addresses are hard-wired to alert the MC when written */
38 /* The rest of these are firmware-defined */
46 /* Values to be written to the per-port status dword in shared
71 * | | \--- Response
72 * | \------- Error
73 * \------------------------------ Resync (always set)
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/linux/arch/arm64/kvm/
H A Dsys_regs.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2012,2013 - ARM Ltd
7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
12 #include <linux/bitfield.h>
20 #include <linux/irqchip/arm-gic-v3.h>
25 #include <asm/debug-monitors.h>
74 "sys_reg read to write-only register"); in read_from_write_only()
82 "sys_reg write to read-only register"); in write_to_read_only()
142 /* Non-mapped EL2 registers are by definition in memory. */ in locate_direct_register()
154 loc->loc = SR_LOC_MEMORY; in locate_mapped_el2_register()
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/linux/drivers/net/ethernet/chelsio/cxgb4/
H A Dt4_hw.c4 * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
16 * - Redistributions of source code must retain the above
20 * - Redistributions in binary form must reproduce the above
43 * t4_wait_op_done_val - wait until an operation is completed
46 * @mask: a single-bit field within @reg that indicates completion
55 * operation completes and -EAGAIN otherwise.
68 if (--attempts == 0) in t4_wait_op_done_val()
69 return -EAGAIN; in t4_wait_op_done_val()
83 * t4_set_reg_field - set a register field to a value
102 * t4_read_indirect - read indirectly addressed registers
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/linux/drivers/pci/
H A Dquirks.c1 // SPDX-License-Identifier: GPL-2.0
3 * This file contains work-arounds for many known PCI hardware bugs.
5 * should be handled in arch-specific code.
17 #include <linux/bitfield.h>
22 #include <linux/isa-dma.h> /* isa_dma_bridge_buggy */
41 if (test_bit(PCI_LINK_LBMS_SEEN, &dev->priv_flags)) in pcie_lbms_seen()
69 * hardware has changed the link speed or width in an attempt to correct
102 int ret = -ENOTTY; in pcie_failed_link_retrain()
105 !pcie_cap_has_lnkctl2(dev) || !dev->link_active_reporting) in pcie_failed_link_retrain()
112 pci_info(dev, "broken device, retraining non-functional downstream link at 2.5GT/s\n"); in pcie_failed_link_retrain()
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