sense\-bitfield\-width (full) in projects: freebsd

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Searched +full:sense +full:- +full:bitfield +full:- +full:width (Results 1 – 25 of 48) sorted by relevance

/freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/
H A D	renesas,intc-irqpin.yaml	`1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/interrupt-controller/renesas,intc-irqpin.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Geert Uytterhoeven <geert+renesas@glider.be> 15 - enum: 16 - renesas,intc-irqpin-r8a7740 # R-Mobile A1 17 - renesas,intc-irqpin-r8a7778 # R-Car M1A 18 - renesas,intc-irqpin-r8a7779 # R-Car H1 19 - renesas,intc-irqpin-sh73a0 # SH-Mobile AG5 [all …]`
/freebsd/contrib/llvm-project/clang/lib/AST/
H A D	RecordLayoutBuilder.cpp	1 //=== RecordLayoutBuilder.cpp - Helper class for building record layouts ---==// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 28 /// BaseSubobjectInfo - Represents a single base subobject in a complete class. 40 /// Class - The class for this base info. 43 /// IsVirtual - Whether the BaseInfo represents a virtual base or not. 46 /// Bases - Information about the base subobjects. 49 /// PrimaryVirtualBaseInfo - Holds the base info for the primary virtual base 72 /// Direct, non-virtual base offsets. 90 BaseOffset = Known->second; in getExternalNVBaseOffset() [all …]
H A D	ASTContext.cpp	1 //===- ASTContext.cpp - Context to hold long-lived AST nodes --------------===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 11 //===----------------------------------------------------------------------===// 125 if (D->isImplicit()) in getDeclLocsForCommentSearch() 130 if (FD->getTemplateSpecializationKind() == TSK_ImplicitInstantiation) in getDeclLocsForCommentSearch() 135 if (VD->isStaticDataMember() && in getDeclLocsForCommentSearch() 136 VD->getTemplateSpecializationKind() == TSK_ImplicitInstantiation) in getDeclLocsForCommentSearch() 141 if (CRD->getTemplateSpecializationKind() == TSK_ImplicitInstantiation) in getDeclLocsForCommentSearch() 146 TemplateSpecializationKind TSK = CTSD->getSpecializationKind(); in getDeclLocsForCommentSearch() [all …]
/freebsd/contrib/llvm-project/lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/
H A D	AppleObjCTypeEncodingParser.cpp	1 //===-- AppleObjCTypeEncodingParser.cpp -----------------------------------===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 34 runtime.GetProcess()->GetTarget().GetArchitecture().GetTriple()); in AppleObjCTypeEncodingParser() 57 total = 10 * total + (type.Next() - '0'); in ReadNumber() 63 // "{CGRect=\"origin\"{CGPoint=\"x\"d\"y\"d}\"size\"{CGSize=\"width\"d\"height\"d}}" 79 retval.bitfield = bitfield_size; in ReadStructElement() 145 lldb::eAccessPublic, element.bitfield); in BuildAggregate() 190 // - @"NSString"@ means "id, followed by a field named NSString of type id" in BuildObjCObjectPointerType() 191 // - @"NSString"} means "a pointer to NSString and the end of the struct" - in BuildObjCObjectPointerType() [all …]
/freebsd/share/misc/
H A D	scsi_modes	`35 # 'i' is a byte-sized integral types, followed by a field width of 38 # 'b' is a bit-sized integral type 39 # 't' is a bitfield type- followed by a bit field width 42 # 'z' values are null-padded strings 81 {Extended Self-Test Completion Time} i2 92 {Maximum Sense Data Length} i1 95 0x02 "Disconnect-Reconnect" { 111 0x16 "Extended Device-Type Specific"; 154 0x18 "Protocol-Specific Logical Unit"; 156 0x19 "Protocol-Specific Port"; [all …]`
/freebsd/share/man/man9/
H A D	bus_dma.9	170 API is a bus, device, and machine-independent (MI) interface to 182 For example, if a DMA engine in a device is limited to 32-bit addresses, 190 For example, a device might require 16-byte alignment of its descriptor ring 201 The per-group tags can then inherit these restrictions from this 203 tag rather than having to list them explicitly when creating the per-group tags. 234 Sync operations also handle architecture-specific details such as CPU cache 239 Static transactions are used with a long-lived memory region that is reused 285 to track the mappings of any in-flight transactions. 315 .Bl -tag -width indent 317 A machine-dependent (MD) opaque type that describes the [all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A D	Instructions.h	1 //===- llvm/Instructions.h - Instruction subclass definitions ---- C++ --===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 13 //===----------------------------------------------------------------------===// 56 //===----------------------------------------------------------------------===// 58 //===----------------------------------------------------------------------===// 67 static_assert(Bitfield::areContiguous<AlignmentField, UsedWithInAllocaField, 103 return getType()->getAddressSpace(); in getAddressSpace() 153 return (I->getOpcode() == Instruction::Alloca); in classof() 162 template <typename Bitfield> [all …]
/freebsd/sys/contrib/device-tree/src/arm/renesas/
H A D	r8a7778.dtsi	`1 // SPDX-License-Identifier: GPL-2.0 3 * Device Tree Source for the R-Car M1A (R8A77781) SoC 14 #include <dt-bindings/clock/r8a7778-clock.h> 15 #include <dt-bindings/interrupt-controller/arm-gic.h> 16 #include <dt-bindings/interrupt-controller/irq.h> 20 interrupt-parent = <&gic>; 21 #address-cells = <1>; 22 #size-cells = <1>; 25 #address-cells = <1>; 26 #size-cells = <0>; [all …]`
H A D	r8a7779.dtsi	`1 // SPDX-License-Identifier: GPL-2.0 3 * Device Tree Source for the R-Car H1 (R8A77790) SoC 9 #include <dt-bindings/clock/r8a7779-clock.h> 10 #include <dt-bindings/interrupt-controller/arm-gic.h> 11 #include <dt-bindings/interrupt-controller/irq.h> 12 #include <dt-bindings/power/r8a7779-sysc.h> 16 interrupt-parent = <&gic>; 17 #address-cells = <1>; 18 #size-cells = <1>; 21 #address-cells = <1>; [all …]`
/freebsd/contrib/llvm-project/clang/lib/Sema/
H A D	SemaChecking.cpp	1 //===- SemaChecking.cpp - Extra Semantic Checking -------------------------===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 12 //===----------------------------------------------------------------------===// 125 return SL->getLocationOfByte(ByteNo, getSourceManager(), LangOpts, in getLocationOfStringLiteralByte() 135 unsigned ArgCount = Call->getNumArgs(); in checkArgCountAtLeast() 139 return Diag(Call->getEndLoc(), diag::err_typecheck_call_too_few_args) in checkArgCountAtLeast() 141 << /is non object/ 0 << Call->getSourceRange(); in checkArgCountAtLeast() 145 unsigned ArgCount = Call->getNumArgs(); in checkArgCountAtMost() 148 return Diag(Call->getEndLoc(), diag::err_typecheck_call_too_many_args_at_most) in checkArgCountAtMost() [all …]
/freebsd/sys/contrib/xen/
H A D	xen.h	30 #include "xen-compat.h" 33 #include "arch-x86/xen.h" 35 #include "arch-arm.h" 135 /* Architecture-specific hypercall definitions. / 157 / New event-channel and physdev hypercalls introduced in 0x00030202. / 175 In the side comments, 'V.' denotes a per-VCPU VIRQ while 'G.' denotes a 176 * global VIRQ. The former can be bound once per VCPU and cannot be re-bound. 178 * allocated to VCPU0 but can subsequently be re-bound. 195 /* Architecture-specific VIRQ definitions. / 223 x != 0 => PFD == x - 1 [all …]
/freebsd/contrib/llvm-project/clang/lib/CodeGen/Targets/
H A D	X86.cpp	1 //===- X86.cpp ------------------------------------------------------------===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 19 /// IsX86_MMXType - Return true if this is an MMX type. 22 return IRType->isVectorTy() && IRType->getPrimitiveSizeInBits() == 64 && in IsX86_MMXType() 23 cast<llvm::VectorType>(IRType)->getElementType()->isIntegerTy() && in IsX86_MMXType() 24 IRType->getScalarSizeInBits() != 64; in IsX86_MMXType() 33 if (IsMMXCons && Ty->isVectorTy()) { in X86AdjustInlineAsmType() 34 if (cast<llvm::VectorType>(Ty)->getPrimitiveSizeInBits().getFixedValue() != in X86AdjustInlineAsmType() 45 return llvm::FixedVectorType::get(Int1Ty, Ty->getScalarSizeInBits()); in X86AdjustInlineAsmType() [all …]
/freebsd/contrib/llvm-project/clang/include/clang/AST/
H A D	ASTContext.h	1 //===- ASTContext.h - Context to hold long-lived AST nodes ------- C++ --===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 12 //===----------------------------------------------------------------------===// 157 uint64_t Width = 0; member 162 TypeInfo(uint64_t Width, unsigned Align, in TypeInfo() 164 : Width(Width), Align(Align), AlignRequirement(AlignRequirement) {} in TypeInfo() 171 CharUnits Width; member 176 TypeInfoChars(CharUnits Width, CharUnits Align, in TypeInfoChars() 178 : Width(Width), Align(Align), AlignRequirement(AlignRequirement) {} in TypeInfoChars() [all …]
H A D	Type.h	1 //===- Type.h - C Language Family Type Representation ------------ C++ --===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 15 //===----------------------------------------------------------------------===// 145 /// Pointer-authentication qualifiers. 157 AuthenticationModeMask = ((1 << AuthenticationModeBits) - 1) 161 IsaPointerMask = ((1 << IsaPointerBits) - 1) << IsaPointerShift, 164 AuthenticatesNullValuesMask = ((1 << AuthenticatesNullValuesBits) - 1) 168 KeyMask = ((1 << KeyBits) - 1) << KeyShift, 171 DiscriminatorMask = ((1u << DiscriminatorBits) - 1) << DiscriminatorShift, [all …]
H A D	DeclBase.h	1 //===- DeclBase.h - Base Classes for representing declarations --- C++ --===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 11 //===----------------------------------------------------------------------===// 79 /// Decl - This represents one declaration (or definition), e.g. a variable, 100 /// decl-derived type that will be filled in later (e.g., by some 104 /// IdentifierNamespace - The different namespaces in which 121 /// elaborated-type-specifiers look for in C. 123 /// same scope but that are otherwise ordinary names (non-type 128 /// This is what elaborated-type-specifiers look for in C++, [all …]
/freebsd/contrib/llvm-project/clang/lib/Basic/Targets/
H A D	ARM.cpp	1 //===--- ARM.cpp - Implement ARM target feature support -------------------===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 11 //===----------------------------------------------------------------------===// 47 ? "E-m:o-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" in setABIAAPCS() 48 : "e-m:o-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64", in setABIAAPCS() 53 "-m:w" in setABIAAPCS() 54 "-p:32:32" in setABIAAPCS() 55 "-Fi8" in setABIAAPCS() 56 "-i64:64" in setABIAAPCS() [all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A D	HexagonConstPropagation.cpp	1 //===- HexagonConstPropagation.cpp --------- 1565 evaluateZEXTr(const RegisterSubReg & R1,unsigned Width,unsigned Bits,const CellMap & Inputs,LatticeCell & Result) evaluateZEXTr() argument 1586 evaluateZEXTi(const APInt & A1,unsigned Width,unsigned Bits,APInt & Result) evaluateZEXTi() argument 1596 evaluateSEXTr(const RegisterSubReg & R1,unsigned Width,unsigned Bits,const CellMap & Inputs,LatticeCell & Result) evaluateSEXTr() argument 1617 evaluateSEXTi(const APInt & A1,unsigned Width,unsigned Bits,APInt & Result) evaluateSEXTi() argument 1732 evaluateEXTRACTr(const RegisterSubReg & R1,unsigned Width,unsigned Bits,unsigned Offset,bool Signed,const CellMap & Inputs,LatticeCell & Result) evaluateEXTRACTr() argument [all...]
/freebsd/contrib/llvm-project/clang/lib/CodeGen/
H A D	CGDebugInfo.cpp	1 //===--- CGDebugInfo.cpp - Emit Debug Information for a Module ------------===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 11 //===----------------------------------------------------------------------===// 67 if (auto Decl = Ty->getAsRecordDecl()) in getTypeAlignIfRequired() 68 if (Decl->hasAttr<MaxFieldAlignmentAttr>()) in getTypeAlignIfRequired() 79 return D->hasAttr<AlignedAttr>() ? D->getMaxAlignment() : 0; in getDeclAlignIfRequired() 109 auto DI = CGF->getDebugInfo(); in init() 115 OriginalLocation = CGF->Builder.getCurrentDebugLocation(); in init() 117 if (OriginalLocation && !DI->CGM.getExpressionLocationsEnabled()) in init() [all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A D	AMDGPURegisterBankInfo.cpp	1 //===- AMDGPURegisterBankInfo.cpp -------------------------------- C++ --==// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 17 /// sort of pseudo-register bank needed to represent SGPRs used in a vector 31 /// is naturally a bitmask with one bit per lane, in a 32 or 64-bit 37 /// SCC, which is a 1-bit unaddressable register. This will need to be copied to 38 /// a 32-bit virtual register. Taken together, this means we need to adjust the 40 /// widened to 32-bits, and all VALU booleans need to be s1 values. 42 /// A noteworthy exception to the s1-means-vcc rule is for legalization artifact 44 /// bank. A non-boolean source (such as a truncate from a 1-bit load from [all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A D	AArch64ISelDAGToDAG.cpp	1 //===-- AArch64ISelDAGToDAG.cpp - A dag to dag inst selector for AArch64 --===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 11 //===----------------------------------------------------------------------===// 31 #define DEBUG_TYPE "aarch64-isel" 34 //===--------------------------------------------------------------------===// 35 /// AArch64DAGToDAGISel - AArch64 specific code to select AArch64 machine 42 /// Subtarget - Keep a pointer to the AArch64Subtarget around so that we can 60 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for 137 int64_t C = CI->getSExtValue(); in SelectAddrModeIndexedUImm() [all …]
/freebsd/contrib/llvm-project/llvm/lib/Transforms/Utils/
H A D	SimplifyLibCalls.cpp	1 //===------ SimplifyLibCalls.cpp - Library calls simplifier ---------------===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 12 //===----------------------------------------------------------------------===// 45 EnableUnsafeFPShrink("enable-double-float-shrink", cl::Hidden, 54 OptimizeHotColdNew("optimize-hot-cold-new", cl::Hidden, cl::init(false), 57 "optimize-existing-hot-cold-new", cl::Hidden, cl::init(false), 87 "cold-new-hint-value", cl::Hidden, cl::init(1), 90 NotColdNewHintValue("notcold-new-hint-value", cl::Hidden, cl::init(128), 94 "hot-new-hint-value", cl::Hidden, cl::init(254), [all …]
/freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/
H A D	InstCombineAndOrXor.cpp	1 //===- InstCombineAndOrXor.cpp --------------------------------------------===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 11 //===----------------------------------------------------------------------===// 34 if (Constant TorF = getPredForICmpCode(Code, Sign, LHS->getType(), NewPred)) in getNewICmpValue() 44 if (Constant TorF = getPredForFCmpCode(Code, LHS->getType(), NewPred)) in getFCmpValue() 58 Type *Ty = V->getType(); in insertRangeTest() 60 // V >= Min && V < Hi --> V < Hi in insertRangeTest() 61 // V < Min \|\| V >= Hi --> V >= Hi in insertRangeTest() 68 // V >= Lo && V < Hi --> V - Lo u< Hi - Lo in insertRangeTest() [all …]
H A D	InstCombineLoadStoreAlloca.cpp	1 //===- InstCombineLoadStoreAlloca.cpp -------------------------------------===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 11 //===----------------------------------------------------------------------===// 35 "instcombine-max-copied-from-constant-users", cl::init(300), 41 "enable-infer-alignment-pass", cl::init(true), cl::Hidden, cl::ZeroOrMore, 46 /// isOnlyCopiedFromConstantMemory - Recursively walk the uses of a (derived) 73 for (auto &U : Value->uses()) { in isOnlyCopiedFromConstantMemory() 77 // Ignore non-volatile loads, they are always ok. in isOnlyCopiedFromConstantMemory() 78 if (!LI->isSimple()) return false; in isOnlyCopiedFromConstantMemory() [all …]
/freebsd/contrib/llvm-project/llvm/lib/Transforms/Scalar/
H A D	SROA.cpp	1 //===- SROA.cpp - Scalar Replacement Of Aggregates ------------------------===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 13 /// or bitfield-style integer scalar if appropriate. 23 //===----------------------------------------------------------------------===// 46 #include "llvm/Config/llvm-config.h" 120 static cl::opt<bool> SROASkipMem2Reg("sroa-skip-mem2reg", cl::init(false), 130 using TrueVal = Bitfield::Element<bool, 0, 1>; // Low 0'th bit. 131 using FalseVal = Bitfield::Element<bool, 1, 1>; // Low 1'th bit. 182 /// already present to ensure it is re-visited. [all …]
/freebsd/contrib/llvm-project/lldb/source/Plugins/TypeSystem/Clang/
H A D	TypeSystemClang.cpp	1 //===-- TypeSystemClang.cpp -----------------------------------------------===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 102 decl->getAccess(); in VerifyDecl() 117 // Open Dylan compiler debug info is designed to be Clang-compatible in TypeSystemClangSupportsLanguage() 126 lldbassert(&m1->getASTContext() == &m2->getASTContext() && in isOverload() 128 clang::ASTContext &context = m1->getASTContext(); in isOverload() 131 context.getCanonicalType(m1->getType())); in isOverload() 134 context.getCanonicalType(m2->getType())); in isOverload() 142 // FIXME: In C++14 and later, we can just pass m2Type->param_type_end() in isOverload() [all …]