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/linux/Documentation/userspace-api/media/v4l/
H A Dsdr-formats.rst7 SDR Formats
10 These formats are used for :ref:`SDR <sdr>` interface only.
16 pixfmt-sdr-cu08
17 pixfmt-sdr-cu16le
18 pixfmt-sdr-cs08
19 pixfmt-sdr-cs14le
20 pixfmt-sdr-ru12le
21 pixfmt-sdr-pcu16be
22 pixfmt-sdr-pcu18be
23 pixfmt-sdr-pcu20be
H A Ddev-sdr.rst7 Software Defined Radio Interface (SDR)
10 SDR is an abbreviation of Software Defined Radio, the radio device which
14 SDR devices are accessed through character device special files named
22 Devices supporting the SDR receiver interface set the
28 element for the SDR receiver.
30 Devices supporting the SDR transmitter interface set the
36 element for the SDR transmitter.
45 SDR devices can support :ref:`controls <control>`, and must support
50 The ``V4L2_TUNER_SDR`` tuner type is used for setting SDR device ADC/DAC
53 follow the SDR tuner index. Normally the SDR tuner is #0 and the RF
[all …]
H A Dvidioc-g-modulator.rst55 :ref:`SDR <sdr>` specific modulator types are ``V4L2_TUNER_SDR`` and
56 ``V4L2_TUNER_RF``. For SDR devices ``txsubchans`` field must be
57 initialized to zero. The term 'modulator' means SDR transmitter in this
H A Dvidioc-g-tuner.rst55 :ref:`SDR <sdr>` specific tuner types are ``V4L2_TUNER_SDR`` and
56 ``V4L2_TUNER_RF``. For SDR devices ``audmode`` field must be initialized
57 to zero. The term 'tuner' means SDR receiver in this context.
203 Software Digital Radio (SDR)
206 - Tuner controls the RF part of a Software Digital Radio (SDR)
H A Dvidioc-querycap.rst232 - The device supports the :ref:`SDR Capture <sdr>` interface.
239 - The device supports the :ref:`SDR Output <sdr>` interface.
/linux/drivers/mtd/nand/raw/
H A Dnand_toshiba.c35 const struct nand_sdr_timings *sdr = in toshiba_nand_benand_read_eccstatus_op() local
39 PSEC_TO_NSEC(sdr->tADL_min)), in toshiba_nand_benand_read_eccstatus_op()
223 struct nand_sdr_timings *sdr = &iface->timings.sdr; in th58nvg2s3hbai4_choose_interface_config() local
229 sdr->tALS_min = 12000; in th58nvg2s3hbai4_choose_interface_config()
230 sdr->tCHZ_max = 20000; in th58nvg2s3hbai4_choose_interface_config()
231 sdr->tCLS_min = 12000; in th58nvg2s3hbai4_choose_interface_config()
232 sdr->tCOH_min = 0; in th58nvg2s3hbai4_choose_interface_config()
233 sdr->tDS_min = 12000; in th58nvg2s3hbai4_choose_interface_config()
234 sdr->tRHOH_min = 25000; in th58nvg2s3hbai4_choose_interface_config()
235 sdr->tRHW_min = 30000; in th58nvg2s3hbai4_choose_interface_config()
[all …]
H A Dnand_timings.c27 .timings.sdr = {
72 .timings.sdr = {
117 .timings.sdr = {
162 .timings.sdr = {
207 .timings.sdr = {
252 .timings.sdr = {
550 /* All NAND chips share the same reset data interface: SDR mode 0 */
557 * onfi_find_closest_sdr_mode - Derive the closest ONFI SDR timing mode given a
568 onfi_timings = &onfi_sdr_timings[mode].timings.sdr; in onfi_find_closest_sdr_mode()
646 * onfi_fill_sdr_interface_config - Initialize a SDR interface config from a
[all …]
H A Dams-delta.c198 const struct nand_sdr_timings *sdr = nand_get_sdr_timings(cf); in gpio_nand_setup_interface() local
201 if (IS_ERR(sdr)) in gpio_nand_setup_interface()
202 return PTR_ERR(sdr); in gpio_nand_setup_interface()
208 priv->tRP = DIV_ROUND_UP(sdr->tRP_min, 1000); in gpio_nand_setup_interface()
212 priv->tWP = DIV_ROUND_UP(sdr->tWP_min, 1000); in gpio_nand_setup_interface()
H A Dmxic_nand.c458 const struct nand_sdr_timings *sdr; in mxic_nfc_setup_interface() local
462 sdr = nand_get_sdr_timings(conf); in mxic_nfc_setup_interface()
463 if (IS_ERR(sdr)) in mxic_nfc_setup_interface()
464 return PTR_ERR(sdr); in mxic_nfc_setup_interface()
469 freq = NSEC_PER_SEC / (sdr->tRC_min / 1000); in mxic_nfc_setup_interface()
475 if (sdr->tRC_min < 30000) in mxic_nfc_setup_interface()
/linux/arch/arm/mach-socfpga/
H A Dself-refresh.S27 * sdr.ctrlcfg.lowpwreq.selfrfshmask
28 * sdr.ctrlcfg.lowpwrtiming.clkdisablecycles
29 * sdr.ctrlcfg.dramtiming4.selfrfshexit
53 /* Enable self refresh: set sdr.ctrlgrp.lowpwreq.selfrshreq = 1 */
58 /* Poll until sdr.ctrlgrp.lowpwrack.selfrfshack == 1 or hit max loops */
89 /* Disable self-refresh: set sdr.ctrlgrp.lowpwreq.selfrshreq = 0 */
94 /* Poll until sdr.ctrlgrp.lowpwrack.selfrfshack == 0 or hit max loops */
/linux/drivers/mtd/nand/raw/atmel/
H A Dnand-controller.c1257 if (conf->timings.sdr.tRC_min < 30000) in atmel_smc_nand_prepare_smcconf()
1270 ncycles = DIV_ROUND_UP(conf->timings.sdr.tWP_min, mckperiodps); in atmel_smc_nand_prepare_smcconf()
1288 timeps = max3(conf->timings.sdr.tCLS_min, conf->timings.sdr.tCS_min, in atmel_smc_nand_prepare_smcconf()
1289 conf->timings.sdr.tALS_min); in atmel_smc_nand_prepare_smcconf()
1290 timeps = max(timeps, conf->timings.sdr.tDS_min); in atmel_smc_nand_prepare_smcconf()
1305 timeps = max3(conf->timings.sdr.tCLH_min, conf->timings.sdr.tCH_min, in atmel_smc_nand_prepare_smcconf()
1306 conf->timings.sdr.tALH_min); in atmel_smc_nand_prepare_smcconf()
1307 timeps = max3(timeps, conf->timings.sdr.tDH_min, in atmel_smc_nand_prepare_smcconf()
1308 conf->timings.sdr.tWH_min); in atmel_smc_nand_prepare_smcconf()
1319 ncycles = DIV_ROUND_UP(conf->timings.sdr.tWC_min, mckperiodps); in atmel_smc_nand_prepare_smcconf()
[all …]
/linux/arch/powerpc/boot/
H A D4xx.c471 unsigned int sdr; in eplike_fixup_uart_clk() local
476 sdr = SDR0_READ(DCRN_SDR0_UART0); in eplike_fixup_uart_clk()
479 sdr = SDR0_READ(DCRN_SDR0_UART1); in eplike_fixup_uart_clk()
482 sdr = SDR0_READ(DCRN_SDR0_UART2); in eplike_fixup_uart_clk()
485 sdr = SDR0_READ(DCRN_SDR0_UART3); in eplike_fixup_uart_clk()
491 if (sdr & 0x00800000u) in eplike_fixup_uart_clk()
494 clock = plb_clk / __fix_zero(sdr & 0xff, 256); in eplike_fixup_uart_clk()
/linux/drivers/media/dvb-frontends/
H A Drtl2832_sdr.c3 * Realtek RTL2832U SDR driver
1132 f->fmt.sdr.pixelformat = dev->pixelformat; in rtl2832_sdr_g_fmt_sdr_cap()
1133 f->fmt.sdr.buffersize = dev->buffersize; in rtl2832_sdr_g_fmt_sdr_cap()
1147 (char *)&f->fmt.sdr.pixelformat); in rtl2832_sdr_s_fmt_sdr_cap()
1153 if (formats[i].pixelformat == f->fmt.sdr.pixelformat) { in rtl2832_sdr_s_fmt_sdr_cap()
1156 f->fmt.sdr.buffersize = formats[i].buffersize; in rtl2832_sdr_s_fmt_sdr_cap()
1163 f->fmt.sdr.pixelformat = formats[0].pixelformat; in rtl2832_sdr_s_fmt_sdr_cap()
1164 f->fmt.sdr.buffersize = formats[0].buffersize; in rtl2832_sdr_s_fmt_sdr_cap()
1177 (char *)&f->fmt.sdr.pixelformat); in rtl2832_sdr_try_fmt_sdr_cap()
1180 if (formats[i].pixelformat == f->fmt.sdr.pixelformat) { in rtl2832_sdr_try_fmt_sdr_cap()
[all …]
/linux/arch/arm/mach-omap2/
H A Dsram242x.S131 * r0 = [PRCM_FULL | PRCM_HALF] r1 = SDRC_DLLA_CTRL value r2 = [DDR | SDR]
132 * PRCM_FULL = 2, PRCM_HALF = 1, DDR = 1, SDR = 0
138 mcr p15, 0, r3, c7, c10, 4 @ memory barrier, finish ARM SDR/DDR
172 cmp r2, #0x1 @ (SDR or DDR) do we need to adjust DLL
173 bne freq_out @ leave if SDR, no DLL function
H A Dsram243x.S131 * r0 = [PRCM_FULL | PRCM_HALF] r1 = SDRC_DLLA_CTRL value r2 = [DDR | SDR]
132 * PRCM_FULL = 2, PRCM_HALF = 1, DDR = 1, SDR = 0
138 mcr p15, 0, r3, c7, c10, 4 @ memory barrier, finish ARM SDR/DDR
172 cmp r2, #0x1 @ (SDR or DDR) do we need to adjust DLL
173 bne freq_out @ leave if SDR, no DLL function
H A Dsleep24xx.S55 mcr p15, 0, r3, c7, c10, 4 @ memory barrier, hope SDR/DDR finished
75 movs r0, r0 @ see if DDR or SDR
/linux/drivers/gpu/drm/amd/display/dc/inc/hw/
H A Ddwb.h91 DWB_SRGB_BT709 = 0, //SDR
97 DWB_SRGB = 0, //SDR
98 DWB_BT709 = 1, //SDR
/linux/arch/powerpc/boot/dts/
H A Dredwood.dts95 SDR0: sdr {
96 compatible = "ibm,sdr-460sx";
249 sdr-base = <0x300>;
290 sdr-base = <0x340>;
331 sdr-base = <0x370>;
H A Dkatmai.dts102 SDR0: sdr {
103 compatible = "ibm,sdr-440spe";
333 sdr-base = <0x300>;
374 sdr-base = <0x340>;
415 sdr-base = <0x370>;
/linux/include/linux/i3c/
H A Ddevice.h46 * @I3C_SDR: SDR mode (NOT HDR mode)
53 /* Use for default SDR transfer mode */
122 * @max_read_len: max private SDR read length in bytes
123 * @max_write_len: max private SDR write length in bytes
/linux/arch/arm/boot/dts/samsung/
H A Dexynos5260-xyref5260.dts99 samsung,dw-mshc-sdr-timing = <0 4>;
111 samsung,dw-mshc-sdr-timing = <2 3>;
H A Dexynos5410-smdk5410.dts71 samsung,dw-mshc-sdr-timing = <2 3>;
81 samsung,dw-mshc-sdr-timing = <2 3>;
/linux/arch/mips/kernel/
H A Dunaligned.c339 * or race makes us see a 64-bit instruction here the sdl/sdr in emulate_load_store_insn()
362 * or race makes us see a 64-bit instruction here the sdl/sdr in emulate_load_store_insn()
417 * or race makes us see a 64-bit instruction here the sdl/sdr in emulate_load_store_insn()
1122 * or race makes us see a 64-bit instruction here the sdl/sdr in emulate_load_store_microMIPS()
1144 * or race makes us see a 64-bit instruction here the sdl/sdr in emulate_load_store_microMIPS()
1186 * or race makes us see a 64-bit instruction here the sdl/sdr in emulate_load_store_microMIPS()
1388 * or race makes us see a 64-bit instruction here the sdl/sdr in emulate_load_store_MIPS16e()
1412 * or race makes us see a 64-bit instruction here the sdl/sdr in emulate_load_store_MIPS16e()
1460 * or race makes us see a 64-bit instruction here the sdl/sdr in emulate_load_store_MIPS16e()
/linux/arch/arm64/boot/dts/altera/
H A Dsocfpga_stratix10.dtsi579 sdr: sdr@f8011100 { label
580 compatible = "altr,sdr-ctl", "syscon";
597 altr,sdr-syscon = <&sdr>;
/linux/arch/arm64/boot/dts/intel/
H A Dsocfpga_agilex.dtsi607 sdr: sdr@f8011100 { label
608 compatible = "altr,sdr-ctl", "syscon";
625 altr,sdr-syscon = <&sdr>;

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