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/linux/Documentation/userspace-api/media/v4l/
H A Dsdr-formats.rst7 SDR Formats
10 These formats are used for :ref:`SDR <sdr>` interface only.
16 pixfmt-sdr-cu08
17 pixfmt-sdr-cu16le
18 pixfmt-sdr-cs08
19 pixfmt-sdr-cs14le
20 pixfmt-sdr-ru12le
21 pixfmt-sdr-pcu16be
22 pixfmt-sdr-pcu18be
23 pixfmt-sdr-pcu20be
H A Ddev-sdr.rst7 Software Defined Radio Interface (SDR)
10 SDR is an abbreviation of Software Defined Radio, the radio device which
14 SDR devices are accessed through character device special files named
22 Devices supporting the SDR receiver interface set the
28 element for the SDR receiver.
30 Devices supporting the SDR transmitter interface set the
36 element for the SDR transmitter.
45 SDR devices can support :ref:`controls <control>`, and must support
50 The ``V4L2_TUNER_SDR`` tuner type is used for setting SDR device ADC/DAC
53 follow the SDR tuner index. Normally the SDR tuner is #0 and the RF
[all …]
H A Dvidioc-g-modulator.rst55 :ref:`SDR <sdr>` specific modulator types are ``V4L2_TUNER_SDR`` and
56 ``V4L2_TUNER_RF``. For SDR devices ``txsubchans`` field must be
57 initialized to zero. The term 'modulator' means SDR transmitter in this
H A Dvidioc-g-tuner.rst55 :ref:`SDR <sdr>` specific tuner types are ``V4L2_TUNER_SDR`` and
56 ``V4L2_TUNER_RF``. For SDR devices ``audmode`` field must be initialized
57 to zero. The term 'tuner' means SDR receiver in this context.
203 Software Digital Radio (SDR)
206 - Tuner controls the RF part of a Software Digital Radio (SDR)
H A Dvidioc-querycap.rst232 - The device supports the :ref:`SDR Capture <sdr>` interface.
239 - The device supports the :ref:`SDR Output <sdr>` interface.
H A Ddevices.rst23 dev-sdr
/linux/drivers/mtd/nand/raw/
H A Dnand_toshiba.c35 const struct nand_sdr_timings *sdr = in toshiba_nand_benand_read_eccstatus_op() local
39 PSEC_TO_NSEC(sdr->tADL_min)), in toshiba_nand_benand_read_eccstatus_op()
223 struct nand_sdr_timings *sdr = &iface->timings.sdr; in th58nvg2s3hbai4_choose_interface_config() local
229 sdr->tALS_min = 12000; in th58nvg2s3hbai4_choose_interface_config()
230 sdr->tCHZ_max = 20000; in th58nvg2s3hbai4_choose_interface_config()
231 sdr->tCLS_min = 12000; in th58nvg2s3hbai4_choose_interface_config()
232 sdr->tCOH_min = 0; in th58nvg2s3hbai4_choose_interface_config()
233 sdr->tDS_min = 12000; in th58nvg2s3hbai4_choose_interface_config()
234 sdr->tRHOH_min = 25000; in th58nvg2s3hbai4_choose_interface_config()
235 sdr->tRHW_min = 30000; in th58nvg2s3hbai4_choose_interface_config()
[all …]
H A Dnand_timings.c27 .timings.sdr = {
72 .timings.sdr = {
117 .timings.sdr = {
162 .timings.sdr = {
207 .timings.sdr = {
252 .timings.sdr = {
550 /* All NAND chips share the same reset data interface: SDR mode 0 */
557 * onfi_find_closest_sdr_mode - Derive the closest ONFI SDR timing mode given a
568 onfi_timings = &onfi_sdr_timings[mode].timings.sdr; in onfi_find_closest_sdr_mode()
646 * onfi_fill_sdr_interface_config - Initialize a SDR interface config from a
[all …]
H A Dcadence-nand-controller.c2400 const struct nand_sdr_timings *sdr) in cadence_nand_setup_sdr_interface() argument
2431 tdvw_min = sdr->tREA_max + board_delay_skew_max; in cadence_nand_setup_sdr_interface()
2437 * for SDR timing modes 1, 2, 3, 4 and 5. in cadence_nand_setup_sdr_interface()
2438 * If clk_period is 20ns the condition is met only for SDR timing in cadence_nand_setup_sdr_interface()
2441 if (sdr->tRC_min <= clk_period && in cadence_nand_setup_sdr_interface()
2442 sdr->tRP_min <= (clk_period / 2) && in cadence_nand_setup_sdr_interface()
2443 sdr->tREH_min <= (clk_period / 2)) { in cadence_nand_setup_sdr_interface()
2446 tdvw = calc_tdvw(trp_cnt, clk_period, sdr->tRHOH_min, in cadence_nand_setup_sdr_interface()
2447 sdr->tREA_max, ext_rd_mode); in cadence_nand_setup_sdr_interface()
2448 tdvw_max = calc_tdvw_max(trp_cnt, clk_period, sdr->tRHOH_min, in cadence_nand_setup_sdr_interface()
[all …]
H A Dams-delta.c198 const struct nand_sdr_timings *sdr = nand_get_sdr_timings(cf); in gpio_nand_setup_interface() local
201 if (IS_ERR(sdr)) in gpio_nand_setup_interface()
202 return PTR_ERR(sdr); in gpio_nand_setup_interface()
208 priv->tRP = DIV_ROUND_UP(sdr->tRP_min, 1000); in gpio_nand_setup_interface()
212 priv->tWP = DIV_ROUND_UP(sdr->tWP_min, 1000); in gpio_nand_setup_interface()
H A Dmxic_nand.c458 const struct nand_sdr_timings *sdr; in mxic_nfc_setup_interface() local
462 sdr = nand_get_sdr_timings(conf); in mxic_nfc_setup_interface()
463 if (IS_ERR(sdr)) in mxic_nfc_setup_interface()
464 return PTR_ERR(sdr); in mxic_nfc_setup_interface()
469 freq = NSEC_PER_SEC / (sdr->tRC_min / 1000); in mxic_nfc_setup_interface()
475 if (sdr->tRC_min < 30000) in mxic_nfc_setup_interface()
/linux/arch/arm/mach-socfpga/
H A Dself-refresh.S27 * sdr.ctrlcfg.lowpwreq.selfrfshmask
28 * sdr.ctrlcfg.lowpwrtiming.clkdisablecycles
29 * sdr.ctrlcfg.dramtiming4.selfrfshexit
53 /* Enable self refresh: set sdr.ctrlgrp.lowpwreq.selfrshreq = 1 */
58 /* Poll until sdr.ctrlgrp.lowpwrack.selfrfshack == 1 or hit max loops */
89 /* Disable self-refresh: set sdr.ctrlgrp.lowpwreq.selfrshreq = 0 */
94 /* Poll until sdr.ctrlgrp.lowpwrack.selfrfshack == 0 or hit max loops */
/linux/arch/powerpc/boot/
H A D4xx.c471 unsigned int sdr; in eplike_fixup_uart_clk() local
476 sdr = SDR0_READ(DCRN_SDR0_UART0); in eplike_fixup_uart_clk()
479 sdr = SDR0_READ(DCRN_SDR0_UART1); in eplike_fixup_uart_clk()
482 sdr = SDR0_READ(DCRN_SDR0_UART2); in eplike_fixup_uart_clk()
485 sdr = SDR0_READ(DCRN_SDR0_UART3); in eplike_fixup_uart_clk()
491 if (sdr & 0x00800000u) in eplike_fixup_uart_clk()
494 clock = plb_clk / __fix_zero(sdr & 0xff, 256); in eplike_fixup_uart_clk()
/linux/arch/arm/mach-omap2/
H A Dsram242x.S131 * r0 = [PRCM_FULL | PRCM_HALF] r1 = SDRC_DLLA_CTRL value r2 = [DDR | SDR]
132 * PRCM_FULL = 2, PRCM_HALF = 1, DDR = 1, SDR = 0
138 mcr p15, 0, r3, c7, c10, 4 @ memory barrier, finish ARM SDR/DDR
172 cmp r2, #0x1 @ (SDR or DDR) do we need to adjust DLL
173 bne freq_out @ leave if SDR, no DLL function
H A Dsram243x.S131 * r0 = [PRCM_FULL | PRCM_HALF] r1 = SDRC_DLLA_CTRL value r2 = [DDR | SDR]
132 * PRCM_FULL = 2, PRCM_HALF = 1, DDR = 1, SDR = 0
138 mcr p15, 0, r3, c7, c10, 4 @ memory barrier, finish ARM SDR/DDR
172 cmp r2, #0x1 @ (SDR or DDR) do we need to adjust DLL
173 bne freq_out @ leave if SDR, no DLL function
H A Dsleep24xx.S55 mcr p15, 0, r3, c7, c10, 4 @ memory barrier, hope SDR/DDR finished
75 movs r0, r0 @ see if DDR or SDR
/linux/drivers/gpu/drm/amd/display/dc/inc/hw/
H A Ddwb.h91 DWB_SRGB_BT709 = 0, //SDR
97 DWB_SRGB = 0, //SDR
98 DWB_BT709 = 1, //SDR
/linux/arch/arm/boot/dts/samsung/
H A Dexynos5260-xyref5260.dts99 samsung,dw-mshc-sdr-timing = <0 4>;
111 samsung,dw-mshc-sdr-timing = <2 3>;
H A Dexynos5410-smdk5410.dts71 samsung,dw-mshc-sdr-timing = <2 3>;
81 samsung,dw-mshc-sdr-timing = <2 3>;
/linux/arch/powerpc/boot/dts/
H A Dredwood.dts95 SDR0: sdr {
96 compatible = "ibm,sdr-460sx";
249 sdr-base = <0x300>;
290 sdr-base = <0x340>;
331 sdr-base = <0x370>;
H A Dkatmai.dts102 SDR0: sdr {
103 compatible = "ibm,sdr-440spe";
333 sdr-base = <0x300>;
374 sdr-base = <0x340>;
415 sdr-base = <0x370>;
/linux/drivers/media/usb/airspy/
H A DKconfig7 This is a video4linux2 driver for AirSpy SDR device.
/linux/drivers/media/usb/hackrf/
H A DKconfig7 This is a video4linux2 driver for HackRF SDR device.
/linux/arch/powerpc/include/asm/
H A Ddcr-regs.h3 * Common DCR / SDR / CPR register definitions used on various IBM/AMCC
72 /* SDR for 405EZ */
/linux/Documentation/devicetree/bindings/input/
H A De3x0-button.txt3 This module is part of the NI Ettus Research USRP E3x0 SDR.

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