xref: /linux/Documentation/devicetree/bindings/ufs/qcom,sa8255p-ufshc.yaml (revision fab183d632628381b466a41479489541ac0e29a0) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/ufs/qcom,sa8255p-ufshc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm SA8255P UFS Host Controller
8
9maintainers:
10  - Ram Kumar Dwivedi <ram.dwivedi@oss.qualcomm.com>
11
12properties:
13  compatible:
14    oneOf:
15      - const: qcom,sa8255p-ufshc
16      - items:
17          - const: qcom,sa8797p-ufshc
18          - const: qcom,sa8255p-ufshc
19
20  reg:
21    minItems: 1
22    maxItems: 2
23
24  reg-names:
25    minItems: 1
26    items:
27      - const: std
28      - const: mcq
29
30  interrupts:
31    maxItems: 1
32
33  iommus:
34    maxItems: 1
35
36  dma-coherent: true
37
38  power-domains:
39    maxItems: 1
40
41required:
42  - compatible
43  - reg
44  - interrupts
45  - power-domains
46  - iommus
47  - dma-coherent
48
49allOf:
50  - $ref: ufs-common.yaml
51
52unevaluatedProperties: false
53
54examples:
55  - |
56    #include <dt-bindings/interrupt-controller/arm-gic.h>
57
58    ufshc@1d84000 {
59        compatible = "qcom,sa8255p-ufshc";
60        reg = <0x01d84000 0x3000>;
61        interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
62        lanes-per-direction = <2>;
63
64        iommus = <&apps_smmu 0x100 0x0>;
65        power-domains = <&scmi3_pd 0>;
66        dma-coherent;
67    };
68