Home
last modified time | relevance | path

Searched +full:sci +full:- +full:inta (Results 1 – 16 of 16) sorted by relevance

/freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/
H A Dti,sci-inta.txt4 The Interrupt Aggregator (INTA) provides a centralized machine
11 +-----------------------------------------+
13 | +--------------+ +------------+ |
14 m ------>| | vint | bit | | 0 |.....|63| vint0 |
15 . | +--------------+ +------------+ | +------+
17 Globalevents ------>| . . |------>| IRQ |
19 . | . . | +------+
20 n ------>| +--------------+ +------------+ |
22 | +--------------+ +------------+ |
24 +-----------------------------------------+
[all …]
H A Dti,sci-inta.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/ti,sci-inta.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lokesh Vutla <lokeshvutla@ti.com>
13 - $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml#
16 The Interrupt Aggregator (INTA) provides a centralized machine
22 +-----------------------------------------+
24 | +--------------+ +------------+ |
25 m ------>| | vint | bit | | 0 |.....|63| vint0 |
[all …]
H A Dti,sci-intr.txt10 +----------------------+
12 +-------+ | +------+ +-----+ |
13 | GPIO |----------->| | irq0 | | 0 | | Host IRQ
14 +-------+ | +------+ +-----+ | controller
15 | . . | +-------+
16 +-------+ | . . |----->| IRQ |
17 | INTA |----------->| . . | +-------+
18 +-------+ | . +-----+ |
19 | +------+ | N | |
20 | | irqM | +-----+ |
[all …]
H A Dti,sci-intr.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/ti,sci-intr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lokesh Vutla <lokeshvutla@ti.com>
13 - $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml#
22 +----------------------+
24 +-------+ | +------+ +-----+ |
25 | GPIO |----------->| | irq0 | | 0 | | Host IRQ
26 +-------+ | +------+ +-----+ | controller
[all …]
/freebsd/sys/contrib/device-tree/Bindings/soc/ti/
H A Dk3-ringacc.txt17 - compatible : Must be "ti,am654-navss-ringacc";
18 - reg : Should contain register location and length of the following
20 - reg-names : should be
21 "rt" - The RA Ring Real-time Control/Status Registers
22 "fifos" - The RA Queues Registers
23 "proxy_gcfg" - The RA Proxy Global Config Registers
24 "proxy_target" - The RA Proxy Datapath Registers
25 - ti,num-rings : Number of rings supported by RA
26 - ti,sci-rm-range-gp-rings : TI-SCI RM subtype for GP ring range
27 - ti,sci : phandle on TI-SCI compatible System controller node
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/ti/
H A Dk3-am62a-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
10 compatible = "mmio-sram";
12 #address-cells = <1>;
13 #size-cells = <1>;
17 gic500: interrupt-controller@1800000 {
18 compatible = "arm,gic-v3";
25 #address-cells = <2>;
26 #size-cells = <2>;
28 #interrupt-cells = <3>;
[all …]
H A Dk3-am62p-j722s-common-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
10 compatible = "mmio-sram";
11 #address-cells = <1>;
12 #size-cells = <1>;
15 gic500: interrupt-controller@1800000 {
16 compatible = "arm,gic-v3";
17 #address-cells = <2>;
18 #size-cells = <2>;
20 #interrupt-cells = <3>;
[all …]
H A Dk3-am62-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
10 compatible = "mmio-sram";
12 #address-cells = <1>;
13 #size-cells = <1>;
17 gic500: interrupt-controller@1800000 {
18 compatible = "arm,gic-v3";
19 #address-cells = <2>;
20 #size-cells = <2>;
22 #interrupt-cells = <3>;
[all …]
H A Dk3-am64-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/phy/phy-cadence.h>
9 #include <dt-bindings/phy/phy-ti.h>
12 serdes_refclk: clock-cmnrefclk {
13 #clock-cells = <0>;
14 compatible = "fixed-clock";
15 clock-frequency = <0>;
21 compatible = "mmio-sram";
23 #address-cells = <1>;
[all …]
H A Dk3-j7200-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
9 serdes_refclk: serdes-refclk {
10 #clock-cells = <0>;
11 compatible = "fixed-clock";
17 compatible = "mmio-sram";
19 #address-cells = <1>;
20 #size-cells = <1>;
23 atf-sram@0 {
28 scm_conf: scm-conf@100000 {
[all …]
H A Dk3-j721s2-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/phy/phy-cadence.h>
9 #include <dt-bindings/phy/phy-ti.h>
12 serdes_refclk: clock-cmnrefclk {
13 #clock-cells = <0>;
14 compatible = "fixed-clock";
15 clock-frequency = <0>;
21 compatible = "mmio-sram";
23 #address-cells = <1>;
[all …]
H A Dk3-am65-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/
7 #include <dt-bindings/phy/phy-am654-serdes.h>
11 compatible = "mmio-sram";
13 #address-cells = <1>;
14 #size-cells = <1>;
17 atf-sram@0 {
21 sysfw-sram@f0000 {
25 l3cache-sram@100000 {
30 gic500: interrupt-controller@1800000 {
[all …]
H A Dk3-j784s4-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/mux/mux.h>
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/phy/phy-ti.h>
12 #include "k3-serdes.h"
15 serdes_refclk: clock-serdes {
16 #clock-cells = <0>;
17 compatible = "fixed-clock";
25 compatible = "mmio-sram";
[all …]
H A Dk3-j721e-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/
7 #include <dt-bindings/phy/phy.h>
8 #include <dt-bindings/phy/phy-ti.h>
9 #include <dt-bindings/mux/mux.h>
11 #include "k3-serdes.h"
14 cmn_refclk: clock-cmnrefclk {
15 #clock-cells = <0>;
16 compatible = "fixed-clock";
17 clock-frequency = <0>;
[all …]
/freebsd/sys/dev/isci/scil/
H A Dscic_sds_controller.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause OR GPL-2.0
9 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
22 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
28 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
133 (((U32)(SMU_CQGR_CYCLE_BIT & (x))) << (31 - SMU_COMPLETION_QUEUE_GET_CYCLE_BIT_SHIFT))
154 (controller)->completion_queue_entries, \
167 (controller)->completion_event_entries, \
171 //****************************************************************************-
173 //****************************************************************************-
[all …]
/freebsd/contrib/file/magic/Magdir/
H A Dimages2 #------------------------------------------------------------------------------
4 # images: file(1) magic for image formats (see also "iff", and "c-lang" for
9 # merging several one- and two-line files into here.
13 # Targa - matches `povray', `ppmtotga' and `xv' outputs
19 # Note: called by DROID "Truevision TGA Bitmap" version 1.0 via PUID x-fmt/367
23 # or theoretically 2-128 reserved for use by Truevision or 128-255 may be used for developer applic…
32 # Targa image data (strength=70=110-40) before some Commodore disc image (strength=70=70+0 ./c64) l…
35 !:strength -40
37 #>(2.S-2) belong !0x28632943
52 >>>>>>>0 use tga-image
[all …]