Lines Matching +full:sci +full:- +full:inta
1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/mux/mux.h>
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/phy/phy-ti.h>
12 #include "k3-serdes.h"
15 serdes_refclk: clock-serdes {
16 #clock-cells = <0>;
17 compatible = "fixed-clock";
25 compatible = "mmio-sram";
27 #address-cells = <1>;
28 #size-cells = <1>;
31 atf-sram@0 {
35 tifs-sram@1f0000 {
39 l3cache-sram@200000 {
45 compatible = "simple-bus";
47 #address-cells = <1>;
48 #size-cells = <1>;
51 serdes_ln_ctrl: mux-controller@4080 {
52 compatible = "reg-mux";
54 #mux-control-cells = <1>;
55 mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
61 idle-states = <J784S4_SERDES0_LANE0_PCIE1_LANE0>,
80 gic500: interrupt-controller@1800000 {
81 compatible = "arm,gic-v3";
82 #address-cells = <2>;
83 #size-cells = <2>;
85 #interrupt-cells = <3>;
86 interrupt-controller;
96 gic_its: msi-controller@1820000 {
97 compatible = "arm,gic-v3-its";
99 socionext,synquacer-pre-its = <0x1000000 0x400000>;
100 msi-controller;
101 #msi-cells = <1>;
105 main_gpio_intr: interrupt-controller@a00000 {
106 compatible = "ti,sci-intr";
108 ti,intr-trigger-type = <1>;
109 interrupt-controller;
110 interrupt-parent = <&gic500>;
111 #interrupt-cells = <1>;
112 ti,sci = <&sms>;
113 ti,sci-dev-id = <10>;
114 ti,interrupt-ranges = <8 392 56>;
118 compatible = "pinctrl-single";
121 #pinctrl-cells = <1>;
122 pinctrl-single,register-width = <32>;
123 pinctrl-single,function-mask = <0xffffffff>;
128 compatible = "pinctrl-single";
130 #pinctrl-cells = <1>;
131 pinctrl-single,register-width = <32>;
132 pinctrl-single,function-mask = <0x00000007>;
137 compatible = "pinctrl-single";
139 #pinctrl-cells = <1>;
140 pinctrl-single,register-width = <32>;
141 pinctrl-single,function-mask = <0x0000001f>;
145 compatible = "ti,j721e-sa2ul";
147 power-domains = <&k3_pds 369 TI_SCI_PD_EXCLUSIVE>;
148 #address-cells = <2>;
149 #size-cells = <2>;
154 dma-names = "tx", "rx1", "rx2";
157 compatible = "inside-secure,safexcel-eip76";
164 compatible = "ti,am654-timer";
168 clock-names = "fck";
169 assigned-clocks = <&k3_clks 97 2>;
170 assigned-clock-parents = <&k3_clks 97 3>;
171 power-domains = <&k3_pds 97 TI_SCI_PD_EXCLUSIVE>;
172 ti,timer-pwm;
176 compatible = "ti,am654-timer";
180 clock-names = "fck";
181 assigned-clocks = <&k3_clks 98 2>;
182 assigned-clock-parents = <&k3_clks 98 3>;
183 power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>;
184 ti,timer-pwm;
188 compatible = "ti,am654-timer";
192 clock-names = "fck";
193 assigned-clocks = <&k3_clks 99 2>;
194 assigned-clock-parents = <&k3_clks 99 3>;
195 power-domains = <&k3_pds 99 TI_SCI_PD_EXCLUSIVE>;
196 ti,timer-pwm;
200 compatible = "ti,am654-timer";
204 clock-names = "fck";
205 assigned-clocks = <&k3_clks 100 2>;
206 assigned-clock-parents = <&k3_clks 100 3>;
207 power-domains = <&k3_pds 100 TI_SCI_PD_EXCLUSIVE>;
208 ti,timer-pwm;
212 compatible = "ti,am654-timer";
216 clock-names = "fck";
217 assigned-clocks = <&k3_clks 101 2>;
218 assigned-clock-parents = <&k3_clks 101 3>;
219 power-domains = <&k3_pds 101 TI_SCI_PD_EXCLUSIVE>;
220 ti,timer-pwm;
224 compatible = "ti,am654-timer";
228 clock-names = "fck";
229 assigned-clocks = <&k3_clks 102 2>;
230 assigned-clock-parents = <&k3_clks 102 3>;
231 power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
232 ti,timer-pwm;
236 compatible = "ti,am654-timer";
240 clock-names = "fck";
241 assigned-clocks = <&k3_clks 103 2>;
242 assigned-clock-parents = <&k3_clks 103 3>;
243 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
244 ti,timer-pwm;
248 compatible = "ti,am654-timer";
252 clock-names = "fck";
253 assigned-clocks = <&k3_clks 104 2>;
254 assigned-clock-parents = <&k3_clks 104 3>;
255 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
256 ti,timer-pwm;
260 compatible = "ti,am654-timer";
264 clock-names = "fck";
265 assigned-clocks = <&k3_clks 105 2>;
266 assigned-clock-parents = <&k3_clks 105 3>;
267 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
268 ti,timer-pwm;
272 compatible = "ti,am654-timer";
276 clock-names = "fck";
277 assigned-clocks = <&k3_clks 106 2>;
278 assigned-clock-parents = <&k3_clks 106 3>;
279 power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
280 ti,timer-pwm;
284 compatible = "ti,am654-timer";
288 clock-names = "fck";
289 assigned-clocks = <&k3_clks 107 2>;
290 assigned-clock-parents = <&k3_clks 107 3>;
291 power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
292 ti,timer-pwm;
296 compatible = "ti,am654-timer";
300 clock-names = "fck";
301 assigned-clocks = <&k3_clks 108 2>;
302 assigned-clock-parents = <&k3_clks 108 3>;
303 power-domains = <&k3_pds 108 TI_SCI_PD_EXCLUSIVE>;
304 ti,timer-pwm;
308 compatible = "ti,am654-timer";
312 clock-names = "fck";
313 assigned-clocks = <&k3_clks 109 2>;
314 assigned-clock-parents = <&k3_clks 109 3>;
315 power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>;
316 ti,timer-pwm;
320 compatible = "ti,am654-timer";
324 clock-names = "fck";
325 assigned-clocks = <&k3_clks 110 2>;
326 assigned-clock-parents = <&k3_clks 110 3>;
327 power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>;
328 ti,timer-pwm;
332 compatible = "ti,am654-timer";
336 clock-names = "fck";
337 assigned-clocks = <&k3_clks 111 2>;
338 assigned-clock-parents = <&k3_clks 111 3>;
339 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
340 ti,timer-pwm;
344 compatible = "ti,am654-timer";
348 clock-names = "fck";
349 assigned-clocks = <&k3_clks 112 2>;
350 assigned-clock-parents = <&k3_clks 112 3>;
351 power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>;
352 ti,timer-pwm;
356 compatible = "ti,am654-timer";
360 clock-names = "fck";
361 assigned-clocks = <&k3_clks 113 2>;
362 assigned-clock-parents = <&k3_clks 113 3>;
363 power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
364 ti,timer-pwm;
368 compatible = "ti,am654-timer";
372 clock-names = "fck";
373 assigned-clocks = <&k3_clks 114 2>;
374 assigned-clock-parents = <&k3_clks 114 3>;
375 power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
376 ti,timer-pwm;
380 compatible = "ti,am654-timer";
384 clock-names = "fck";
385 assigned-clocks = <&k3_clks 115 2>;
386 assigned-clock-parents = <&k3_clks 115 3>;
387 power-domains = <&k3_pds 115 TI_SCI_PD_EXCLUSIVE>;
388 ti,timer-pwm;
392 compatible = "ti,am654-timer";
396 clock-names = "fck";
397 assigned-clocks = <&k3_clks 116 2>;
398 assigned-clock-parents = <&k3_clks 116 3>;
399 power-domains = <&k3_pds 116 TI_SCI_PD_EXCLUSIVE>;
400 ti,timer-pwm;
404 compatible = "ti,j721e-uart", "ti,am654-uart";
407 current-speed = <115200>;
409 clock-names = "fclk";
410 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
415 compatible = "ti,j721e-uart", "ti,am654-uart";
418 current-speed = <115200>;
420 clock-names = "fclk";
421 power-domains = <&k3_pds 388 TI_SCI_PD_EXCLUSIVE>;
426 compatible = "ti,j721e-uart", "ti,am654-uart";
429 current-speed = <115200>;
431 clock-names = "fclk";
432 power-domains = <&k3_pds 389 TI_SCI_PD_EXCLUSIVE>;
437 compatible = "ti,j721e-uart", "ti,am654-uart";
440 current-speed = <115200>;
442 clock-names = "fclk";
443 power-domains = <&k3_pds 390 TI_SCI_PD_EXCLUSIVE>;
448 compatible = "ti,j721e-uart", "ti,am654-uart";
451 current-speed = <115200>;
453 clock-names = "fclk";
454 power-domains = <&k3_pds 391 TI_SCI_PD_EXCLUSIVE>;
459 compatible = "ti,j721e-uart", "ti,am654-uart";
462 current-speed = <115200>;
464 clock-names = "fclk";
465 power-domains = <&k3_pds 392 TI_SCI_PD_EXCLUSIVE>;
470 compatible = "ti,j721e-uart", "ti,am654-uart";
473 current-speed = <115200>;
475 clock-names = "fclk";
476 power-domains = <&k3_pds 393 TI_SCI_PD_EXCLUSIVE>;
481 compatible = "ti,j721e-uart", "ti,am654-uart";
484 current-speed = <115200>;
486 clock-names = "fclk";
487 power-domains = <&k3_pds 394 TI_SCI_PD_EXCLUSIVE>;
492 compatible = "ti,j721e-uart", "ti,am654-uart";
495 current-speed = <115200>;
497 clock-names = "fclk";
498 power-domains = <&k3_pds 395 TI_SCI_PD_EXCLUSIVE>;
503 compatible = "ti,j721e-uart", "ti,am654-uart";
506 current-speed = <115200>;
508 clock-names = "fclk";
509 power-domains = <&k3_pds 396 TI_SCI_PD_EXCLUSIVE>;
514 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
516 gpio-controller;
517 #gpio-cells = <2>;
518 interrupt-parent = <&main_gpio_intr>;
520 interrupt-controller;
521 #interrupt-cells = <2>;
523 ti,davinci-gpio-unbanked = <0>;
524 power-domains = <&k3_pds 163 TI_SCI_PD_EXCLUSIVE>;
526 clock-names = "gpio";
531 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
533 gpio-controller;
534 #gpio-cells = <2>;
535 interrupt-parent = <&main_gpio_intr>;
537 interrupt-controller;
538 #interrupt-cells = <2>;
540 ti,davinci-gpio-unbanked = <0>;
541 power-domains = <&k3_pds 164 TI_SCI_PD_EXCLUSIVE>;
543 clock-names = "gpio";
548 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
550 gpio-controller;
551 #gpio-cells = <2>;
552 interrupt-parent = <&main_gpio_intr>;
554 interrupt-controller;
555 #interrupt-cells = <2>;
557 ti,davinci-gpio-unbanked = <0>;
558 power-domains = <&k3_pds 165 TI_SCI_PD_EXCLUSIVE>;
560 clock-names = "gpio";
565 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
567 gpio-controller;
568 #gpio-cells = <2>;
569 interrupt-parent = <&main_gpio_intr>;
571 interrupt-controller;
572 #interrupt-cells = <2>;
574 ti,davinci-gpio-unbanked = <0>;
575 power-domains = <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
577 clock-names = "gpio";
582 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
585 #address-cells = <1>;
586 #size-cells = <0>;
588 clock-names = "fck";
589 power-domains = <&k3_pds 270 TI_SCI_PD_EXCLUSIVE>;
594 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
597 #address-cells = <1>;
598 #size-cells = <0>;
600 clock-names = "fck";
601 power-domains = <&k3_pds 271 TI_SCI_PD_EXCLUSIVE>;
606 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
609 #address-cells = <1>;
610 #size-cells = <0>;
612 clock-names = "fck";
613 power-domains = <&k3_pds 272 TI_SCI_PD_EXCLUSIVE>;
618 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
621 #address-cells = <1>;
622 #size-cells = <0>;
624 clock-names = "fck";
625 power-domains = <&k3_pds 273 TI_SCI_PD_EXCLUSIVE>;
630 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
633 #address-cells = <1>;
634 #size-cells = <0>;
636 clock-names = "fck";
637 power-domains = <&k3_pds 274 TI_SCI_PD_EXCLUSIVE>;
642 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
645 #address-cells = <1>;
646 #size-cells = <0>;
648 clock-names = "fck";
649 power-domains = <&k3_pds 275 TI_SCI_PD_EXCLUSIVE>;
654 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
657 #address-cells = <1>;
658 #size-cells = <0>;
660 clock-names = "fck";
661 power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>;
666 compatible = "ti,j721e-sdhci-8bit";
670 power-domains = <&k3_pds 140 TI_SCI_PD_EXCLUSIVE>;
672 clock-names = "clk_ahb", "clk_xin";
673 assigned-clocks = <&k3_clks 140 2>;
674 assigned-clock-parents = <&k3_clks 140 3>;
675 bus-width = <8>;
676 ti,otap-del-sel-legacy = <0x0>;
677 ti,otap-del-sel-mmc-hs = <0x0>;
678 ti,otap-del-sel-ddr52 = <0x6>;
679 ti,otap-del-sel-hs200 = <0x8>;
680 ti,otap-del-sel-hs400 = <0x5>;
681 ti,itap-del-sel-legacy = <0x10>;
682 ti,itap-del-sel-mmc-hs = <0xa>;
683 ti,strobe-sel = <0x77>;
684 ti,clkbuf-sel = <0x7>;
685 ti,trm-icp = <0x8>;
686 mmc-ddr-1_8v;
687 mmc-hs200-1_8v;
688 mmc-hs400-1_8v;
689 dma-coherent;
694 compatible = "ti,j721e-sdhci-4bit";
698 power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>;
700 clock-names = "clk_ahb", "clk_xin";
701 assigned-clocks = <&k3_clks 141 4>;
702 assigned-clock-parents = <&k3_clks 141 5>;
703 bus-width = <4>;
704 ti,otap-del-sel-legacy = <0x0>;
705 ti,otap-del-sel-sd-hs = <0x0>;
706 ti,otap-del-sel-sdr12 = <0xf>;
707 ti,otap-del-sel-sdr25 = <0xf>;
708 ti,otap-del-sel-sdr50 = <0xc>;
709 ti,otap-del-sel-sdr104 = <0x5>;
710 ti,otap-del-sel-ddr50 = <0xc>;
711 ti,itap-del-sel-legacy = <0x0>;
712 ti,itap-del-sel-sd-hs = <0x0>;
713 ti,itap-del-sel-sdr12 = <0x0>;
714 ti,itap-del-sel-sdr25 = <0x0>;
715 ti,itap-del-sel-ddr50 = <0x2>;
716 ti,clkbuf-sel = <0x7>;
717 ti,trm-icp = <0x8>;
718 dma-coherent;
719 sdhci-caps-mask = <0x00000003 0x00000000>;
720 no-1-8-v;
725 compatible = "ti,j784s4-wiz-10g";
726 #address-cells = <1>;
727 #size-cells = <1>;
728 power-domains = <&k3_pds 404 TI_SCI_PD_EXCLUSIVE>;
730 clock-names = "fck", "core_ref_clk", "ext_ref_clk", "core_ref1_clk";
731 assigned-clocks = <&k3_clks 404 6>;
732 assigned-clock-parents = <&k3_clks 404 10>;
733 num-lanes = <4>;
734 #reset-cells = <1>;
735 #clock-cells = <1>;
740 compatible = "ti,j721e-serdes-10g";
742 reg-names = "torrent_phy";
744 reset-names = "torrent_reset";
747 clock-names = "refclk", "phy_en_refclk";
748 assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
751 assigned-clock-parents = <&k3_clks 404 6>,
754 #address-cells = <1>;
755 #size-cells = <0>;
756 #clock-cells = <1>;
762 compatible = "ti,j784s4-wiz-10g";
763 #address-cells = <1>;
764 #size-cells = <1>;
765 power-domains = <&k3_pds 405 TI_SCI_PD_EXCLUSIVE>;
767 clock-names = "fck", "core_ref_clk", "ext_ref_clk", "core_ref1_clk";
768 assigned-clocks = <&k3_clks 405 6>;
769 assigned-clock-parents = <&k3_clks 405 10>;
770 num-lanes = <4>;
771 #reset-cells = <1>;
772 #clock-cells = <1>;
777 compatible = "ti,j721e-serdes-10g";
779 reg-names = "torrent_phy";
781 reset-names = "torrent_reset";
784 clock-names = "refclk", "phy_en_refclk";
785 assigned-clocks = <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>,
788 assigned-clock-parents = <&k3_clks 405 6>,
791 #address-cells = <1>;
792 #size-cells = <0>;
793 #clock-cells = <1>;
799 compatible = "ti,j784s4-wiz-10g";
800 #address-cells = <1>;
801 #size-cells = <1>;
802 power-domains = <&k3_pds 406 TI_SCI_PD_EXCLUSIVE>;
804 clock-names = "fck", "core_ref_clk", "ext_ref_clk", "core_ref1_clk";
805 assigned-clocks = <&k3_clks 406 6>;
806 assigned-clock-parents = <&k3_clks 406 10>;
807 num-lanes = <4>;
808 #reset-cells = <1>;
809 #clock-cells = <1>;
814 compatible = "ti,j721e-serdes-10g";
816 reg-names = "torrent_phy";
818 reset-names = "torrent_reset";
821 clock-names = "refclk", "phy_en_refclk";
822 assigned-clocks = <&serdes_wiz2 TI_WIZ_PLL0_REFCLK>,
825 assigned-clock-parents = <&k3_clks 406 6>,
828 #address-cells = <1>;
829 #size-cells = <0>;
830 #clock-cells = <1>;
836 compatible = "ti,j784s4-wiz-10g";
837 #address-cells = <1>;
838 #size-cells = <1>;
839 power-domains = <&k3_pds 407 TI_SCI_PD_EXCLUSIVE>;
841 clock-names = "fck", "core_ref_clk", "ext_ref_clk", "core_ref1_clk";
842 assigned-clocks = <&k3_clks 407 6>;
843 assigned-clock-parents = <&k3_clks 407 10>;
844 num-lanes = <4>;
845 #reset-cells = <1>;
846 #clock-cells = <1>;
856 compatible = "ti,j721e-serdes-10g";
859 reg-names = "torrent_phy";
861 reset-names = "torrent_reset";
864 clock-names = "refclk", "phy_en_refclk";
865 assigned-clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>,
868 assigned-clock-parents = <&k3_clks 407 6>,
871 #address-cells = <1>;
872 #size-cells = <0>;
873 #clock-cells = <1>;
879 bootph-all;
880 compatible = "simple-bus";
881 #address-cells = <2>;
882 #size-cells = <2>;
884 ti,sci-dev-id = <280>;
885 dma-coherent;
886 dma-ranges;
888 main_navss_intr: interrupt-controller@310e0000 {
889 compatible = "ti,sci-intr";
891 ti,intr-trigger-type = <4>;
892 interrupt-controller;
893 interrupt-parent = <&gic500>;
894 #interrupt-cells = <1>;
895 ti,sci = <&sms>;
896 ti,sci-dev-id = <283>;
897 ti,interrupt-ranges = <0 64 64>,
902 main_udmass_inta: msi-controller@33d00000 {
903 compatible = "ti,sci-inta";
905 interrupt-controller;
906 #interrupt-cells = <0>;
907 interrupt-parent = <&main_navss_intr>;
908 msi-controller;
909 ti,sci = <&sms>;
910 ti,sci-dev-id = <321>;
911 ti,interrupt-ranges = <0 0 256>;
912 ti,unmapped-event-sources = <&main_bcdma_csi>;
916 bootph-all;
917 compatible = "ti,am654-secure-proxy";
918 #mbox-cells = <1>;
919 reg-names = "target_data", "rt", "scfg";
923 interrupt-names = "rx_011";
928 compatible = "ti,am654-hwspinlock";
930 #hwlock-cells = <1>;
934 compatible = "ti,am654-mailbox";
936 #mbox-cells = <1>;
937 ti,mbox-num-users = <4>;
938 ti,mbox-num-fifos = <16>;
939 interrupt-parent = <&main_navss_intr>;
944 compatible = "ti,am654-mailbox";
946 #mbox-cells = <1>;
947 ti,mbox-num-users = <4>;
948 ti,mbox-num-fifos = <16>;
949 interrupt-parent = <&main_navss_intr>;
954 compatible = "ti,am654-mailbox";
956 #mbox-cells = <1>;
957 ti,mbox-num-users = <4>;
958 ti,mbox-num-fifos = <16>;
959 interrupt-parent = <&main_navss_intr>;
964 compatible = "ti,am654-mailbox";
966 #mbox-cells = <1>;
967 ti,mbox-num-users = <4>;
968 ti,mbox-num-fifos = <16>;
969 interrupt-parent = <&main_navss_intr>;
974 compatible = "ti,am654-mailbox";
976 #mbox-cells = <1>;
977 ti,mbox-num-users = <4>;
978 ti,mbox-num-fifos = <16>;
979 interrupt-parent = <&main_navss_intr>;
984 compatible = "ti,am654-mailbox";
986 #mbox-cells = <1>;
987 ti,mbox-num-users = <4>;
988 ti,mbox-num-fifos = <16>;
989 interrupt-parent = <&main_navss_intr>;
994 compatible = "ti,am654-mailbox";
996 #mbox-cells = <1>;
997 ti,mbox-num-users = <4>;
998 ti,mbox-num-fifos = <16>;
999 interrupt-parent = <&main_navss_intr>;
1004 compatible = "ti,am654-mailbox";
1006 #mbox-cells = <1>;
1007 ti,mbox-num-users = <4>;
1008 ti,mbox-num-fifos = <16>;
1009 interrupt-parent = <&main_navss_intr>;
1014 compatible = "ti,am654-mailbox";
1016 #mbox-cells = <1>;
1017 ti,mbox-num-users = <4>;
1018 ti,mbox-num-fifos = <16>;
1019 interrupt-parent = <&main_navss_intr>;
1024 compatible = "ti,am654-mailbox";
1026 #mbox-cells = <1>;
1027 ti,mbox-num-users = <4>;
1028 ti,mbox-num-fifos = <16>;
1029 interrupt-parent = <&main_navss_intr>;
1034 compatible = "ti,am654-mailbox";
1036 #mbox-cells = <1>;
1037 ti,mbox-num-users = <4>;
1038 ti,mbox-num-fifos = <16>;
1039 interrupt-parent = <&main_navss_intr>;
1044 compatible = "ti,am654-mailbox";
1046 #mbox-cells = <1>;
1047 ti,mbox-num-users = <4>;
1048 ti,mbox-num-fifos = <16>;
1049 interrupt-parent = <&main_navss_intr>;
1054 compatible = "ti,am654-mailbox";
1056 #mbox-cells = <1>;
1057 ti,mbox-num-users = <4>;
1058 ti,mbox-num-fifos = <16>;
1059 interrupt-parent = <&main_navss_intr>;
1064 compatible = "ti,am654-mailbox";
1066 #mbox-cells = <1>;
1067 ti,mbox-num-users = <4>;
1068 ti,mbox-num-fifos = <16>;
1069 interrupt-parent = <&main_navss_intr>;
1074 compatible = "ti,am654-mailbox";
1076 #mbox-cells = <1>;
1077 ti,mbox-num-users = <4>;
1078 ti,mbox-num-fifos = <16>;
1079 interrupt-parent = <&main_navss_intr>;
1084 compatible = "ti,am654-mailbox";
1086 #mbox-cells = <1>;
1087 ti,mbox-num-users = <4>;
1088 ti,mbox-num-fifos = <16>;
1089 interrupt-parent = <&main_navss_intr>;
1094 compatible = "ti,am654-mailbox";
1096 #mbox-cells = <1>;
1097 ti,mbox-num-users = <4>;
1098 ti,mbox-num-fifos = <16>;
1099 interrupt-parent = <&main_navss_intr>;
1104 compatible = "ti,am654-mailbox";
1106 #mbox-cells = <1>;
1107 ti,mbox-num-users = <4>;
1108 ti,mbox-num-fifos = <16>;
1109 interrupt-parent = <&main_navss_intr>;
1114 compatible = "ti,am654-mailbox";
1116 #mbox-cells = <1>;
1117 ti,mbox-num-users = <4>;
1118 ti,mbox-num-fifos = <16>;
1119 interrupt-parent = <&main_navss_intr>;
1124 compatible = "ti,am654-mailbox";
1126 #mbox-cells = <1>;
1127 ti,mbox-num-users = <4>;
1128 ti,mbox-num-fifos = <16>;
1129 interrupt-parent = <&main_navss_intr>;
1134 compatible = "ti,am654-mailbox";
1136 #mbox-cells = <1>;
1137 ti,mbox-num-users = <4>;
1138 ti,mbox-num-fifos = <16>;
1139 interrupt-parent = <&main_navss_intr>;
1144 compatible = "ti,am654-mailbox";
1146 #mbox-cells = <1>;
1147 ti,mbox-num-users = <4>;
1148 ti,mbox-num-fifos = <16>;
1149 interrupt-parent = <&main_navss_intr>;
1154 compatible = "ti,am654-mailbox";
1156 #mbox-cells = <1>;
1157 ti,mbox-num-users = <4>;
1158 ti,mbox-num-fifos = <16>;
1159 interrupt-parent = <&main_navss_intr>;
1164 compatible = "ti,am654-mailbox";
1166 #mbox-cells = <1>;
1167 ti,mbox-num-users = <4>;
1168 ti,mbox-num-fifos = <16>;
1169 interrupt-parent = <&main_navss_intr>;
1174 compatible = "ti,am654-navss-ringacc";
1180 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
1181 ti,num-rings = <1024>;
1182 ti,sci-rm-range-gp-rings = <0x1>;
1183 ti,sci = <&sms>;
1184 ti,sci-dev-id = <315>;
1185 msi-parent = <&main_udmass_inta>;
1188 main_udmap: dma-controller@31150000 {
1189 compatible = "ti,j721e-navss-main-udmap";
1196 reg-names = "gcfg", "rchanrt", "tchanrt",
1198 msi-parent = <&main_udmass_inta>;
1199 #dma-cells = <1>;
1201 ti,sci = <&sms>;
1202 ti,sci-dev-id = <319>;
1205 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
1208 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
1211 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
1214 main_bcdma_csi: dma-controller@311a0000 {
1215 compatible = "ti,j721s2-dmss-bcdma-csi";
1220 reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt";
1221 msi-parent = <&main_udmass_inta>;
1222 #dma-cells = <3>;
1223 ti,sci = <&sms>;
1224 ti,sci-dev-id = <281>;
1225 ti,sci-rm-range-rchan = <0x21>;
1226 ti,sci-rm-range-tchan = <0x22>;
1231 compatible = "ti,j721e-cpts";
1233 reg-names = "cpts";
1235 clock-names = "cpts";
1236 assigned-clocks = <&k3_clks 62 3>; /* CPTS_RFT_CLK */
1237 assigned-clock-parents = <&k3_clks 62 5>; /* MAIN_0_HSDIV6_CLK */
1238 interrupts-extended = <&main_navss_intr 391>;
1239 interrupt-names = "cpts";
1240 ti,cpts-periodic-outputs = <6>;
1241 ti,cpts-ext-ts-inputs = <8>;
1249 reg-names = "m_can", "message_ram";
1250 power-domains = <&k3_pds 245 TI_SCI_PD_EXCLUSIVE>;
1252 clock-names = "hclk", "cclk";
1255 interrupt-names = "int0", "int1";
1256 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
1264 reg-names = "m_can", "message_ram";
1265 power-domains = <&k3_pds 246 TI_SCI_PD_EXCLUSIVE>;
1267 clock-names = "hclk", "cclk";
1270 interrupt-names = "int0", "int1";
1271 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
1279 reg-names = "m_can", "message_ram";
1280 power-domains = <&k3_pds 247 TI_SCI_PD_EXCLUSIVE>;
1282 clock-names = "hclk", "cclk";
1285 interrupt-names = "int0", "int1";
1286 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
1294 reg-names = "m_can", "message_ram";
1295 power-domains = <&k3_pds 248 TI_SCI_PD_EXCLUSIVE>;
1297 clock-names = "hclk", "cclk";
1300 interrupt-names = "int0", "int1";
1301 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
1309 reg-names = "m_can", "message_ram";
1310 power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>;
1312 clock-names = "hclk", "cclk";
1315 interrupt-names = "int0", "int1";
1316 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
1324 reg-names = "m_can", "message_ram";
1325 power-domains = <&k3_pds 250 TI_SCI_PD_EXCLUSIVE>;
1327 clock-names = "hclk", "cclk";
1330 interrupt-names = "int0", "int1";
1331 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
1339 reg-names = "m_can", "message_ram";
1340 power-domains = <&k3_pds 251 TI_SCI_PD_EXCLUSIVE>;
1342 clock-names = "hclk", "cclk";
1345 interrupt-names = "int0", "int1";
1346 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
1354 reg-names = "m_can", "message_ram";
1355 power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>;
1357 clock-names = "hclk", "cclk";
1360 interrupt-names = "int0", "int1";
1361 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
1369 reg-names = "m_can", "message_ram";
1370 power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>;
1372 clock-names = "hclk", "cclk";
1375 interrupt-names = "int0", "int1";
1376 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
1384 reg-names = "m_can", "message_ram";
1385 power-domains = <&k3_pds 254 TI_SCI_PD_EXCLUSIVE>;
1387 clock-names = "hclk", "cclk";
1390 interrupt-names = "int0", "int1";
1391 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
1399 reg-names = "m_can", "message_ram";
1400 power-domains = <&k3_pds 255 TI_SCI_PD_EXCLUSIVE>;
1402 clock-names = "hclk", "cclk";
1405 interrupt-names = "int0", "int1";
1406 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
1414 reg-names = "m_can", "message_ram";
1415 power-domains = <&k3_pds 256 TI_SCI_PD_EXCLUSIVE>;
1417 clock-names = "hclk", "cclk";
1420 interrupt-names = "int0", "int1";
1421 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
1429 reg-names = "m_can", "message_ram";
1430 power-domains = <&k3_pds 257 TI_SCI_PD_EXCLUSIVE>;
1432 clock-names = "hclk", "cclk";
1435 interrupt-names = "int0", "int1";
1436 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
1444 reg-names = "m_can", "message_ram";
1445 power-domains = <&k3_pds 258 TI_SCI_PD_EXCLUSIVE>;
1447 clock-names = "hclk", "cclk";
1450 interrupt-names = "int0", "int1";
1451 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
1459 reg-names = "m_can", "message_ram";
1460 power-domains = <&k3_pds 259 TI_SCI_PD_EXCLUSIVE>;
1462 clock-names = "hclk", "cclk";
1465 interrupt-names = "int0", "int1";
1466 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
1474 reg-names = "m_can", "message_ram";
1475 power-domains = <&k3_pds 260 TI_SCI_PD_EXCLUSIVE>;
1477 clock-names = "hclk", "cclk";
1480 interrupt-names = "int0", "int1";
1481 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
1489 reg-names = "m_can", "message_ram";
1490 power-domains = <&k3_pds 261 TI_SCI_PD_EXCLUSIVE>;
1492 clock-names = "hclk", "cclk";
1495 interrupt-names = "int0", "int1";
1496 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
1504 reg-names = "m_can", "message_ram";
1505 power-domains = <&k3_pds 262 TI_SCI_PD_EXCLUSIVE>;
1507 clock-names = "hclk", "cclk";
1510 interrupt-names = "int0", "int1";
1511 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
1516 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1519 #address-cells = <1>;
1520 #size-cells = <0>;
1521 power-domains = <&k3_pds 376 TI_SCI_PD_EXCLUSIVE>;
1527 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1530 #address-cells = <1>;
1531 #size-cells = <0>;
1532 power-domains = <&k3_pds 377 TI_SCI_PD_EXCLUSIVE>;
1538 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1541 #address-cells = <1>;
1542 #size-cells = <0>;
1543 power-domains = <&k3_pds 378 TI_SCI_PD_EXCLUSIVE>;
1549 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1552 #address-cells = <1>;
1553 #size-cells = <0>;
1554 power-domains = <&k3_pds 379 TI_SCI_PD_EXCLUSIVE>;
1560 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1563 #address-cells = <1>;
1564 #size-cells = <0>;
1565 power-domains = <&k3_pds 380 TI_SCI_PD_EXCLUSIVE>;
1571 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1574 #address-cells = <1>;
1575 #size-cells = <0>;
1576 power-domains = <&k3_pds 381 TI_SCI_PD_EXCLUSIVE>;
1582 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1585 #address-cells = <1>;
1586 #size-cells = <0>;
1587 power-domains = <&k3_pds 382 TI_SCI_PD_EXCLUSIVE>;
1593 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1596 #address-cells = <1>;
1597 #size-cells = <0>;
1598 power-domains = <&k3_pds 383 TI_SCI_PD_EXCLUSIVE>;
1603 ufs_wrapper: ufs-wrapper@4e80000 {
1604 compatible = "ti,j721e-ufs";
1606 power-domains = <&k3_pds 387 TI_SCI_PD_EXCLUSIVE>;
1608 assigned-clocks = <&k3_clks 387 3>;
1609 assigned-clock-parents = <&k3_clks 387 6>;
1611 #address-cells = <2>;
1612 #size-cells = <2>;
1616 compatible = "cdns,ufshc-m31-16nm", "jedec,ufs-2.0";
1619 freq-table-hz = <250000000 250000000>, <19200000 19200000>,
1622 clock-names = "core_clk", "phy_clk", "ref_clk";
1623 dma-coherent;
1628 compatible = "ti,j721s2-r5fss";
1629 ti,cluster-mode = <1>;
1630 #address-cells = <1>;
1631 #size-cells = <1>;
1634 power-domains = <&k3_pds 336 TI_SCI_PD_EXCLUSIVE>;
1637 compatible = "ti,j721s2-r5f";
1640 reg-names = "atcm", "btcm";
1641 ti,sci = <&sms>;
1642 ti,sci-dev-id = <339>;
1643 ti,sci-proc-ids = <0x06 0xff>;
1645 firmware-name = "j784s4-main-r5f0_0-fw";
1646 ti,atcm-enable = <1>;
1647 ti,btcm-enable = <1>;
1652 compatible = "ti,j721s2-r5f";
1655 reg-names = "atcm", "btcm";
1656 ti,sci = <&sms>;
1657 ti,sci-dev-id = <340>;
1658 ti,sci-proc-ids = <0x07 0xff>;
1660 firmware-name = "j784s4-main-r5f0_1-fw";
1661 ti,atcm-enable = <1>;
1662 ti,btcm-enable = <1>;
1668 compatible = "ti,j721s2-r5fss";
1669 ti,cluster-mode = <1>;
1670 #address-cells = <1>;
1671 #size-cells = <1>;
1674 power-domains = <&k3_pds 337 TI_SCI_PD_EXCLUSIVE>;
1677 compatible = "ti,j721s2-r5f";
1680 reg-names = "atcm", "btcm";
1681 ti,sci = <&sms>;
1682 ti,sci-dev-id = <341>;
1683 ti,sci-proc-ids = <0x08 0xff>;
1685 firmware-name = "j784s4-main-r5f1_0-fw";
1686 ti,atcm-enable = <1>;
1687 ti,btcm-enable = <1>;
1692 compatible = "ti,j721s2-r5f";
1695 reg-names = "atcm", "btcm";
1696 ti,sci = <&sms>;
1697 ti,sci-dev-id = <342>;
1698 ti,sci-proc-ids = <0x09 0xff>;
1700 firmware-name = "j784s4-main-r5f1_1-fw";
1701 ti,atcm-enable = <1>;
1702 ti,btcm-enable = <1>;
1708 compatible = "ti,j721s2-r5fss";
1709 ti,cluster-mode = <1>;
1710 #address-cells = <1>;
1711 #size-cells = <1>;
1714 power-domains = <&k3_pds 338 TI_SCI_PD_EXCLUSIVE>;
1717 compatible = "ti,j721s2-r5f";
1720 reg-names = "atcm", "btcm";
1721 ti,sci = <&sms>;
1722 ti,sci-dev-id = <343>;
1723 ti,sci-proc-ids = <0x0a 0xff>;
1725 firmware-name = "j784s4-main-r5f2_0-fw";
1726 ti,atcm-enable = <1>;
1727 ti,btcm-enable = <1>;
1732 compatible = "ti,j721s2-r5f";
1735 reg-names = "atcm", "btcm";
1736 ti,sci = <&sms>;
1737 ti,sci-dev-id = <344>;
1738 ti,sci-proc-ids = <0x0b 0xff>;
1740 firmware-name = "j784s4-main-r5f2_1-fw";
1741 ti,atcm-enable = <1>;
1742 ti,btcm-enable = <1>;
1748 compatible = "ti,j721s2-c71-dsp";
1751 reg-names = "l2sram", "l1dram";
1752 ti,sci = <&sms>;
1753 ti,sci-dev-id = <30>;
1754 ti,sci-proc-ids = <0x30 0xff>;
1756 firmware-name = "j784s4-c71_0-fw";
1761 compatible = "ti,j721s2-c71-dsp";
1764 reg-names = "l2sram", "l1dram";
1765 ti,sci = <&sms>;
1766 ti,sci-dev-id = <33>;
1767 ti,sci-proc-ids = <0x31 0xff>;
1769 firmware-name = "j784s4-c71_1-fw";
1774 compatible = "ti,j721s2-c71-dsp";
1777 reg-names = "l2sram", "l1dram";
1778 ti,sci = <&sms>;
1779 ti,sci-dev-id = <37>;
1780 ti,sci-proc-ids = <0x32 0xff>;
1782 firmware-name = "j784s4-c71_2-fw";
1787 compatible = "ti,j721s2-c71-dsp";
1790 reg-names = "l2sram", "l1dram";
1791 ti,sci = <&sms>;
1792 ti,sci-dev-id = <40>;
1793 ti,sci-proc-ids = <0x33 0xff>;
1795 firmware-name = "j784s4-c71_3-fw";
1800 compatible = "ti,j721e-esm";
1802 ti,esm-pins = <688>, <689>, <690>, <691>, <692>, <693>, <694>,
1804 bootph-pre-ram;
1808 compatible = "ti,j7-rti-wdt";
1811 power-domains = <&k3_pds 348 TI_SCI_PD_EXCLUSIVE>;
1812 assigned-clocks = <&k3_clks 348 0>;
1813 assigned-clock-parents = <&k3_clks 348 4>;
1817 compatible = "ti,j7-rti-wdt";
1820 power-domains = <&k3_pds 349 TI_SCI_PD_EXCLUSIVE>;
1821 assigned-clocks = <&k3_clks 349 0>;
1822 assigned-clock-parents = <&k3_clks 349 4>;
1826 compatible = "ti,j7-rti-wdt";
1829 power-domains = <&k3_pds 350 TI_SCI_PD_EXCLUSIVE>;
1830 assigned-clocks = <&k3_clks 350 0>;
1831 assigned-clock-parents = <&k3_clks 350 4>;
1835 compatible = "ti,j7-rti-wdt";
1838 power-domains = <&k3_pds 351 TI_SCI_PD_EXCLUSIVE>;
1839 assigned-clocks = <&k3_clks 351 0>;
1840 assigned-clock-parents = <&k3_clks 351 4>;
1844 compatible = "ti,j7-rti-wdt";
1847 power-domains = <&k3_pds 352 TI_SCI_PD_EXCLUSIVE>;
1848 assigned-clocks = <&k3_clks 352 0>;
1849 assigned-clock-parents = <&k3_clks 352 4>;
1853 compatible = "ti,j7-rti-wdt";
1856 power-domains = <&k3_pds 353 TI_SCI_PD_EXCLUSIVE>;
1857 assigned-clocks = <&k3_clks 353 0>;
1858 assigned-clock-parents = <&k3_clks 353 4>;
1862 compatible = "ti,j7-rti-wdt";
1865 power-domains = <&k3_pds 354 TI_SCI_PD_EXCLUSIVE>;
1866 assigned-clocks = <&k3_clks 354 0>;
1867 assigned-clock-parents = <&k3_clks 354 4>;
1871 compatible = "ti,j7-rti-wdt";
1874 power-domains = <&k3_pds 355 TI_SCI_PD_EXCLUSIVE>;
1875 assigned-clocks = <&k3_clks 355 0>;
1876 assigned-clock-parents = <&k3_clks 355 4>;
1885 compatible = "ti,j7-rti-wdt";
1888 power-domains = <&k3_pds 360 TI_SCI_PD_EXCLUSIVE>;
1889 assigned-clocks = <&k3_clks 360 0>;
1890 assigned-clock-parents = <&k3_clks 360 4>;
1896 compatible = "ti,j7-rti-wdt";
1899 power-domains = <&k3_pds 356 TI_SCI_PD_EXCLUSIVE>;
1900 assigned-clocks = <&k3_clks 356 0>;
1901 assigned-clock-parents = <&k3_clks 356 4>;
1907 compatible = "ti,j7-rti-wdt";
1910 power-domains = <&k3_pds 357 TI_SCI_PD_EXCLUSIVE>;
1911 assigned-clocks = <&k3_clks 357 0>;
1912 assigned-clock-parents = <&k3_clks 357 4>;
1918 compatible = "ti,j7-rti-wdt";
1921 power-domains = <&k3_pds 358 TI_SCI_PD_EXCLUSIVE>;
1922 assigned-clocks = <&k3_clks 358 0>;
1923 assigned-clock-parents = <&k3_clks 358 4>;
1929 compatible = "ti,j7-rti-wdt";
1932 power-domains = <&k3_pds 359 TI_SCI_PD_EXCLUSIVE>;
1933 assigned-clocks = <&k3_clks 359 0>;
1934 assigned-clock-parents = <&k3_clks 359 4>;
1940 compatible = "ti,j7-rti-wdt";
1943 power-domains = <&k3_pds 361 TI_SCI_PD_EXCLUSIVE>;
1944 assigned-clocks = <&k3_clks 361 0>;
1945 assigned-clock-parents = <&k3_clks 361 4>;
1951 compatible = "ti,j7-rti-wdt";
1954 power-domains = <&k3_pds 362 TI_SCI_PD_EXCLUSIVE>;
1955 assigned-clocks = <&k3_clks 362 0>;
1956 assigned-clock-parents = <&k3_clks 362 4>;
1962 compatible = "ti,j7-rti-wdt";
1965 power-domains = <&k3_pds 363 TI_SCI_PD_EXCLUSIVE>;
1966 assigned-clocks = <&k3_clks 363 0>;
1967 assigned-clock-parents = <&k3_clks 363 4>;
1973 compatible = "ti,j7-rti-wdt";
1976 power-domains = <&k3_pds 364 TI_SCI_PD_EXCLUSIVE>;
1977 assigned-clocks = <&k3_clks 364 0>;
1978 assigned-clock-parents = <&k3_clks 364 4>;
1984 compatible = "ti,j7-rti-wdt";
1987 power-domains = <&k3_pds 365 TI_SCI_PD_EXCLUSIVE>;
1988 assigned-clocks = <&k3_clks 365 0>;
1989 assigned-clock-parents = <&k3_clks 366 4>;
1995 compatible = "ti,j7-rti-wdt";
1998 power-domains = <&k3_pds 366 TI_SCI_PD_EXCLUSIVE>;
1999 assigned-clocks = <&k3_clks 366 0>;
2000 assigned-clock-parents = <&k3_clks 366 4>;
2006 compatible = "ti,j721e-mhdp8546";
2009 reg-names = "mhdptx", "j721e-intg";
2011 interrupt-parent = <&gic500>;
2013 power-domains = <&k3_pds 217 TI_SCI_PD_EXCLUSIVE>;
2017 #address-cells = <1>;
2018 #size-cells = <0>;
2019 /* Remote-endpoints are on the boards so
2026 compatible = "ti,j721e-dss";
2044 reg-names = "common_m", "common_s0",
2055 clock-names = "fck", "vp1", "vp2", "vp3", "vp4";
2056 power-domains = <&k3_pds 218 TI_SCI_PD_EXCLUSIVE>;
2061 interrupt-names = "common_m",