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/linux/Documentation/devicetree/bindings/interconnect/
H A Dqcom,sar2130p-rpmh.yaml4 $id: http://devicetree.org/schemas/interconnect/qcom,sar2130p-rpmh.yaml#
7 title: Qualcomm RPMh Network-On-Chip Interconnect on SAR2130P
21 See also: include/dt-bindings/interconnect/qcom,sar2130p-rpmh.h
26 - qcom,sar2130p-clk-virt
27 - qcom,sar2130p-config-noc
28 - qcom,sar2130p-gem-noc
29 - qcom,sar2130p-lpass-ag-noc
30 - qcom,sar2130p-mc-virt
31 - qcom,sar2130p-mmss-noc
32 - qcom,sar2130p-nsp-noc
[all …]
/linux/Documentation/devicetree/bindings/pinctrl/
H A Dqcom,sar2130p-tlmm.yaml4 $id: http://devicetree.org/schemas/pinctrl/qcom,sar2130p-tlmm.yaml#
7 title: Qualcomm Technologies, Inc. SAR2130P TLMM block
13 Top Level Mode Multiplexer pin controller in Qualcomm SAR2130P SoC.
20 const: qcom,sar2130p-tlmm
38 - $ref: "#/$defs/qcom-sar2130p-tlmm-state"
41 $ref: "#/$defs/qcom-sar2130p-tlmm-state"
45 qcom-sar2130p-tlmm-state:
110 compatible = "qcom,sar2130p-tlmm";
/linux/Documentation/devicetree/bindings/clock/
H A Dqcom,sar2130p-gcc.yaml4 $id: http://devicetree.org/schemas/clock/qcom,sar2130p-gcc.yaml#
7 title: Qualcomm Global Clock & Reset Controller on sar2130p
14 power domains on sar2130p.
16 See also: include/dt-bindings/clock/qcom,sar2130p-gcc.h
20 const: qcom,sar2130p-gcc
52 compatible = "qcom,sar2130p-gcc";
H A Dqcom,sm8550-tcsr.yaml29 - qcom,sar2130p-tcsr
H A Dqcom,rpmhcc.yaml25 - qcom,sar2130p-rpmh-clk
/linux/Documentation/devicetree/bindings/phy/
H A Dqcom,sc8280xp-qmp-usb43dp-phy.yaml19 - qcom,sar2130p-qmp-usb3-dp-phy
131 - qcom,sar2130p-qmp-usb3-dp-phy
H A Dqcom,sc8280xp-qmp-pcie-phy.yaml23 - qcom,sar2130p-qmp-gen3x2-pcie-phy
150 - qcom,sar2130p-qmp-gen3x2-pcie-phy
H A Dqcom,snps-eusb2-phy.yaml21 - qcom,sar2130p-snps-eusb2-phy
/linux/Documentation/devicetree/bindings/cache/
H A Dqcom,llcc.yaml29 - qcom,sar2130p-llcc
92 - qcom,sar2130p-llcc
/linux/Documentation/devicetree/bindings/mailbox/
H A Dqcom-ipcc.yaml32 - qcom,sar2130p-ipcc
/linux/Documentation/devicetree/bindings/iommu/
H A Darm,smmu.yaml45 - qcom,sar2130p-smmu-500
98 - qcom,sar2130p-smmu-500
536 - qcom,sar2130p-smmu-500
/linux/drivers/clk/qcom/
H A DMakefile103 obj-$(CONFIG_SAR_GCC_2130P) += gcc-sar2130p.o
104 obj-$(CONFIG_SAR_GPUCC_2130P) += gpucc-sar2130p.o
H A DKconfig702 tristate "SAR2130P Global Clock Controller"
706 Support for the global clock controller on SAR2130P devices.
711 tristate "SAR2130P Graphics clock controller"
715 Support for the graphics clock controller on SAR2130P devices.
1154 SAR2130P, SM8550 or SM8650 devices.
H A Dtcsrcc-sm8550.c169 { .compatible = "qcom,sar2130p-tcsr", .data = &tcsr_cc_sar2130p_desc },
H A Dgcc-sar2130p.c13 #include <dt-bindings/clock/qcom,sar2130p-gcc.h>
2314 { .compatible = "qcom,sar2130p-gcc" },
2348 .name = "gcc-sar2130p",
2365 MODULE_DESCRIPTION("QTI GCC SAR2130P Driver");
/linux/Documentation/devicetree/bindings/soc/qcom/
H A Dqcom,aoss-qmp.yaml34 - qcom,sar2130p-aoss-qmp
/linux/Documentation/devicetree/bindings/dma/
H A Dqcom,gpi.yaml32 - qcom,sar2130p-gpi-dma
/linux/Documentation/devicetree/bindings/nvmem/
H A Dqcom,qfprom.yaml42 - qcom,sar2130p-qfprom
/linux/Documentation/devicetree/bindings/usb/
H A Dqcom,dwc3.yaml45 - qcom,sar2130p-dwc3
359 - qcom,sar2130p-dwc3
H A Dqcom,snps-dwc3.yaml46 - qcom,sar2130p-dwc3
346 - qcom,sar2130p-dwc3
/linux/Documentation/devicetree/bindings/power/
H A Dqcom,rpmpd.yaml44 - qcom,sar2130p-rpmhpd
/linux/Documentation/devicetree/bindings/pci/
H A Dqcom,pcie-sm8550.yaml23 - qcom,sar2130p-pcie
/linux/drivers/soc/qcom/
H A Dubwc_config.c243 { .compatible = "qcom,sar2130p", .data = &sar2130p_data },
/linux/drivers/pmdomain/qcom/
H A Drpmhpd.c280 /* SAR2130P RPMH powerdomains */
777 { .compatible = "qcom,sar2130p-rpmhpd", .data = &sar2130p_desc},
/linux/drivers/gpu/drm/msm/
H A Dmsm_mdss.c559 { .compatible = "qcom,sar2130p-mdss", .data = &data_74k },

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