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/linux/Documentation/devicetree/bindings/interconnect/
H A Dqcom,sar2130p-rpmh.yaml4 $id: http://devicetree.org/schemas/interconnect/qcom,sar2130p-rpmh.yaml#
7 title: Qualcomm RPMh Network-On-Chip Interconnect on SAR2130P
21 See also: include/dt-bindings/interconnect/qcom,sar2130p-rpmh.h
26 - qcom,sar2130p-clk-virt
27 - qcom,sar2130p-config-noc
28 - qcom,sar2130p-gem-noc
29 - qcom,sar2130p-lpass-ag-noc
30 - qcom,sar2130p-mc-virt
31 - qcom,sar2130p-mmss-noc
32 - qcom,sar2130p-nsp-noc
[all …]
/linux/Documentation/devicetree/bindings/display/msm/
H A Dqcom,sar2130p-mdss.yaml4 $id: http://devicetree.org/schemas/display/msm/qcom,sar2130p-mdss.yaml#
7 title: Qualcomm SAR2130P Display MDSS
20 const: qcom,sar2130p-mdss
48 const: qcom,sar2130p-dpu
56 const: qcom,sar2130p-dp
64 const: qcom,sar2130p-dsi-ctrl
71 const: qcom,sar2130p-dsi-phy-5nm
85 compatible = "qcom,sar2130p-mdss";
114 compatible = "qcom,sar2130p-dpu";
196 compatible = "qcom,sar2130p-dp",
[all …]
H A Ddsi-controller-main.yaml29 - qcom,sar2130p-dsi-ctrl
350 - qcom,sar2130p-dsi-ctrl
H A Ddp-controller.yaml54 - qcom,sar2130p-dp
/linux/Documentation/devicetree/bindings/pinctrl/
H A Dqcom,sar2130p-tlmm.yaml4 $id: http://devicetree.org/schemas/pinctrl/qcom,sar2130p-tlmm.yaml#
7 title: Qualcomm Technologies, Inc. SAR2130P TLMM block
13 Top Level Mode Multiplexer pin controller in Qualcomm SAR2130P SoC.
20 const: qcom,sar2130p-tlmm
38 - $ref: "#/$defs/qcom-sar2130p-tlmm-state"
41 $ref: "#/$defs/qcom-sar2130p-tlmm-state"
45 qcom-sar2130p-tlmm-state:
110 compatible = "qcom,sar2130p-tlmm";
/linux/Documentation/devicetree/bindings/clock/
H A Dqcom,sar2130p-gcc.yaml4 $id: http://devicetree.org/schemas/clock/qcom,sar2130p-gcc.yaml#
7 title: Qualcomm Global Clock & Reset Controller on sar2130p
14 power domains on sar2130p.
16 See also: include/dt-bindings/clock/qcom,sar2130p-gcc.h
20 const: qcom,sar2130p-gcc
52 compatible = "qcom,sar2130p-gcc";
H A Dqcom,sm8450-gpucc.yaml23 include/dt-bindings/clock/qcom,sar2130p-gpucc.h
40 - qcom,sar2130p-gpucc
H A Dqcom,sm8550-tcsr.yaml35 - qcom,sar2130p-tcsr
H A Dqcom,rpmhcc.yaml30 - qcom,sar2130p-rpmh-clk
H A Dqcom,sm8550-dispcc.yaml31 - qcom,sar2130p-dispcc
/linux/drivers/clk/qcom/
H A Dgpucc-sar2130p.c13 #include <dt-bindings/clock/qcom,sar2130p-gpucc.h>
14 #include <dt-bindings/reset/qcom,sar2130p-gpucc.h>
469 { .compatible = "qcom,sar2130p-gpucc" },
495 .name = "gpu_cc-sar2130p",
501 MODULE_DESCRIPTION("QTI GPU_CC SAR2130P Driver");
H A DMakefile132 obj-$(CONFIG_SAR_GCC_2130P) += gcc-sar2130p.o
133 obj-$(CONFIG_SAR_GPUCC_2130P) += gpucc-sar2130p.o
H A Dtcsrcc-sm8550.c169 { .compatible = "qcom,sar2130p-tcsr", .data = &tcsr_cc_sar2130p_desc },
H A DKconfig1069 tristate "SAR2130P Global Clock Controller"
1073 Support for the global clock controller on SAR2130P devices.
1078 tristate "SAR2130P Graphics clock controller"
1082 Support for the graphics clock controller on SAR2130P devices.
1577 SAR2130P, SM8550 or SM8650 devices.
H A Dgcc-sar2130p.c13 #include <dt-bindings/clock/qcom,sar2130p-gcc.h>
2314 { .compatible = "qcom,sar2130p-gcc" },
2348 .name = "gcc-sar2130p",
2365 MODULE_DESCRIPTION("QTI GCC SAR2130P Driver");
H A Ddispcc-sm8550.c1758 { .compatible = "qcom,sar2130p-dispcc" },
1789 } else if (of_device_is_compatible(pdev->dev.of_node, "qcom,sar2130p-dispcc")) { in disp_cc_sm8550_probe()
/linux/drivers/interconnect/qcom/
H A Dsar2130p.c17 #include <dt-bindings/interconnect/qcom,sar2130p-rpmh.h>
1722 { .compatible = "qcom,sar2130p-clk-virt", .data = &sar2130p_clk_virt},
1723 { .compatible = "qcom,sar2130p-config-noc", .data = &sar2130p_config_noc},
1724 { .compatible = "qcom,sar2130p-gem-noc", .data = &sar2130p_gem_noc},
1725 { .compatible = "qcom,sar2130p-lpass-ag-noc", .data = &sar2130p_lpass_ag_noc},
1726 { .compatible = "qcom,sar2130p-mc-virt", .data = &sar2130p_mc_virt},
1727 { .compatible = "qcom,sar2130p-mmss-noc", .data = &sar2130p_mmss_noc},
1728 { .compatible = "qcom,sar2130p-nsp-noc", .data = &sar2130p_nsp_noc},
1729 { .compatible = "qcom,sar2130p-pcie-anoc", .data = &sar2130p_pcie_anoc},
1730 { .compatible = "qcom,sar2130p-system-noc", .data = &sar2130p_system_noc},
[all …]
/linux/Documentation/devicetree/bindings/phy/
H A Dqcom,sc8280xp-qmp-usb43dp-phy.yaml30 - qcom,sar2130p-qmp-usb3-dp-phy
215 - qcom,sar2130p-qmp-usb3-dp-phy
H A Dqcom,sc8280xp-qmp-pcie-phy.yaml30 - qcom,sar2130p-qmp-gen3x2-pcie-phy
167 - qcom,sar2130p-qmp-gen3x2-pcie-phy
/linux/Documentation/devicetree/bindings/mailbox/
H A Dqcom-ipcc.yaml38 - qcom,sar2130p-ipcc
/linux/drivers/pinctrl/qcom/
H A DKconfig.msm346 tristate "Qualcomm SAR2130P pin controller driver"
351 Technologies Inc SAR2130P platform.
H A DMakefile49 obj-$(CONFIG_PINCTRL_SAR2130P) += pinctrl-sar2130p.o
/linux/Documentation/devicetree/bindings/pci/
H A Dqcom,pcie-sm8550.yaml25 - qcom,sar2130p-pcie
/linux/Documentation/devicetree/bindings/thermal/
H A Dqcom-tsens.yaml72 - qcom,sar2130p-tsens
/linux/drivers/pmdomain/qcom/
H A Drpmhpd.c341 /* SAR2130P RPMH powerdomains */
896 { .compatible = "qcom,sar2130p-rpmhpd", .data = &sar2130p_desc},

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