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/linux/Documentation/devicetree/bindings/pinctrl/
H A Drenesas,rzg2l-poeg.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/renesas,rzg2l-poeg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Biju Das <biju.das.jz@bp.renesas.com>
17 * Output-disable request from the GPT.
26 - enum:
27 - renesas,r9a07g044-poeg # RZ/G2{L,LC}
28 - renesas,r9a07g054-poeg # RZ/V2L
29 - const: renesas,rzg2l-poeg
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/linux/arch/arm64/boot/dts/renesas/
H A Dr9a07g054.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/r9a07g054-cpg.h>
13 #address-cells = <2>;
14 #size-cells = <2>;
16 audio_clk1: audio1-clk {
17 compatible = "fixed-clock";
18 #clock-cells = <0>;
20 clock-frequency = <0>;
23 audio_clk2: audio2-clk {
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H A Dr9a07g043.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/clock/r9a07g043-cpg.h>
12 #address-cells = <2>;
13 #size-cells = <2>;
15 audio_clk1: audio1-clk {
16 compatible = "fixed-clock";
17 #clock-cells = <0>;
19 clock-frequency = <0>;
22 audio_clk2: audio2-clk {
23 compatible = "fixed-clock";
[all …]
H A Dr9a07g043u11-smarc-cru-csi-ov5645.dtso1 // SPDX-License-Identifier: GPL-2.0
9 /dts-v1/;
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
16 #include "rz-smarc-cru-csi-ov5645.dtsi"
19 enable-gpios = <&pinctrl RZG2L_GPIO(4, 4) GPIO_ACTIVE_HIGH>;
20 reset-gpios = <&pinctrl RZG2L_GPIO(0, 1) GPIO_ACTIVE_LOW>;
H A Dr9a07g044c2-smarc-cru-csi-ov5645.dtso1 // SPDX-License-Identifier: GPL-2.0
9 /dts-v1/;
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
16 #include "rz-smarc-cru-csi-ov5645.dtsi"
19 enable-gpios = <&pinctrl RZG2L_GPIO(0, 1) GPIO_ACTIVE_HIGH>;
20 reset-gpios = <&pinctrl RZG2L_GPIO(5, 2) GPIO_ACTIVE_LOW>;
H A Dr9a07g044l2-smarc-cru-csi-ov5645.dtso1 // SPDX-License-Identifier: GPL-2.0
9 /dts-v1/;
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
16 #include "rz-smarc-cru-csi-ov5645.dtsi"
19 enable-gpios = <&pinctrl RZG2L_GPIO(2, 0) GPIO_ACTIVE_HIGH>;
20 reset-gpios = <&pinctrl RZG2L_GPIO(40, 2) GPIO_ACTIVE_LOW>;
H A Dr9a07g054l2-smarc-cru-csi-ov5645.dtso1 // SPDX-License-Identifier: GPL-2.0
9 /dts-v1/;
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
16 #include "rz-smarc-cru-csi-ov5645.dtsi"
19 enable-gpios = <&pinctrl RZG2L_GPIO(2, 0) GPIO_ACTIVE_HIGH>;
20 reset-gpios = <&pinctrl RZG2L_GPIO(40, 2) GPIO_ACTIVE_LOW>;
H A Dr9a07g044.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/r9a07g044-cpg.h>
13 #address-cells = <2>;
14 #size-cells = <2>;
16 audio_clk1: audio1-clk {
17 compatible = "fixed-clock";
18 #clock-cells = <0>;
20 clock-frequency = <0>;
23 audio_clk2: audio2-clk {
[all …]
H A Dr9a07g043-smarc-pmod.dtso1 // SPDX-License-Identifier: GPL-2.0
11 * +----------------------------+
17 * +----------------------------+
21 /dts-v1/;
24 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
26 &pinctrl {
27 can0-stb-hog {
31 can1-stb-hog {
35 sci0_pins: sci0-pins {
42 pinctrl-0 = <&sci0_pins>;
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H A Drzg2lc-smarc-som.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/irqc-rzg2l.h>
10 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
27 reg_1p8v: regulator-1p8v {
28 compatible = "regulator-fixed";
29 regulator-name = "fixed-1.8V";
30 regulator-min-microvolt = <1800000>;
31 regulator-max-microvolt = <1800000>;
32 regulator-boot-on;
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H A Drzg2ul-smarc-som.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/irqc-rzg2l.h>
10 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
28 reg_1p8v: regulator-1p8v {
29 compatible = "regulator-fixed";
30 regulator-name = "fixed-1.8V";
31 regulator-min-microvolt = <1800000>;
32 regulator-max-microvolt = <1800000>;
33 regulator-boot-on;
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H A Drzg2l-smarc-som.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/irqc-rzg2l.h>
10 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
38 reg_1p8v: regulator-1p8v {
39 compatible = "regulator-fixed";
40 regulator-name = "fixed-1.8V";
41 regulator-min-microvolt = <1800000>;
42 regulator-max-microvolt = <1800000>;
43 regulator-boot-on;
[all …]
H A Dr9a09g011.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/r9a09g011-cpg.h>
13 #address-cells = <2>;
14 #size-cells = <2>;
18 compatible = "fixed-clock";
19 #clock-cells = <0>;
21 clock-frequency = <0>;
25 #address-cells = <1>;
26 #size-cells = <0>;
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H A Drz-smarc-common.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
12 * SSI-WM8978
32 stdout-path = "serial0:115200n8";
36 compatible = "simple-audio-card";
37 simple-audio-card,format = "i2s";
38 simple-audio-card,bitclock-master = <&cpu_dai>;
39 simple-audio-card,frame-master = <&cpu_dai>;
40 simple-audio-card,mclk-fs = <256>;
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H A Dr9a07g043u11-smarc-du-adv7513.dtso1 // SPDX-License-Identifier: GPL-2.0
9 /dts-v1/;
12 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
15 #include "rz-smarc-du-adv7513.dtsi"
17 &pinctrl {
44 drive-strength = <2>;
50 drive-strength = <2>;
55 drive-strength = <2>;
H A Drzg2ul-smarc-pinfunction.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
11 &pinctrl {
12 pinctrl-0 = <&sound_clk_pins>;
13 pinctrl-names = "default";
21 can0-stb-hog {
22 gpio-hog;
24 output-low;
25 line-name = "can0_stb";
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H A Drzg2l-smarc.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
17 osc1: cec-clock {
18 compatible = "fixed-clock";
19 #clock-cells = <0>;
20 clock-frequency = <12000000>;
23 hdmi-out {
24 compatible = "hdmi-connector";
29 remote-endpoint = <&adv7535_out>;
[all …]
H A Drzg2lc-smarc.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
11 #include "rzg2lc-smarc-pinfunction.dtsi"
12 #include "rz-smarc-common.dtsi"
20 osc1: cec-clock {
21 compatible = "fixed-clock";
22 #clock-cells = <0>;
23 clock-frequency = <12000000>;
26 hdmi-out {
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H A Drzg2lc-smarc-pinfunction.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
11 &pinctrl {
12 pinctrl-0 = <&sound_clk_pins>;
13 pinctrl-names = "default";
16 /* SW8 should be at position 2->1 */
24 /* SW8 should be at position 2->3 so that GPIO9_CAN1_STB line is activated */
25 can1-stb-hog {
26 gpio-hog;
[all …]
H A Drzg2l-smarc-pinfunction.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
11 &pinctrl {
12 pinctrl-0 = <&sound_clk_pins>;
13 pinctrl-names = "default";
20 /* SW7 should be at position 2->3 so that GPIO8_CAN0_STB line is activated */
21 can0-stb-hog {
22 gpio-hog;
24 output-low;
[all …]
/linux/Documentation/devicetree/bindings/mmc/
H A Drenesas,sdhi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Wolfram Sang <wsa+renesas@sang-engineering.com>
15 - enum:
16 - renesas,sdhi-mmc-r8a77470 # RZ/G1C
17 - renesas,sdhi-r7s72100 # RZ/A1H
18 - renesas,sdhi-r7s9210 # SH-Mobile AG5
19 - renesas,sdhi-r8a73a4 # R-Mobile APE6
20 - renesas,sdhi-r8a7740 # R-Mobile A1
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/linux/drivers/pinctrl/renesas/
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_PINCTRL_SH_PFC) += core.o pinctrl.o
3 obj-$(CONFIG_PINCTRL_SH_PFC_GPIO) += gpio.o
4 obj-$(CONFIG_PINCTRL_PFC_EMEV2) += pfc-emev2.o
5 obj-$(CONFIG_PINCTRL_PFC_R8A73A4) += pfc-r8a73a4.o
6 obj-$(CONFIG_PINCTRL_PFC_R8A7740) += pfc-r8a7740.o
7 obj-$(CONFIG_PINCTRL_PFC_R8A7742) += pfc-r8a7790.o
8 obj-$(CONFIG_PINCTRL_PFC_R8A7743) += pfc-r8a7791.o
9 obj-$(CONFIG_PINCTRL_PFC_R8A7744) += pfc-r8a7791.o
10 obj-$(CONFIG_PINCTRL_PFC_R8A7745) += pfc-r8a7794.o
[all …]
/linux/drivers/irqchip/
H A Dirq-renesas-rzg2l.c1 // SPDX-License-Identifier: GPL-2.0
7 * Author: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
63 * struct rzg2l_irqc_reg_cache - registers cache (necessary for suspend/resume)
73 * struct rzg2l_irqc_priv - IRQ controller private data structure
90 return data->domain->host_data; in irq_data_to_priv()
95 unsigned int hw_irq = hwirq - IRQC_IRQ_START; in rzg2l_clear_irq_int()
99 iscr = readl_relaxed(priv->base + ISCR); in rzg2l_clear_irq_int()
100 iitsr = readl_relaxed(priv->base + IITSR); in rzg2l_clear_irq_int()
103 * ISCR can only be cleared if the type is falling-edge, rising-edge or in rzg2l_clear_irq_int()
104 * falling/rising-edge. in rzg2l_clear_irq_int()
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/linux/
H A DMAINTAINERS5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-scsi@vger.kernel.org
88 F: drivers/scsi/3w-*
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