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/linux/Documentation/devicetree/bindings/net/
H A Dsophgo,cv1800b-dwmac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/sophgo,cv1800b-dwmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Inochi Amaoto <inochiama@gmail.com>
17 - sophgo,cv1800b-dwmac
19 - compatible
24 - const: sophgo,cv1800b-dwmac
25 - const: snps,dwmac-3.70a
32 - description: GMAC main clock
[all …]
H A Dintel,dwmac-plat.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/intel,dwmac-plat.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vineetha G. Jaya Kumaran <vineetha.g.jaya.kumaran@intel.com>
17 - intel,keembay-dwmac
19 - compatible
22 - $ref: snps,dwmac.yaml#
27 - items:
28 - enum:
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/linux/arch/arm64/boot/dts/st/
H A Dstm32mp253.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
11 compatible = "arm,cortex-a35";
14 enable-method = "psci";
15 power-domains = <&CPU_PD1>;
16 power-domain-names = "psci";
20 arm-pmu {
23 interrupt-affinity = <&cpu0>, <&cpu1>;
27 CPU_PD1: power-domain-cpu1 {
28 #power-domain-cells = <0>;
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H A Dstm32mp233.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2025 - All Rights Reserved
11 compatible = "arm,cortex-a35";
14 enable-method = "psci";
15 power-domains = <&cpu1_pd>;
16 power-domain-names = "psci";
20 arm-pmu {
23 interrupt-affinity = <&cpu0>, <&cpu1>;
27 cpu1_pd: power-domain-cpu1 {
28 #power-domain-cells = <0>;
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/linux/arch/arm64/boot/dts/renesas/
H A Dr9a09g087.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #address-cells = <2>;
14 #size-cells = <2>;
15 interrupt-parent = <&gic>;
18 #address-cells = <1>;
19 #size-cells = <0>;
22 compatible = "arm,cortex-a55";
25 next-level-cache = <&L3_CA55>;
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H A Dr9a09g077.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #address-cells = <2>;
14 #size-cells = <2>;
15 interrupt-parent = <&gic>;
18 #address-cells = <1>;
19 #size-cells = <0>;
22 compatible = "arm,cortex-a55";
25 next-level-cache = <&L3_CA55>;
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H A Dr9a09g056.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/clock/renesas,r9a09g056-cpg.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
12 /* RZV2N_Px = Offset address of PFC_P_mn - 0x20 */
31 #address-cells = <2>;
32 #size-cells = <2>;
33 interrupt-parent = <&gic>;
35 audio_extal_clk: audio-clk {
36 compatible = "fixed-clock";
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H A Dr9a09g047.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/clock/renesas,r9a09g047-cpg.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #address-cells = <2>;
14 #size-cells = <2>;
15 interrupt-parent = <&gic>;
17 audio_extal_clk: audio-clk {
18 compatible = "fixed-clock";
19 #clock-cells = <0>;
21 clock-frequency = <0>;
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H A Dr9a09g057.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/clock/renesas,r9a09g057-cpg.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #address-cells = <2>;
14 #size-cells = <2>;
15 interrupt-parent = <&gic>;
17 audio_extal_clk: audio-clk {
18 compatible = "fixed-clock";
19 #clock-cells = <0>;
21 clock-frequency = <0>;
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/linux/arch/arm64/boot/dts/intel/
H A Dsocfpga_agilex5.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/clock/intel,agilex5-clkmgr.h>
14 compatible = "intel,socfpga-agilex5";
15 #address-cells = <2>;
16 #size-cells = <2>;
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/linux/arch/arm64/boot/dts/qcom/
H A Dsa8540p-ride.dts1 // SPDX-License-Identifier: BSD-3-Clause
7 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
13 #include "sa8540p-pmics.dtsi"
17 compatible = "qcom,sa8540p-ride", "qcom,sa8540p";
29 stdout-path = "serial0:115200n8";
34 regulators-0 {
35 compatible = "qcom,pm8150-rpmh-regulators";
36 qcom,pmic-id = "a";
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H A Dqcs8300-ride.dts1 // SPDX-License-Identifier: BSD-3-Clause
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
12 #include "monaco-pmics.dtsi"
15 compatible = "qcom,qcs8300-ride", "qcom,qcs8300";
16 chassis-type = "embedded";
24 stdout-path = "serial0:115200n8";
27 regulator-usb2-vbus {
28 compatible = "regulator-fixed";
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/linux/drivers/net/ethernet/intel/ixgbe/
H A Dixgbe_dcb_82599.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
10 * ixgbe_dcb_config_rx_arbiter_82599 - Config Rx Data arbiter
18 * Configure Rx Packet Arbiter and credits for each traffic class.
60 * Configure Rx packet plane (recycle mode; WSP) and in ixgbe_dcb_config_rx_arbiter_82599()
70 * ixgbe_dcb_config_tx_desc_arbiter_82599 - Config Tx Desc. arbiter
88 /* Clear the per-Tx queue credits; we use per-TC instead */ in ixgbe_dcb_config_tx_desc_arbiter_82599()
121 * ixgbe_dcb_config_tx_data_arbiter_82599 - Config Tx Data arbiter
183 * ixgbe_dcb_config_pfc_82599 - Configure priority flow control
203 * X540 & X550 supports per TC Rx priority flow control. in ixgbe_dcb_config_pfc_82599()
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H A Dixgbe_dcb_82598.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
10 * ixgbe_dcb_config_rx_arbiter_82598 - Config Rx data arbiter
16 * Configure Rx Data Arbiter and credits for each traffic class.
67 * ixgbe_dcb_config_tx_desc_arbiter_82598 - Config Tx Desc. arbiter
113 * ixgbe_dcb_config_tx_data_arbiter_82598 - Config Tx data arbiter
160 * ixgbe_dcb_config_pfc_82598 - Config priority flow control
194 fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE; in ixgbe_dcb_config_pfc_82598()
195 reg = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN; in ixgbe_dcb_config_pfc_82598()
201 reg = hw->fc.pause_time * 0x00010001; in ixgbe_dcb_config_pfc_82598()
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/linux/tools/testing/selftests/drivers/net/
H A Dstats.py2 # SPDX-License-Identifier: GPL-2.0
24 def check_pause(cfg) -> None:
26 Check that drivers which support Pause config also report standard
31 ethnl.pause_get({"header": {"dev-index": cfg.ifindex}})
37 data = ethnl.pause_get({"header": {"dev-index": cfg.ifindex,
42 def check_fec(cfg) -> None:
44 Check that drivers which support FEC config also report standard
49 ethnl.fec_get({"header": {"dev-inde
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H A Dnetpoll_basic.py2 # SPDX-License-Identifier: GPL-2.0
11 suggested using a single RX/TX queue, pushing traffic to the NIC, and then
46 format="%(asctime)s - %(levelname)s - %(message)s",
49 NETCONSOLE_CONFIGFS_PATH: str = "/sys/kernel/config/netconsole"
67 def ethtool_get_ringsize(interface_name: str) -> tuple[int, int]:
72 ethtool_result = ethtool(f"-g {interface_name}", json=True)[0]
73 rxs = ethtool_result["rx"]
77 f"Failed to read RX/TX ringsize: {exception}. Not going to mess with them."
83 def ethtool_set_ringsize(interface_name: str, ring_size: tuple[int, int]) -> bool:
84 """Try to the number of RX and TX ringsize."""
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/linux/drivers/net/ethernet/cadence/
H A Dmacb_main.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2004-2006 Atmel Corporation
10 #include <linux/clk-provider.h>
13 #include <linux/dma-mapping.h>
15 #include <linux/firmware/xlnx-zynqmp.h>
61 #define MACB_TX_WAKEUP_THRESH(bp) (3 * (bp)->tx_ring_size / 4)
72 #define MACB_MAX_TX_LEN ((unsigned int)((1 << MACB_TX_FRMLEN_SIZE) -
554 u32 config; macb_usx_pcs_link_up() local
628 macb_mac_config(struct phylink_config * config,unsigned int mode,const struct phylink_link_state * state) macb_mac_config() argument
686 macb_mac_link_down(struct phylink_config * config,unsigned int mode,phy_interface_t interface) macb_mac_link_down() argument
707 macb_mac_link_up(struct phylink_config * config,struct phy_device * phy,unsigned int mode,phy_interface_t interface,int speed,int duplex,bool tx_pause,bool rx_pause) macb_mac_link_up() argument
776 macb_mac_select_pcs(struct phylink_config * config,phy_interface_t interface) macb_mac_select_pcs() argument
835 macb_get_pcs_fixed_state(struct phylink_config * config,struct phylink_link_state * state) macb_get_pcs_fixed_state() argument
2551 void *tx, *rx; macb_alloc_consistent() local
2699 u32 config; gem_mdc_clk_div() local
2724 u32 config; macb_mdc_clk_div() local
2818 u32 config; macb_init_hw() local
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/linux/arch/arm/boot/dts/axis/
H A Dartpec6.dtsi2 * Device Tree Source for the Axis ARTPEC-6 SoC
4 * This file is dual-licensed: you can use it either under the terms
43 #include <dt-bindings/interrupt-controller/arm-gic.h>
44 #include <dt-bindings/dma/nbpfaxi.h>
45 #include <dt-bindings/clock/axis,artpec6-clkctrl.h>
48 #address-cells = <1>;
49 #size-cells = <1>;
51 interrupt-parent = <&intc>;
54 #address-cells = <1>;
55 #size-cells = <0>;
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/linux/drivers/net/ethernet/intel/idpf/
H A Dvirtchnl2.h1 /* SPDX-License-Identifier: GPL-2.0-only */
16 * all the structures in this header follow little-endian format.
90 * enum virtchnl2_vport_type - Type of virtual port.
98 * enum virtchnl2_queue_model - Type of queue model.
108 * In the split queue model, hardware uses transmit completion queues to post
110 * descriptor queues to post descriptors to hardware.
112 * queue, while software uses receive buffer queues to post buffers to hardware.
230 * enum virtchnl2_action_types - Available actions for sideband flow steering
254 * enum virtchnl2_txq_sched_mode - Transmit Queue Scheduling Modes.
269 * enum virtchnl2_rxq_flags - Receive Queue Feature flags.
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/linux/drivers/net/ethernet/intel/ice/
H A Dice.h1 /* SPDX-License-Identifier: GPL-2.0 */
19 #include <linux/dma-mapping.h>
89 #define ICE_MAX_NUM_DESC_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? \
115 #define ICE_MAX_RXQS_PER_TC 256 /* Used when setting VSI context per TC Rx queues */
125 #define ICE_MAX_MTU (ICE_AQ_SET_MAC_FRAME_SIZE_MAX - ICE_ETH_PKT_HDR_PAD)
133 #define ICE_TX_DESC(R, i) (&(((struct ice_tx_desc *)((R)->desc))[i]))
134 #define ICE_RX_DESC(R, i) (&(((union ice_32b_rx_flex_desc *)((R)->des
480 struct ice_ring_container rx; global() member
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/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mp-beacon-som.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
18 reg_wl_bt: regulator-wifi-bt {
19 compatible = "regulator-fixed";
20 pinctrl-names = "default";
21 pinctrl-0 = <&pinctrl_reg_wl_bt>;
22 regulator-name = "wl-bt-pow-dwn";
23 regulator-min-microvolt = <3300000>;
24 regulator-max-microvolt = <3300000>;
26 startup-delay-us = <70000>;
27 regulator-always-on;
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/linux/Documentation/networking/device_drivers/ethernet/freescale/dpaa2/
H A Doverview.rst16 DPAA2 is a hardware architecture designed for high-speeed network
23 DPAA2 hardware resources. The MC provides an object-based abstraction for
25 The MC uses DPAA2 hardware resources such as queues, buffer pools, and
28 The MC provides memory-mapped I/O command interfaces (MC portals)
34 +--------------------------------------+
38 +-----------------------------|--------+
41 | config,use,destroy)
44 +------------------------| mc portal |-+
46 | +- - - - - - - - - - - - -V- - -+ |
50 | +- - - - - - - - - - - - - - - -+ |
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/linux/drivers/net/ethernet/google/gve/
H A Dgve_main.c1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 * Copyright (C) 2015-2024 Google LLC
34 #define GVE_VERSION_PREFIX "GVE-"
49 driver_info = dma_alloc_coherent(&priv->pdev->dev, in gve_verify_driver_compatibility()
53 return -ENOMEM; in gve_verify_driver_compatibility()
67 strscpy(driver_info->os_version_str1, utsname()->releas in gve_verify_driver_compatibility()
825 struct gve_rx_ring *rx = &priv->rx[idx]; gve_rx_get_qpl() local
1170 struct gve_rx_ring *rx; gve_unreg_xsk_pool() local
1188 struct gve_rx_ring *rx; gve_reg_xsk_pool() local
1216 struct gve_rx_ring *rx = &priv->rx[i]; gve_unreg_xdp_info() local
1236 struct gve_rx_ring *rx; gve_reg_xdp_info() local
2667 struct gve_rx_ring *rx = &priv->rx[idx]; gve_get_rx_queue_stats() local
2694 gve_get_base_stats(struct net_device * dev,struct netdev_queue_stats_rx * rx,struct netdev_queue_stats_tx * tx) gve_get_base_stats() argument
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/linux/arch/riscv/boot/dts/sophgo/
H A Dcv180x.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 #include <dt-bindings/clock/sophgo,cv1800.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include "cv18xx-reset.h"
13 #address-cells = <1>;
14 #size-cells = <1>;
17 compatible = "fixed-clock";
18 clock-output-names = "osc_25m";
19 #clock-cells = <0>;
[all …]
/linux/drivers/net/caif/
H A Dcaif_virtio.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) ST-Ericsson AB 2013
21 #include <linux/dma-mapping.h>
33 /* Defaults used if virtio config space is unavailable */
41 /* struct cfv_napi_contxt - NAPI context info
46 * used to indicate invalid head-id.
53 /* struct cfv_stats - statistics for debugfs
54 * @rx_napi_complete: Number of NAPI completions (RX)
55 * @rx_napi_resched: Number of calls where the full quota was used (RX)
56 * @rx_nomem: Number of SKB alloc failures (RX)
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