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/freebsd/sys/contrib/device-tree/Bindings/net/
H A Dsnps,dwmac.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandre Torgue <alexandre.torgue@foss.st.com>
11 - Giuseppe Cavallaro <peppe.cavallaro@st.com>
12 - Jos
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H A Dintel,dwmac-plat.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/intel,dwmac-plat.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vineetha G. Jaya Kumaran <vineetha.g.jaya.kumaran@intel.com>
17 - intel,keembay-dwmac
19 - compatible
22 - $ref: snps,dwmac.yaml#
27 - items:
28 - enum:
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/freebsd/sys/contrib/device-tree/src/arm64/rockchip/
H A Drk3588.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include "rk3588-pinctrl.dtsi"
11 compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon";
16 compatible = "rockchip,rk3588-pipe-phy-gr
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H A Drk3568.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
12 compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci";
16 clock-names = "sata", "pmalive", "rxoob";
19 phy-names = "sata-phy";
20 ports-implemented = <0x1>;
21 power-domains = <&power RK3568_PD_PIPE>;
26 compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
31 compatible = "rockchip,rk3568-qos", "syscon";
36 compatible = "rockchip,rk3568-qos", "syscon";
41 compatible = "rockchip,rk3568-qos", "syscon";
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/freebsd/sys/contrib/device-tree/src/arm64/qcom/
H A Dsa8540p-ride.dts1 // SPDX-License-Identifier: BSD-3-Clause
7 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
13 #include "sa8540p-pmics.dtsi"
17 compatible = "qcom,sa8540p-rid
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H A Dsa8155p-adp.dts1 // SPDX-License-Identifier: BSD-3-Clause
6 /dts-v1/;
8 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
9 #include <dt-bindings/gpio/gpio.h>
16 compatible = "qcom,sa8155p-adp", "qcom,sa8155p";
24 stdout-path = "serial0:115200n8";
27 vreg_3p3: vreg-3p3-regulator {
28 compatible = "regulator-fixed";
29 regulator-name = "vreg_3p3";
30 regulator-min-microvolt = <3300000>;
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/freebsd/sys/dev/ixgbe/
H A Dixgbe_dcb_82599.c2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2020, Intel Corporation
41 * ixgbe_dcb_get_tc_stats_82599 - Returns status for each traffic class
62 stats->qptc[tc] += IXGBE_READ_REG(hw, IXGBE_QPTC(tc)); in ixgbe_dcb_get_tc_stats_82599()
64 stats->qbtc[tc] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(tc)); in ixgbe_dcb_get_tc_stats_82599()
65 stats->qbtc[tc] += in ixgbe_dcb_get_tc_stats_82599()
68 stats->qprc[tc] += IXGBE_READ_REG(hw, IXGBE_QPRC(tc)); in ixgbe_dcb_get_tc_stats_82599()
70 stats->qbrc[tc] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(tc)); in ixgbe_dcb_get_tc_stats_82599()
71 stats->qbrc[tc] += in ixgbe_dcb_get_tc_stats_82599()
75 stats->qprdc[tc] += IXGBE_READ_REG(hw, IXGBE_QPRDC(tc)); in ixgbe_dcb_get_tc_stats_82599()
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H A Dixgbe_dcb_82598.c2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2020, Intel Corporation
41 * ixgbe_dcb_get_tc_stats_82598 - Return status data for each traffic class
62 stats->qptc[tc] += IXGBE_READ_REG(hw, IXGBE_QPTC(tc)); in ixgbe_dcb_get_tc_stats_82598()
64 stats->qbtc[tc] += IXGBE_READ_REG(hw, IXGBE_QBTC(tc)); in ixgbe_dcb_get_tc_stats_82598()
66 stats->qprc[tc] += IXGBE_READ_REG(hw, IXGBE_QPRC(tc)); in ixgbe_dcb_get_tc_stats_82598()
68 stats->qbrc[tc] += IXGBE_READ_REG(hw, IXGBE_QBRC(tc)); in ixgbe_dcb_get_tc_stats_82598()
75 * ixgbe_dcb_get_pfc_stats_82598 - Returns CBFC status data
95 stats->pxofftxc[tc] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(tc)); in ixgbe_dcb_get_pfc_stats_82598()
97 stats->pxoffrxc[tc] += IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(tc)); in ixgbe_dcb_get_pfc_stats_82598()
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/freebsd/sys/contrib/device-tree/src/arm/axis/
H A Dartpec6.dtsi2 * Device Tree Source for the Axis ARTPEC-6 SoC
4 * This file is dual-licensed: you can use it either under the terms
43 #include <dt-bindings/interrupt-controller/arm-gic.h>
44 #include <dt-bindings/dma/nbpfaxi.h>
45 #include <dt-bindings/clock/axis,artpec6-clkctrl.h>
48 #address-cells = <1>;
49 #size-cells = <1>;
51 interrupt-parent = <&intc>;
54 #address-cells = <1>;
55 #size-cells = <0>;
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/freebsd/sys/contrib/device-tree/src/arm/rockchip/
H A Drv1126.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rockchip,rv1126-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-binding
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/freebsd/sys/dev/ixl/
H A Dvirtchnl.h3 Copyright (c) 2013-2018, Intel Corporation
38 * This header file describes the VF-PF communication protocol used
42 * desc->opcode is always aqc_opc_send_msg_to_pf
50 * have a maximum of sixteen queues for all of its VSIs.
59 * queues and interrupts. After these operations are complete, the VF
60 * driver may start its queues, optionally add MAC and VLAN filters, and
72 VIRTCHNL_ERR_PARAM = -5,
73 VIRTCHNL_STATUS_ERR_OPCODE_MISMATCH = -38,
74 VIRTCHNL_STATUS_ERR_CQP_COMPL_ERROR = -39,
75 VIRTCHNL_STATUS_ERR_INVALID_VF_ID = -40,
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/freebsd/sys/dev/neta/
H A Dif_mvnetareg.h46 /* XXX: Currently multi-queue can be used on the Tx side only */
53 #if MVNETA_TX_QNUM_MAX & (MVNETA_TX_QNUM_MAX - 1) != 0
56 #if MVNETA_RX_QNUM_MAX & (MVNETA_RX_QNUM_MAX - 1) != 0
62 #define MVNETA_TX_QUEUE_ALL ((1<<MVNETA_TX_QNUM_MAX)-1)
63 #define MVNETA_RX_QUEUE_ALL ((1<<MVNETA_RX_QNUM_MAX)-1)
99 /* Rx DMA Hardware Parser Registers */
117 /* Rx DMA Miscellaneous Registers */
118 #define MVNETA_PMFS 0x247c /* Port Rx Minimal Frame Size */
119 #define MVNETA_PDFC 0x2484 /* Port Rx Discard Frame Counter */
123 /* Rx DMA Networking Controller Miscellaneous Registers */
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H A Dif_mvnetavar.h61 bus_read_4((sc)->res[0], (reg))
63 bus_write_4((sc)->res[0], (reg), (val))
66 bus_read_region_4((sc)->res[0], (reg), (val), (c))
68 bus_write_region_4((sc)->res[0], (reg), (val), (c))
71 bus_read_4((sc)->res[0], MVNETA_PORTMIB_BASE + (reg))
76 #define MVNETA_IS_QUEUE_SET(queues, q) \ argument
77 ((((queues) >> (q)) & 0x1))
80 * EEE: Lower Power Idle config
92 * the ethernet device has 8 rx/tx DMA queues. each of queue has its own
113 /* Virtual address of the RX buffer */
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/freebsd/sys/dev/enic/
H A Dvnic_resource.h1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2008-2017 Cisco Systems, Inc. All rights reserved.
19 RES_TYPE_EOL, /* End-of-list */
20 RES_TYPE_WQ, /* Work queues */
21 RES_TYPE_RQ, /* Receive queues */
22 RES_TYPE_CQ, /* Completion queues */
24 RES_TYPE_NIC_CFG, /* Enet NIC config registers */
28 RES_TYPE_RX_STATS, /* Netblock Rx statistic regs */
30 RES_TYPE_INTR_TABLE, /* MSI/MSI-X Interrupt table */
31 RES_TYPE_INTR_PBA, /* MSI/MSI-X PBA table */
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/freebsd/sys/contrib/device-tree/src/arm/ti/keystone/
H A Dkeystone-k2hk-netcp.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2015-2017 Texas Instruments Incorporated - http://www.ti.com/
9 compatible = "ti,keystone-navigator-qmss";
10 dma-coherent;
11 #address-cells = <1>;
12 #size-cell
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H A Dkeystone-k2g-netcp.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
9 compatible = "ti,66ak2g-navss-qm";
10 dma-coherent;
11 #address-cells = <1>;
12 #size-cells = <1>;
13 power-domain
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/freebsd/sys/dev/iavf/
H A Dvirtchnl.h1 /* SPDX-License-Identifier: BSD-3-Clause */
36 * This header file describes the VF-PF communication protocol used
40 * desc->opcode is always aqc_opc_send_msg_to_pf
48 * have a maximum of sixteen queues for all of its VSIs.
57 * queues and interrupts. After these operations are complete, the VF
58 * driver may start its queues, optionally add MAC and VLAN filters, and
70 VIRTCHNL_STATUS_ERR_PARAM = -5,
71 VIRTCHNL_STATUS_ERR_NO_MEMORY = -18,
72 VIRTCHNL_STATUS_ERR_OPCODE_MISMATCH = -38,
73 VIRTCHNL_STATUS_ERR_CQP_COMPL_ERROR = -39,
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/freebsd/share/man/man9/
H A Diflibdd.9195 .Bl -ohang -offset indent
198 queues.
200 the hardware transmit queues.
201 ntxqs is the number of queues per qset.
205 queues.
207 the hardware receive queues.
208 nrxqs is the number of queues per qset.
211 Mandatory function that frees the allocated queues and associated transmit
221 .Bl -ohang -offset indent
233 Optional function called by the VLAN config eventhandler.
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/freebsd/sys/dev/dpaa2/
H A Ddpaa2_ni.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright © 2021-2023 Dmitry Salychev
210 uint8_t queues; member
241 * other commands on the queue through DPIO. Note that Tx queues
242 * are logical queues and not all management commands are available
248 * and Rx error queues).
249 * idx: Selects a specific queue out of the set of queues in a TC.
251 * ignored for QUEUE_TYPE 3 (Rx error queue). For access to the
259 * destination DPCON or DPIO - 1. This field is ignored for
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/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dimx8mp-evk.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/phy/phy-imx8-pcie.h>
13 compatible = "fsl,imx8mp-evk", "fsl,imx8mp";
16 stdout-path = &uart2;
19 hdmi-connecto
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H A Dimx8-ss-conn.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2019 NXP
7 #include <dt-bindings/clock/imx8-lpcg.h>
8 #include <dt-bindings/firmware/imx/rsrc.h>
10 conn_axi_clk: clock-conn-axi {
11 compatible = "fixed-cloc
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/freebsd/sys/dev/liquidio/base/
H A Dlio_config.h41 /*--------------------------CONFIG VALUES------------------------*/
90 #define LIO_CN23XX_MAX_INPUT_JABBER (LIO_CN23XX_PKI_MAX_FRAME_SIZE - \
101 /* Macros to get octeon config params */
102 #define LIO_GET_IQ_CFG(cfg) ((cfg)->iq)
103 #define LIO_GET_IQ_MAX_Q_CFG(cfg) ((cfg)->iq.max_iqs)
104 #define LIO_GET_IQ_INSTR_TYPE_CFG(cfg) ((cfg)->iq.instr_type)
106 #define LIO_GET_IQ_INTR_PKT_CFG(cfg) ((cfg)->iq.iq_intr_pkt)
108 #define LIO_GET_OQ_MAX_Q_CFG(cfg) ((cfg)->oq.max_oqs)
109 #define LIO_GET_OQ_PKTS_PER_INTR_CFG(cfg) ((cfg)->oq.pkts_per_intr)
110 #define LIO_GET_OQ_REFILL_THRESHOLD_CFG(cfg) ((cfg)->oq.refill_threshold)
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/freebsd/sys/dev/ice/
H A Dif_ice_iflib.c1 /* SPDX-License-Identifier: BSD-3-Clause */
252 * scctx->isc_tx_tso_size_max + the VLAN header is a valid size.
256 * DMA tag. However, scctx->isc_tx_tso_segsize_max is used to set the
285 * IFLIB_SKIP_MSIX allows the driver to handle allocating MSI-X
308 /* Static driver-wide sysctls */
312 * ice_pci_mapping - Map PCI BAR memory
323 rc = ice_map_bar(sc->dev, &sc->bar0, 0); in ice_pci_mapping()
331 * ice_free_pci_mapping - Release PCI BAR memory
340 ice_free_bar(sc->dev, &sc->bar0); in ice_free_pci_mapping()
348 * ice_register - register device method callback
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/freebsd/sys/contrib/dev/iwlwifi/
H A Diwl-fh.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * Copyright (C) 2005-2014, 2018-2021, 2023-2024 Intel Corporation
4 * Copyright (C) 2015-2017 Intel Deutschland GmbH
12 #include "iwl-tran
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/freebsd/share/man/man4/
H A Dbxe.435 .Bd -ragged -offset indent
42 .Bd -literal -offset indent
51 tagging, checksum offload (IPv4, TCP, UDP, IPv6-TCP, IPv6-UDP), MSI-X
60 .Bl -bullet -compact
70 QLogic NetXtreme II BCM57712-MF 10Gb
74 QLogic NetXtreme II BCM57800-MF 10Gb
78 QLogic NetXtreme II BCM57810-MF 10Gb
82 QLogic NetXtreme II BCM57840-MF 10Gb
92 .Bl -tag -width indent
115 Sets the default number of fast path packet processing queues.
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