1*9c067b84SDoug Ambrisko /* SPDX-License-Identifier: BSD-3-Clause 2*9c067b84SDoug Ambrisko * Copyright 2008-2017 Cisco Systems, Inc. All rights reserved. 3*9c067b84SDoug Ambrisko * Copyright 2007 Nuova Systems, Inc. All rights reserved. 4*9c067b84SDoug Ambrisko */ 5*9c067b84SDoug Ambrisko 6*9c067b84SDoug Ambrisko #ifndef _VNIC_RESOURCE_H_ 7*9c067b84SDoug Ambrisko #define _VNIC_RESOURCE_H_ 8*9c067b84SDoug Ambrisko 9*9c067b84SDoug Ambrisko #define VNIC_RES_MAGIC 0x766E6963L /* 'vnic' */ 10*9c067b84SDoug Ambrisko #define VNIC_RES_VERSION 0x00000000L 11*9c067b84SDoug Ambrisko #define MGMTVNIC_MAGIC 0x544d474dL /* 'MGMT' */ 12*9c067b84SDoug Ambrisko #define MGMTVNIC_VERSION 0x00000000L 13*9c067b84SDoug Ambrisko 14*9c067b84SDoug Ambrisko /* The MAC address assigned to the CFG vNIC is fixed. */ 15*9c067b84SDoug Ambrisko #define MGMTVNIC_MAC { 0x02, 0x00, 0x54, 0x4d, 0x47, 0x4d } 16*9c067b84SDoug Ambrisko 17*9c067b84SDoug Ambrisko /* vNIC resource types */ 18*9c067b84SDoug Ambrisko enum vnic_res_type { 19*9c067b84SDoug Ambrisko RES_TYPE_EOL, /* End-of-list */ 20*9c067b84SDoug Ambrisko RES_TYPE_WQ, /* Work queues */ 21*9c067b84SDoug Ambrisko RES_TYPE_RQ, /* Receive queues */ 22*9c067b84SDoug Ambrisko RES_TYPE_CQ, /* Completion queues */ 23*9c067b84SDoug Ambrisko RES_TYPE_MEM, /* Window to dev memory */ 24*9c067b84SDoug Ambrisko RES_TYPE_NIC_CFG, /* Enet NIC config registers */ 25*9c067b84SDoug Ambrisko RES_TYPE_RSS_KEY, /* Enet RSS secret key */ 26*9c067b84SDoug Ambrisko RES_TYPE_RSS_CPU, /* Enet RSS indirection table */ 27*9c067b84SDoug Ambrisko RES_TYPE_TX_STATS, /* Netblock Tx statistic regs */ 28*9c067b84SDoug Ambrisko RES_TYPE_RX_STATS, /* Netblock Rx statistic regs */ 29*9c067b84SDoug Ambrisko RES_TYPE_INTR_CTRL, /* Interrupt ctrl table */ 30*9c067b84SDoug Ambrisko RES_TYPE_INTR_TABLE, /* MSI/MSI-X Interrupt table */ 31*9c067b84SDoug Ambrisko RES_TYPE_INTR_PBA, /* MSI/MSI-X PBA table */ 32*9c067b84SDoug Ambrisko RES_TYPE_INTR_PBA_LEGACY, /* Legacy intr status */ 33*9c067b84SDoug Ambrisko RES_TYPE_DEBUG, /* Debug-only info */ 34*9c067b84SDoug Ambrisko RES_TYPE_DEV, /* Device-specific region */ 35*9c067b84SDoug Ambrisko RES_TYPE_DEVCMD, /* Device command region */ 36*9c067b84SDoug Ambrisko RES_TYPE_PASS_THRU_PAGE, /* Pass-thru page */ 37*9c067b84SDoug Ambrisko RES_TYPE_SUBVNIC, /* subvnic resource type */ 38*9c067b84SDoug Ambrisko RES_TYPE_MQ_WQ, /* MQ Work queues */ 39*9c067b84SDoug Ambrisko RES_TYPE_MQ_RQ, /* MQ Receive queues */ 40*9c067b84SDoug Ambrisko RES_TYPE_MQ_CQ, /* MQ Completion queues */ 41*9c067b84SDoug Ambrisko RES_TYPE_DEPRECATED1, /* Old version of devcmd 2 */ 42*9c067b84SDoug Ambrisko RES_TYPE_DEVCMD2, /* Device control region */ 43*9c067b84SDoug Ambrisko RES_TYPE_MAX, /* Count of resource types */ 44*9c067b84SDoug Ambrisko }; 45*9c067b84SDoug Ambrisko 46*9c067b84SDoug Ambrisko struct vnic_resource_header { 47*9c067b84SDoug Ambrisko u32 magic; 48*9c067b84SDoug Ambrisko u32 version; 49*9c067b84SDoug Ambrisko }; 50*9c067b84SDoug Ambrisko 51*9c067b84SDoug Ambrisko struct mgmt_barmap_hdr { 52*9c067b84SDoug Ambrisko u32 magic; /* magic number */ 53*9c067b84SDoug Ambrisko u32 version; /* header format version */ 54*9c067b84SDoug Ambrisko u16 lif; /* loopback lif for mgmt frames */ 55*9c067b84SDoug Ambrisko u16 pci_slot; /* installed pci slot */ 56*9c067b84SDoug Ambrisko char serial[16]; /* card serial number */ 57*9c067b84SDoug Ambrisko }; 58*9c067b84SDoug Ambrisko 59*9c067b84SDoug Ambrisko struct vnic_resource { 60*9c067b84SDoug Ambrisko u8 type; 61*9c067b84SDoug Ambrisko u8 bar; 62*9c067b84SDoug Ambrisko u8 pad[2]; 63*9c067b84SDoug Ambrisko u32 bar_offset; 64*9c067b84SDoug Ambrisko u32 count; 65*9c067b84SDoug Ambrisko }; 66*9c067b84SDoug Ambrisko 67*9c067b84SDoug Ambrisko #endif /* _VNIC_RESOURCE_H_ */ 68