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/linux/Documentation/devicetree/bindings/soc/fsl/cpm_qe/
H A Dfsl,cpm1-tsa.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,cpm1-tsa.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: PowerQUICC CPM Time-slot assigner (TSA) controller
10 - Herve Codina <herve.codina@bootlin.com>
13 The TSA is the time-slot assigner that can be found on some PowerQUICC SoC.
14 Its purpose is to route some TDM time-slots to other internal serial
20 - enum:
21 - fsl,mpc885-tsa
[all …]
H A Dfsl,qe-tsa.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe-tsa.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: PowerQUICC QE Time-slot assigner (TSA) controller
10 - Herve Codina <herve.codina@bootlin.com>
13 The TSA is the time-slot assigner that can be found on some PowerQUICC SoC.
14 Its purpose is to route some TDM time-slots to other internal serial
20 - enum:
21 - fsl,mpc8321-tsa
[all …]
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6qdl-dhcom-drc02.dtsi1 // SPDX-License-Identifier: GPL-2.0+
8 stdout-path = "serial0:115200n8";
13 * Special SoM hardware required which uses the pins from micro SD card. The
14 * pins SD3_DAT0 and SD3_DAT1 are muxed as can2 Tx and Rx. The signals for can2
15 * Tx and Rx are routed to the DHCOM UART1 rts/cts pins. Therefore the micro SD
17 * pins, see uart1 and usdhc3 node below.
26 * GPIO line, however the i.MX6 UART driver assumes RX happens
28 * line. Hence, the RX is always enabled here.
30 rs485-rx-en-hog {
31 gpio-hog;
[all …]
/linux/arch/arm64/boot/dts/qcom/
H A Dsa8540p-ride.dts1 // SPDX-License-Identifier: BSD-3-Clause
7 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
13 #include "sa8540p-pmics.dtsi"
17 compatible = "qcom,sa8540p-ride", "qcom,sa8540p";
29 stdout-path = "serial0:115200n8";
34 regulators-0 {
35 compatible = "qcom,pm8150-rpmh-regulators";
36 qcom,pmic-id = "a";
[all …]
H A Dqcs404-evb-4000.dts1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include "qcs404-evb.dtsi"
13 compatible = "qcom,qcs404-evb-4000", "qcom,qcs404-evb",
20 snps,reset-gpio = <&tlmm 60 GPIO_ACTIVE_LOW>;
21 snps,reset-active-low;
22 snps,reset-delays-us = <0 10000 10000>;
24 pinctrl-names = "default";
25 pinctrl-0 = <&ethernet_defaults>;
[all …]
H A Dsm6125.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,dispcc-sm6125.h>
7 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
8 #include <dt-bindings/clock/qcom,gcc-sm6125.h>
9 #include <dt-bindings/clock/qcom,rpmcc.h>
10 #include <dt-bindings/dma/qcom-gpi.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/power/qcom-rpmpd.h>
16 interrupt-parent = <&intc>;
[all …]
/linux/arch/arm/boot/dts/rockchip/
H A Drk3066a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/pinctrl/rockchip.h>
9 #include <dt-bindings/clock/rk3066a-cru.h>
10 #include <dt-bindings/power/rk3066-power.h>
22 #address-cells = <1>;
23 #size-cells = <0>;
24 enable-method = "rockchip,rk3066-smp";
28 compatible = "arm,cortex-a9";
29 next-level-cache = <&L2>;
[all …]
H A Drk3128.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/clock/rk3128-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3128-power.h>
15 interrupt-parent = <&gic>;
16 #address-cells = <1>;
17 #size-cells = <1>;
[all …]
H A Drv1126-pinctrl.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <arm64/rockchip/rockchip-pinconf.dtsi>
15 /omit-if-no-ref/
16 clk_out_ethernetm1_pins: clk-out-ethernetm1-pins {
17 rockchip,pins =
23 /omit-if-no-ref/
24 emmc_rstnout: emmc-rstnout {
25 rockchip,pins =
29 /omit-if-no-ref/
[all …]
/linux/sound/soc/fsl/
H A Dfsl_sai.c1 // SPDX-License-Identifier: GPL-2.0+
5 // Copyright 2012-2015 Freescale Semiconductor, Inc.
22 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
26 #include "imx-pcm.h"
44 * fsl_sai_dir_is_synced - Check if stream is synced by the opposite stream
55 int adir = (dir == TX) ? RX : TX; in fsl_sai_dir_is_synced()
58 return !sai->synchronou in fsl_sai_dir_is_synced()
572 u32 pins, bclk; fsl_sai_hw_params() local
1336 u32 rx, tx, type; fsl_sai_read_dlcfg() local
[all...]
/linux/arch/arm/boot/dts/microchip/
H A Dsama5d3.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * sama5d3.dtsi - Device Tree Include file for SAMA5D3 family SoC
10 #include <dt-bindings/dma/at91.h>
11 #include <dt-bindings/pinctrl/at91.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/clock/at91.h>
15 #include <dt-bindings/mfd/at91-usart.h>
18 #address-cells = <1>;
19 #size-cells = <1>;
[all …]
H A Dsama5d4.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * sama5d4.dtsi - Device Tree Include file for SAMA5D4 family SoC
9 #include <dt-bindings/clock/at91.h>
10 #include <dt-bindings/dma/at91.h>
11 #include <dt-bindings/mfd/at91-usart.h>
12 #include <dt-bindings/pinctrl/at91.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
14 #include <dt-bindings/gpio/gpio.h>
17 #address-cells = <1>;
18 #size-cells = <1>;
[all …]
H A Dat91sam9x5.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * at91sam9x5.dtsi - Device Tree Include file for AT91SAM9x5 family SoC
11 #include <dt-bindings/dma/at91.h>
12 #include <dt-bindings/pinctrl/at91.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/clock/at91.h>
16 #include <dt-bindings/mfd/at91-usart.h>
19 #address-cells = <1>;
20 #size-cells = <1>;
[all …]
/linux/arch/arm64/boot/dts/tesla/
H A Dfsd-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Tesla Full Self-Driving SoC device tree source
5 * Copyright (c) 2017-2021 Samsung Electronics Co., Ltd.
7 * Copyright (c) 2017-2021 Tesla, Inc.
11 #include "fsd-pinctrl.h"
14 gpf0: gpf0-gpio-bank {
15 gpio-controller;
16 #gpio-cells = <2>;
18 interrupt-controller;
19 #interrupt-cells = <2>;
[all …]
/linux/drivers/net/ethernet/intel/i40e/
H A Di40e_ptp.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2013 - 2018 Intel Corporation. */
5 #include <linux/posix-clock.h>
39 CANT_DO_PINS = -1,
52 end = -2,
66 led_end = -2,
142 struct i40e_ptp_pins_settings *pins);
145 * i40e_ptp_extts0_work - workqueue task function
154 struct i40e_hw *hw = &pf->hw; in i40e_ptp_extts0_work()
169 event.index = hw->pf_id; in i40e_ptp_extts0_work()
[all …]
/linux/drivers/pinctrl/
H A Dpinctrl-artpec6.c2 * Driver for the Axis ARTPEC-6 pin controller
18 #include <linux/pinctrl/pinconf-generic.h>
24 #include "pinctrl-utils.h"
26 #define ARTPEC6_LAST_PIN 97 /* 97 pins in pinmux */
59 struct pinctrl_pin_desc *pins; member
69 const unsigned int *pins; member
80 /* pins */
215 .pins = cpuclkout_pins0,
221 .pins = udlclkout_pins0,
227 .pins = i2c1_pins0,
[all …]
/linux/arch/arm/boot/dts/broadcom/
H A Dbcm2835-common.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 interrupt-parent = <&intc>;
11 dma: dma-controller@7e007000 {
12 compatible = "brcm,bcm2835-dma";
25 /* dma channel 11-14 share one irq */
32 interrupt-names = "dma0",
47 "dma-shared-all";
48 #dma-cells = <1>;
49 brcm,dma-channel-mask = <0x7f35>;
52 intc: interrupt-controller@7e00b200 {
[all …]
H A Dbcm2711.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/soc/bcm2835-pm.h>
10 #address-cells = <2>;
11 #size-cells = <1>;
13 interrupt-parent = <&gicv2>;
16 compatible = "brcm,bcm2711-vc5";
20 clk_27MHz: clk-27M {
21 #clock-cells = <0>;
22 compatible = "fixed-clock";
[all …]
/linux/Documentation/devicetree/bindings/media/
H A Dst-rc.txt1 Device-Tree bindings for ST IRB IP
4 - compatible: Should contain "st,comms-irb".
5 - reg: Base physical address of the controller and length of memory
7 - interrupts: interrupt-specifier for the sole interrupt generated by
10 - rx-mode: can be "infrared" or "uhf". This property specifies the L1
11 protocol used for receiving remote control signals. rx-mode should
12 be present iff the rx pins are wired up.
13 - tx-mode: should be "infrared". This property specifies the L1
14 protocol used for transmitting remote control signals. tx-mode should
15 be present iff the tx pins are wired up.
[all …]
/linux/arch/arm64/boot/dts/allwinner/
H A Dsun50i-h616.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/sun50i-h616-ccu.h>
8 #include <dt-bindings/clock/sun50i-h6-r-ccu.h>
9 #include <dt-bindings/clock/sun6i-rtc.h>
10 #include <dt-bindings/reset/sun50i-h616-ccu.h>
11 #include <dt-bindings/reset/sun50i-h6-r-ccu.h>
12 #include <dt-bindings/thermal/thermal.h>
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
[all …]
/linux/arch/arm/boot/dts/allwinner/
H A Dsunxi-h3-h5.dtsi4 * This file is dual-licensed: you can use it either under the terms
43 #include <dt-bindings/clock/sun6i-rtc.h>
44 #include <dt-bindings/clock/sun8i-de2.h>
45 #include <dt-bindings/clock/sun8i-h3-ccu.h>
46 #include <dt-bindings/clock/sun8i-r-ccu.h>
47 #include <dt-bindings/interrupt-controller/arm-gic.h>
48 #include <dt-bindings/reset/sun8i-de2.h>
49 #include <dt-bindings/reset/sun8i-h3-ccu.h>
50 #include <dt-bindings/reset/sun8i-r-ccu.h>
53 interrupt-parent = <&gic>;
[all …]
H A Dsun6i-a31.dtsi4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * This file is dual-licensed: you can use it either under the terms
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/thermal/thermal.h>
48 #include <dt-bindings/clock/sun6i-a31-ccu.h>
49 #include <dt-bindings/clock/sun6i-rtc.h>
50 #include <dt-bindings/reset/sun6i-a31-ccu.h>
53 interrupt-parent = <&gic>;
54 #address-cells = <1>;
55 #size-cells = <1>;
[all …]
/linux/arch/arm/boot/dts/xilinx/
H A Dzynq-zc702.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2011 - 2014 Xilinx
6 /dts-v1/;
7 #include "zynq-7000.dtsi"
8 #include <dt-bindings/gpio/gpio.h>
12 compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000";
31 stdout-path = "serial0:115200n8";
34 gpio-keys {
35 compatible = "gpio-keys";
37 switch-14 {
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mp-beacon-som.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
18 reg_wl_bt: regulator-wifi-bt {
19 compatible = "regulator-fixed";
20 pinctrl-names = "default";
21 pinctrl-0 = <&pinctrl_reg_wl_bt>;
22 regulator-name = "wl-bt-pow-dwn";
23 regulator-min-microvolt = <3300000>;
24 regulator-max-microvolt = <3300000>;
26 startup-delay-us = <70000>;
27 regulator-always-on;
[all …]
/linux/arch/arm64/boot/dts/ti/
H A Dk3-j721e-evm-gesi-exp-board.dtso1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
8 * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
11 /dts-v1/;
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/net/ti-dp83867.h>
17 #include "k3-pinctrl.h"
21 ethernet1 = "/bus@100000/ethernet@c000000/ethernet-ports/port@1";
22 ethernet2 = "/bus@100000/ethernet@c000000/ethernet-ports/port@2";
23 ethernet3 = "/bus@100000/ethernet@c000000/ethernet-ports/port@3";
24 ethernet4 = "/bus@100000/ethernet@c000000/ethernet-ports/port@4";
[all …]

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