1*724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0+ 2*724ba675SRob Herring/* 3*724ba675SRob Herring * Copyright (C) 2021 DH electronics GmbH 4*724ba675SRob Herring */ 5*724ba675SRob Herring 6*724ba675SRob Herring/ { 7*724ba675SRob Herring chosen { 8*724ba675SRob Herring stdout-path = "serial0:115200n8"; 9*724ba675SRob Herring }; 10*724ba675SRob Herring}; 11*724ba675SRob Herring 12*724ba675SRob Herring/* 13*724ba675SRob Herring * Special SoM hardware required which uses the pins from micro SD card. The 14*724ba675SRob Herring * pins SD3_DAT0 and SD3_DAT1 are muxed as can2 Tx and Rx. The signals for can2 15*724ba675SRob Herring * Tx and Rx are routed to the DHCOM UART1 rts/cts pins. Therefore the micro SD 16*724ba675SRob Herring * card must be disabled and the uart1 rts/cts must be output on other DHCOM 17*724ba675SRob Herring * pins, see uart1 and usdhc3 node below. 18*724ba675SRob Herring */ 19*724ba675SRob Herring&can2 { 20*724ba675SRob Herring status = "okay"; 21*724ba675SRob Herring}; 22*724ba675SRob Herring 23*724ba675SRob Herring&gpio1 { 24*724ba675SRob Herring /* 25*724ba675SRob Herring * NOTE: On DRC02, the RS485_RX_En is controlled by a separate 26*724ba675SRob Herring * GPIO line, however the i.MX6 UART driver assumes RX happens 27*724ba675SRob Herring * during TX anyway and that it only controls drive enable DE 28*724ba675SRob Herring * line. Hence, the RX is always enabled here. 29*724ba675SRob Herring */ 30*724ba675SRob Herring rs485-rx-en-hog { 31*724ba675SRob Herring gpio-hog; 32*724ba675SRob Herring gpios = <18 0>; /* GPIO Q */ 33*724ba675SRob Herring line-name = "rs485-rx-en"; 34*724ba675SRob Herring output-low; 35*724ba675SRob Herring }; 36*724ba675SRob Herring}; 37*724ba675SRob Herring 38*724ba675SRob Herring&gpio3 { 39*724ba675SRob Herring gpio-line-names = 40*724ba675SRob Herring "", "", "", "", "", "", "", "", 41*724ba675SRob Herring "", "", "", "", "", "", "", "", 42*724ba675SRob Herring "", "", "", "", "", "", "", "", 43*724ba675SRob Herring "", "", "", "DRC02-In1", "", "", "", ""; 44*724ba675SRob Herring}; 45*724ba675SRob Herring 46*724ba675SRob Herring&gpio4 { 47*724ba675SRob Herring gpio-line-names = 48*724ba675SRob Herring "", "", "", "", "", "DHCOM-E", "DRC02-In2", "DHCOM-H", 49*724ba675SRob Herring "DHCOM-I", "DRC02-HW0", "", "", "", "", "", "", 50*724ba675SRob Herring "", "", "", "", "DRC02-Out1", "", "", "", 51*724ba675SRob Herring "", "", "", "", "", "", "", ""; 52*724ba675SRob Herring}; 53*724ba675SRob Herring 54*724ba675SRob Herring&gpio6 { 55*724ba675SRob Herring gpio-line-names = 56*724ba675SRob Herring "", "", "", "DRC02-Out2", "", "", "SOM-HW1", "", 57*724ba675SRob Herring "", "", "", "", "", "", "DRC02-HW2", "DRC02-HW1", 58*724ba675SRob Herring "", "", "", "", "", "", "", "", 59*724ba675SRob Herring "", "", "", "", "", "", "", ""; 60*724ba675SRob Herring}; 61*724ba675SRob Herring 62*724ba675SRob Herring&i2c1 { 63*724ba675SRob Herring eeprom@50 { 64*724ba675SRob Herring compatible = "atmel,24c04"; 65*724ba675SRob Herring reg = <0x50>; 66*724ba675SRob Herring pagesize = <16>; 67*724ba675SRob Herring }; 68*724ba675SRob Herring}; 69*724ba675SRob Herring 70*724ba675SRob Herring&uart1 { 71*724ba675SRob Herring /* 72*724ba675SRob Herring * Due to the use of can2 the signals for can2 Tx and Rx are routed to 73*724ba675SRob Herring * DHCOM UART1 rts/cts pins. Therefore this UART have to use DHCOM GPIOs 74*724ba675SRob Herring * for rts/cts. So configure DHCOM GPIO I as rts and GPIO M as cts. 75*724ba675SRob Herring */ 76*724ba675SRob Herring /delete-property/ uart-has-rtscts; 77*724ba675SRob Herring cts-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; /* GPIO M */ 78*724ba675SRob Herring pinctrl-0 = <&pinctrl_uart1 &pinctrl_dhcom_i &pinctrl_dhcom_m>; 79*724ba675SRob Herring pinctrl-names = "default"; 80*724ba675SRob Herring rts-gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; /* GPIO I */ 81*724ba675SRob Herring}; 82*724ba675SRob Herring 83*724ba675SRob Herring&uart5 { 84*724ba675SRob Herring /* 85*724ba675SRob Herring * On DRC02 this UART is used as RS485 interface and RS485_TX_En is 86*724ba675SRob Herring * controlled by DHCOM GPIO P. So remove rts/cts pins and the property 87*724ba675SRob Herring * uart-has-rtscts from this UART and add the DHCOM GPIO P pin via 88*724ba675SRob Herring * rts-gpios. The RS485_RX_En is controlled by DHCOM GPIO Q, see gpio1 89*724ba675SRob Herring * node above. 90*724ba675SRob Herring */ 91*724ba675SRob Herring /delete-property/ uart-has-rtscts; 92*724ba675SRob Herring linux,rs485-enabled-at-boot-time; 93*724ba675SRob Herring pinctrl-0 = <&pinctrl_uart5_core &pinctrl_dhcom_p &pinctrl_dhcom_q>; 94*724ba675SRob Herring pinctrl-names = "default"; 95*724ba675SRob Herring rts-gpios = <&gpio7 13 GPIO_ACTIVE_HIGH>; /* GPIO P */ 96*724ba675SRob Herring}; 97*724ba675SRob Herring 98*724ba675SRob Herring&usbh1 { 99*724ba675SRob Herring disable-over-current; 100*724ba675SRob Herring}; 101*724ba675SRob Herring 102*724ba675SRob Herring&usdhc2 { /* SD card */ 103*724ba675SRob Herring status = "okay"; 104*724ba675SRob Herring}; 105*724ba675SRob Herring 106*724ba675SRob Herring&usdhc3 { 107*724ba675SRob Herring /* 108*724ba675SRob Herring * Due to the use of can2 the micro SD card on module have to be 109*724ba675SRob Herring * disabled, because the pins SD3_DAT0 and SD3_DAT1 are muxed as 110*724ba675SRob Herring * can2 Tx and Rx. 111*724ba675SRob Herring */ 112*724ba675SRob Herring status = "disabled"; 113*724ba675SRob Herring}; 114*724ba675SRob Herring 115*724ba675SRob Herring&iomuxc { 116*724ba675SRob Herring pinctrl-0 = < 117*724ba675SRob Herring /* 118*724ba675SRob Herring * The following DHCOM GPIOs are used on this board. 119*724ba675SRob Herring * Therefore, they have been removed from the list below. 120*724ba675SRob Herring * I: uart1 rts 121*724ba675SRob Herring * M: uart1 cts 122*724ba675SRob Herring * P: uart5 rs485-tx-en 123*724ba675SRob Herring * Q: uart5 rs485-rx-en 124*724ba675SRob Herring */ 125*724ba675SRob Herring &pinctrl_hog_base 126*724ba675SRob Herring &pinctrl_dhcom_a &pinctrl_dhcom_b &pinctrl_dhcom_c 127*724ba675SRob Herring &pinctrl_dhcom_d &pinctrl_dhcom_e &pinctrl_dhcom_f 128*724ba675SRob Herring &pinctrl_dhcom_g &pinctrl_dhcom_h 129*724ba675SRob Herring &pinctrl_dhcom_j &pinctrl_dhcom_k &pinctrl_dhcom_l 130*724ba675SRob Herring &pinctrl_dhcom_n &pinctrl_dhcom_o 131*724ba675SRob Herring &pinctrl_dhcom_r 132*724ba675SRob Herring &pinctrl_dhcom_s &pinctrl_dhcom_t &pinctrl_dhcom_u 133*724ba675SRob Herring &pinctrl_dhcom_v &pinctrl_dhcom_w &pinctrl_dhcom_int 134*724ba675SRob Herring >; 135*724ba675SRob Herring pinctrl-names = "default"; 136*724ba675SRob Herring 137*724ba675SRob Herring pinctrl_uart5_core: uart5-core-grp { 138*724ba675SRob Herring fsl,pins = < 139*724ba675SRob Herring MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x1b0b1 140*724ba675SRob Herring MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x1b0b1 141*724ba675SRob Herring >; 142*724ba675SRob Herring }; 143*724ba675SRob Herring}; 144