Home
last modified time | relevance | path

Searched +full:rx +full:- +full:input (Results 1 – 25 of 908) sorted by relevance

12345678910>>...37

/linux/Documentation/devicetree/bindings/net/
H A Dnvidia,tegra234-mgbe.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/nvidia,tegra234-mgbe.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Tegra234 MGBE Multi-Gigabit Ethernet Controller
10 - Thierry Reding <treding@nvidia.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 const: nvidia,tegra234-mgbe
20 reg-names:
22 - const: hypervisor
[all …]
/linux/arch/s390/kernel/
H A Duprobes.c1 // SPDX-License-Identifier: GPL-2.0
3 * User-space Probes (UProbes) for s390
25 return probe_is_prohibited_opcode(auprobe->insn); in arch_uprobe_analyze_insn()
30 if (psw_bits(regs->psw).eaba == PSW_BITS_AMODE_24BIT) in arch_uprobe_pre_xol()
31 return -EINVAL; in arch_uprobe_pre_xol()
32 if (!is_compat_task() && psw_bits(regs->psw).eaba == PSW_BITS_AMODE_31BIT) in arch_uprobe_pre_xol()
33 return -EINVAL; in arch_uprobe_pre_xol()
35 auprobe->saved_per = psw_bits(regs->psw).per; in arch_uprobe_pre_xol()
36 auprobe->saved_int_code = regs->int_code; in arch_uprobe_pre_xol()
37 regs->int_code = UPROBE_TRAP_NR; in arch_uprobe_pre_xol()
[all …]
/linux/drivers/media/rc/
H A Dene_ir.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
11 #define ENE_STATUS 0 /* hardware status - unused */
37 #define ENE_FW2_RXIRQ 0x04 /* RX IRQ pending*/
38 #define ENE_FW2_GP0A 0x08 /* Use GPIO0A for demodulated input */
42 #define ENE_FW2_FAN_INPUT 0x40 /* fan input used for demodulated data*/
45 /* firmware RX pointer for new style buffer */
48 /* high parts of samples for fan input (8 samples)*/
52 #define ENE_FW_SAMPLE_PERIOD_FAN 61 /* fan input has fixed sample period */
66 /* fan as input settings */
80 #define ENE_CIRCFG_RX_EN 0x01 /* RX enable */
[all …]
/linux/arch/m68k/include/asm/
H A Dmcfuart.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * mcfuart.h -- ColdFire internal UART support defines.
7 * (C) Copyright 1999-2003, Greg Ungerer (gerg@snapgear.com)
35 #define MCFUART_UIPCR 0x10 /* Input Port Change (r) */
51 #define MCFUART_UIPR 0x34 /* Input Port (r) */
60 #define MCFUART_MR1_RXIRQFULL 0x40 /* RX IRQ type FULL */
61 #define MCFUART_MR1_RXIRQRDY 0x00 /* RX IRQ type RDY */
62 #define MCFUART_MR1_RXERRBLOCK 0x20 /* RX block error mode */
63 #define MCFUART_MR1_RXERRCHAR 0x00 /* RX char error mode */
107 #define MCFUART_UCSR_RXCLKTIMER 0xd0 /* RX clock is timer */
[all …]
/linux/drivers/gpu/drm/amd/display/modules/hdcp/
H A Dhdcp1_transition.c30 struct mod_hdcp_transition_input_hdcp1 *input, in mod_hdcp_hdcp1_transition() argument
34 struct mod_hdcp_connection *conn = &hdcp->connection; in mod_hdcp_hdcp1_transition()
35 struct mod_hdcp_link_adjustment *adjust = &hdcp->connection.link.adjust; in mod_hdcp_hdcp1_transition()
39 if (input->bksv_read != PASS || input->bcaps_read != PASS) { in mod_hdcp_hdcp1_transition()
40 /* 1A-04: repeatedly attempts on port access failure */ in mod_hdcp_hdcp1_transition()
49 if (input->create_session != PASS) { in mod_hdcp_hdcp1_transition()
51 adjust->hdcp1.disable = 1; in mod_hdcp_hdcp1_transition()
54 } else if (input->an_write != PASS || in mod_hdcp_hdcp1_transition()
55 input->aksv_write != PASS || in mod_hdcp_hdcp1_transition()
56 input->bksv_read != PASS || in mod_hdcp_hdcp1_transition()
[all …]
/linux/drivers/net/wan/
H A Dhd64570.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 /* SCA HD64570 register definitions - all addresses for mode 0 (8086 MPU)
42 /* MSCI channel (port) 0 registers - offset 0x20
43 MSCI channel (port) 1 registers - offset 0x40 */
48 #define TRBL 0x00 /* TX/RX buffer L */
49 #define TRBH 0x01 /* TX/RX buffer H */
68 #define RXS 0x16 /* RX Clock Source */
72 #define RRC 0x1A /* RX Ready Control */
77 /* Timer channel 0 (port 0 RX) registers - offset 0x60
78 Timer channel 1 (port 0 TX) registers - offset 0x68
[all …]
/linux/tools/testing/selftests/drivers/net/hw/
H A Drss_api.py2 # SPDX-License-Identifier: GPL-2.0
19 qcnt = len(glob.glob(f"/sys/class/net/{cfg.ifname}/queues/rx-*"))
29 return int(output.split()[-1])
33 descr = ethtool(f"-n {cfg.ifname} rx-flow-hash {fl_type}").stdout
37 "IP SA": "ip-src",
38 "IP DA": "ip-dst",
39 "L4 bytes 0 & 1 [TCP/UDP src port]": "l4-b-0-1",
40 "L4 bytes 2 & 3 [TCP/UDP dst port]": "l4-b-2-3",
55 for line in descr.split("\n")[1:-2]:
74 ethnl.rss_set({"header": {"dev-name": "lo"},
[all …]
/linux/drivers/staging/media/atomisp/pci/
H A Dsystem_global.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 // SPDX-License-Identifier: GPL-2.0-or-later
15 * - The system is hetereogeneous; Multiple cells and devices classes
16 * - The cell and device instances are homogeneous, each device type
18 * - Device instances supporting a subset of the class capabilities are
25 * N.B. the 3 input formatters are of 2 different classess
40 * the bus for too long; as the input system can only buffer
41 * 2 lines on Moorefield and Cherrytrail, the input system buffers
128 IRQ1_ID, /* Input formatter */
129 IRQ2_ID, /* input system */
[all …]
/linux/drivers/net/ethernet/marvell/octeon_ep_vf/
H A Doctep_vf_config.h1 /* SPDX-License-Identifier: GPL-2.0 */
17 /* Minimum input (Tx) requests to be enqueued to ring doorbell */
25 /* Rx Queue: maximum descriptors per ring */
28 /* Rx buffer size: Use page size buffers.
31 * page buffers in consecutive Rx descriptors as fragments.
51 #define OCTEP_VF_MAX_MTU (10000 - (ETH_HLEN + ETH_FCS_LEN))
56 #define CFG_GET_IQ_CFG(cfg) ((cfg)->iq)
57 #define CFG_GET_IQ_NUM_DESC(cfg) ((cfg)->iq.num_descs)
58 #define CFG_GET_IQ_INSTR_TYPE(cfg) ((cfg)->iq.instr_type)
60 #define CFG_GET_IQ_DB_MIN(cfg) ((cfg)->iq.db_min)
[all …]
/linux/Documentation/netlink/specs/
H A Dovpn.yaml1 # SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause)
5 # Copyright (c) 2024-2025, OpenVPN Inc.
7 ---
15 -
17 name: nonce-tail-size
19 -
21 name: cipher-alg
22 entries: [none, aes-gcm, chacha20-poly1305]
23 -
25 name: del-peer-reason
[all …]
/linux/include/dt-bindings/clock/
H A Dtegra234-clock.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */
58 /** @brief clock recovered from EAVB input */
126 /** @brief clock recovered from I2S1 input */
130 /** @brief clock recovered from I2S2 input */
134 /** @brief clock recovered from I2S3 input */
138 /** @brief clock recovered from I2S4 input */
142 /** @brief clock recovered from I2S5 input */
146 /** @brief clock recovered from I2S6 input */
192 /** @brief input from Tegra's XTAL_IN */
[all …]
/linux/arch/riscv/boot/dts/starfive/
H A Djh7110-pine64-star64.dts1 // SPDX-License-Identifier: GPL-2.0 OR MIT
6 /dts-v1/;
7 #include "jh7110-common.dtsi"
18 starfive,tx-use-rgmii-clk;
19 assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>;
20 assigned-clock-parents = <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>;
25 phy-handle = <&phy1>;
26 phy-mode = "rgmii-id";
27 starfive,tx-use-rgmii-clk;
28 assigned-clocks = <&syscrg JH7110_SYSCLK_GMAC1_TX>;
[all …]
H A Djh7110-milkv-mars.dts1 // SPDX-License-Identifier: GPL-2.0 OR MIT
6 /dts-v1/;
7 #include "jh7110-common.dtsi"
10 model = "Milk-V Mars";
15 assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>;
16 assigned-clock-parents = <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>;
17 starfive,tx-use-rgmii-clk;
34 rx-internal-delay-ps = <1500>;
35 tx-internal-delay-ps = <1500>;
36 motorcomm,rx-clk-drv-microamp = <3970>;
[all …]
/linux/drivers/net/ethernet/marvell/octeon_ep/
H A Doctep_config.h1 /* SPDX-License-Identifier: GPL-2.0 */
18 /* Minimum input (Tx) requests to be enqueued to ring doorbell */
26 /* Rx Queue: maximum descriptors per ring */
29 /* Rx buffer size: Use page size buffers.
32 * page buffers in consecutive Rx descriptors as fragments.
60 #define CFG_GET_IQ_CFG(cfg) ((cfg)->iq)
61 #define CFG_GET_IQ_NUM_DESC(cfg) ((cfg)->iq.num_descs)
62 #define CFG_GET_IQ_INSTR_TYPE(cfg) ((cfg)->iq.instr_type)
64 #define CFG_GET_IQ_DB_MIN(cfg) ((cfg)->iq.db_min)
65 #define CFG_GET_IQ_INTR_THRESHOLD(cfg) ((cfg)->iq.intr_threshold)
[all …]
/linux/arch/x86/crypto/
H A Dcast6-avx-x86_64-asm_64.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Cast6 Cipher 8-way parallel algorithm (AVX/x86_64)
6 * <Johannes.Goetzfried@informatik.stud.uni-erlangen.de>
8 * Copyright © 2012-2013 Jussi Kivilinna <jussi.kivilinna@iki.fi>
13 #include "glue_helper-asm-avx.S"
15 .file "cast6-avx-x86_64-asm_64.S"
26 /* s-boxes */
33 8-way AVX cast6
47 #define RX %xmm8 macro
130 F_head(b1, RX, RGI1, RGI2, op0); \
[all …]
/linux/include/sound/
H A Dak4114.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
13 #define AK4114_REG_IO0 0x02 /* input/output control */
14 #define AK4114_REG_IO1 0x03 /* input/output control */
19 #define AK4114_REG_RXCSB0 0x08 /* RX channel status byte 0 */
20 #define AK4114_REG_RXCSB1 0x09 /* RX channel status byte 1 */
21 #define AK4114_REG_RXCSB2 0x0a /* RX channel status byte 2 */
22 #define AK4114_REG_RXCSB3 0x0b /* RX channel status byte 3 */
23 #define AK4114_REG_RXCSB4 0x0c /* RX channel status byte 4 */
33 #define AK4114_REG_QSUB_ADDR 0x16 /* Q-subcode address + control */
34 #define AK4114_REG_QSUB_TRACK 0x17 /* Q-subcode track */
[all …]
H A Dak4117.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
12 #define AK4117_REG_IO 0x02 /* input/output control */
18 #define AK4117_REG_RXCSB0 0x08 /* RX channel status byte 0 */
19 #define AK4117_REG_RXCSB1 0x09 /* RX channel status byte 1 */
20 #define AK4117_REG_RXCSB2 0x0a /* RX channel status byte 2 */
21 #define AK4117_REG_RXCSB3 0x0b /* RX channel status byte 3 */
22 #define AK4117_REG_RXCSB4 0x0c /* RX channel status byte 4 */
27 #define AK4117_REG_QSUB_ADDR 0x11 /* Q-subcode address + control */
28 #define AK4117_REG_QSUB_TRACK 0x12 /* Q-subcode track */
29 #define AK4117_REG_QSUB_INDEX 0x13 /* Q-subcode index */
[all …]
H A Dak4113.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
16 /* input/output control */
18 /* input/output control */
32 /* RX channel status byte 0 */
34 /* RX channel status byte 1 */
36 /* RX channel status byte 2 */
38 /* RX channel status byte 3 */
40 /* RX channel status byte 4 */
50 /* Q-subcode address + control */
52 /* Q-subcode track */
[all …]
/linux/arch/riscv/boot/dts/thead/
H A Dth1520-lichee-module-4a.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 /dts-v1/;
12 compatible = "sipeed,lichee-module-4a", "thead,th1520";
26 clock-frequency = <24000000>;
30 clock-frequency = <32768>;
34 gpio-line-names = "", "", "",
44 bus-width = <8>;
45 max-frequency = <198000000>;
46 mmc-hs400-1_8v;
47 non-removable;
[all …]
H A Dth1520-beaglev-ahead.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 /dts-v1/;
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/leds/common.h>
15 compatible = "beagle,beaglev-ahead", "thead,th1520";
35 stdout-path = "serial0:115200n8";
44 pinctrl-names = "default";
45 pinctrl-0 = <&led_pins>;
46 compatible = "gpio-leds";
48 led-1 {
[all …]
/linux/drivers/hid/
H A Dhid-wiimote-modules.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright (c) 2011-2013 David Herrmann <dh.herrmann@gmail.com>
19 * re-detection which causes all modules to be unloaded and then reload the
22 * wdata->input is a shared input device. It is always initialized prior to
24 * WIIMOD_FLAG_INPUT, then the input device will get registered after all
27 * called. This guarantees that no input interaction is done, anymore. However,
28 * the wiimote core keeps a reference to the input device so it is freed only
30 * input devices.
35 #include <linux/input.h>
37 #include "hid-wiimote.h"
[all …]
/linux/sound/soc/tegra/
H A Dtegra186_asrc.c1 // SPDX-License-Identifier: GPL-2.0-only
2 // SPDX-FileCopyrightText: Copyright (c) 2022-2025 NVIDIA CORPORATION. All rights reserved.
4 // tegra186_asrc.c - Tegra186 ASRC driver
72 regmap_write(asrc->regmap, in tegra186_asrc_lock_stream()
82 regcache_cache_only(asrc->regmap, true); in tegra186_asrc_runtime_suspend()
83 regcache_mark_dirty(asrc->regmap); in tegra186_asrc_runtime_suspend()
93 regcache_cache_only(asrc->regmap, false); in tegra186_asrc_runtime_resume()
100 regmap_write(asrc->regmap, TEGRA186_ASRC_GLOBAL_SCRATCH_ADDR, in tegra186_asrc_runtime_resume()
101 asrc->soc_data->aram_start_addr); in tegra186_asrc_runtime_resume()
102 regmap_write(asrc->regmap, TEGRA186_ASRC_GLOBAL_ENB, in tegra186_asrc_runtime_resume()
[all …]
/linux/arch/arm/boot/dts/xilinx/
H A Dzynq-zc706.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2011 - 2014 Xilinx
6 /dts-v1/;
7 #include "zynq-7000.dtsi"
11 compatible = "xlnx,zynq-zc706", "xlnx,zynq-7000";
30 stdout-path = "serial0:115200n8";
34 compatible = "usb-nop-xceiv";
35 #phy-cells = <0>;
40 ps-clk-frequency = <33333333>;
45 phy-mode = "rgmii-id";
[all …]
H A Dzynq-zc702.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2011 - 2014 Xilinx
6 /dts-v1/;
7 #include "zynq-7000.dtsi"
8 #include <dt-bindings/gpio/gpio.h>
12 compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000";
31 stdout-path = "serial0:115200n8";
34 gpio-keys {
35 compatible = "gpio-keys";
37 switch-14 {
[all …]
/linux/Documentation/devicetree/bindings/sound/
H A Drockchip,rk3576-sai.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/rockchip,rk3576-sai.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
14 - Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
17 - $ref: dai-common.yaml#
21 const: rockchip,rk3576-sai
33 dma-names:
36 - enum: [tx, rx]
37 - const: rx
[all …]

12345678910>>...37