1099343c6SBo Shen* Atmel SSC driver. 2099343c6SBo Shen 3099343c6SBo ShenRequired properties: 4099343c6SBo Shen- compatible: "atmel,at91rm9200-ssc" or "atmel,at91sam9g45-ssc" 5099343c6SBo Shen - atmel,at91rm9200-ssc: support pdc transfer 6099343c6SBo Shen - atmel,at91sam9g45-ssc: support dma transfer 7099343c6SBo Shen- reg: Should contain SSC registers location and length 8099343c6SBo Shen- interrupts: Should contain SSC interrupt 9725fc136SBoris BREZILLON- clock-names: tuple listing input clock names. 10725fc136SBoris BREZILLON Required elements: "pclk" 11725fc136SBoris BREZILLON- clocks: phandles to input clocks. 12099343c6SBo Shen 13f813175aSRichard Genoud 14f813175aSRichard GenoudRequired properties for devices compatible with "atmel,at91sam9g45-ssc": 15f813175aSRichard Genoud- dmas: DMA specifier, consisting of a phandle to DMA controller node, 16f813175aSRichard Genoud the memory interface and SSC DMA channel ID (for tx and rx). 17f813175aSRichard Genoud See Documentation/devicetree/bindings/dma/atmel-dma.txt for details. 18f813175aSRichard Genoud- dma-names: Must be "tx", "rx". 19f813175aSRichard Genoud 20a69d0009SBo ShenOptional properties: 21a69d0009SBo Shen - atmel,clk-from-rk-pin: bool property. 22a69d0009SBo Shen - When SSC works in slave mode, according to the hardware design, the 23a69d0009SBo Shen clock can get from TK pin, and also can get from RK pin. So, add 24a69d0009SBo Shen this parameter to choose where the clock from. 25a69d0009SBo Shen - By default the clock is from TK pin, if the clock from RK pin, this 26a69d0009SBo Shen property is needed. 27*e8314d7dSPeter Rosin - #sound-dai-cells: Should contain <0>. 28*e8314d7dSPeter Rosin - This property makes the SSC into an automatically registered DAI. 29a69d0009SBo Shen 30f813175aSRichard GenoudExamples: 31f813175aSRichard Genoud- PDC transfer: 32099343c6SBo Shenssc0: ssc@fffbc000 { 33099343c6SBo Shen compatible = "atmel,at91rm9200-ssc"; 34099343c6SBo Shen reg = <0xfffbc000 0x4000>; 35099343c6SBo Shen interrupts = <14 4 5>; 36725fc136SBoris BREZILLON clocks = <&ssc0_clk>; 37725fc136SBoris BREZILLON clock-names = "pclk"; 38099343c6SBo Shen}; 39f813175aSRichard Genoud 40f813175aSRichard Genoud- DMA transfer: 41f813175aSRichard Genoudssc0: ssc@f0010000 { 42f813175aSRichard Genoud compatible = "atmel,at91sam9g45-ssc"; 43f813175aSRichard Genoud reg = <0xf0010000 0x4000>; 44f813175aSRichard Genoud interrupts = <28 4 5>; 45f813175aSRichard Genoud dmas = <&dma0 1 13>, 46f813175aSRichard Genoud <&dma0 1 14>; 47f813175aSRichard Genoud dma-names = "tx", "rx"; 48f813175aSRichard Genoud pinctrl-names = "default"; 49f813175aSRichard Genoud pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; 50f813175aSRichard Genoud}; 51