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/linux/Documentation/devicetree/bindings/spi/
H A Dspi-peripheral-props.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-peripheral-props.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Peripheral-specific properties for a SPI bus.
11 be common properties like spi-max-frequency, spi-cs-high, etc. or they could
12 be controller specific like delay in clock or data lines, etc. These
14 per-peripheral and there can be multiple peripherals attached to a
20 - Mark Brown <broonie@kernel.org>
28 - minimum: 0
[all …]
H A Dsnps,dw-apb-ssi.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/spi/snps,dw-apb-ssi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mark Brown <broonie@kernel.org>
13 - $ref: spi-controller.yaml#
14 - if:
19 - mscc,ocelot-spi
20 - mscc,jaguar2-spi
25 - if:
[all …]
H A Dfsl,dspi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <Frank.Li@nxp.com>
15 - enum:
16 - fsl,vf610-dspi
17 - fsl,ls1021a-v1.0-dspi
18 - fsl,ls1012a-dspi
19 - fsl,ls1028a-dspi
20 - fsl,ls1043a-dspi
[all …]
/linux/drivers/net/ethernet/stmicro/stmmac/
H A Ddwmac-meson8b.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/clk-provider.h>
35 /* TX clock delay in ns = "8ns / 4 * tx_dly_val" (where 8ns are exactly one
37 * 0ns = 0x0, 2ns = 0x1, 4ns = 0x2, 6ns = 0x3
56 * input RX rising/falling edge and sent to the Ethernet internals. This sets
57 * the automatically delay and skew automatically (internally).
60 /* An internal counter based on the "timing-adjustment" clock. The counter is
62 * delay (= the counter value) when to start sampling RXEN and RXD[3:0].
66 * large input delay, the bit for that signal (RXEN = bit 0, RXD[3] = bit 1,
67 * ...) can be configured to be 1 to compensate for a delay of about 1ns.
[all …]
H A Ddwmac-tegra.c1 // SPDX-License-Identifier: GPL-2.0-only
12 "rx-pcs", "tx", "tx-pcs", "mac-divider", "mac", "mgbe", "ptp-ref", "mac"
66 clk_bulk_disable_unprepare(ARRAY_SIZE(mgbe_clks), mgbe->clks); in tegra_mgbe_suspend()
68 return reset_control_assert(mgbe->rst_mac); in tegra_mgbe_suspend()
77 err = clk_bulk_prepare_enable(ARRAY_SIZE(mgbe_clks), mgbe->clks); in tegra_mgbe_resume()
81 err = reset_control_deassert(mgbe->rst_mac); in tegra_mgbe_resume()
86 writel(MAC_SBD_INTR, mgbe->regs + MGBE_WRAP_COMMON_INTR_ENABLE); in tegra_mgbe_resume()
89 writel(mgbe->iommu_sid, mgbe->hv + MGBE_WRAP_AXI_ASID0_CTRL); in tegra_mgbe_resume()
91 value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_STATUS); in tegra_mgbe_resume()
93 value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_HW_INIT_CTRL); in tegra_mgbe_resume()
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-ls1043a-rdb.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Freescale Layerscape-1043A family SoC.
5 * Copyright 2014-2015 Freescale Semiconductor, Inc.
11 /dts-v1/;
12 #include "fsl-ls1043a.dtsi"
16 compatible = "fsl,ls1043a-rdb", "fsl,ls1043a";
26 stdout-path = "serial0:115200n8";
36 shunt-resistor = <1000>;
67 #address-cells = <2>;
68 #size-cells = <1>;
[all …]
/linux/drivers/spi/
H A Dspi-dw-dma.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/dma-mapping.h>
15 #include <linux/platform_data/dma-dw.h>
19 #include "spi-dw.h"
30 if (s->dma_dev != chan->device->dev) in dw_spi_dma_chan_filter()
33 chan->private = s; in dw_spi_dma_chan_filter()
43 def_burst = dws->fifo_len / 2; in dw_spi_dma_maxburst_init()
45 ret = dma_get_slave_caps(dws->rxchan, &caps); in dw_spi_dma_maxburst_init()
51 dws->rxburst = min(max_burst, def_burst); in dw_spi_dma_maxburst_init()
52 dw_writel(dws, DW_SPI_DMARDLR, dws->rxburst - 1); in dw_spi_dma_maxburst_init()
[all …]
H A Dspi-dw-core.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/dma-mapping.h>
15 #include <linux/delay.h>
18 #include <linux/spi/spi-mem.h>
23 #include "spi-dw.h"
32 u32 rx_sample_dly; /* RX sample delay */
66 snprintf(name, 32, "dw_spi%d", dws->host->bus_num); in dw_spi_debugfs_init()
67 dws->debugfs = debugfs_create_dir(name, NULL); in dw_spi_debugfs_init()
69 dws->regset.regs = dw_spi_dbgfs_regs; in dw_spi_debugfs_init()
70 dws->regset.nregs = ARRAY_SIZE(dw_spi_dbgfs_regs); in dw_spi_debugfs_init()
[all …]
H A Dspi-bitbang.c1 // SPDX-License-Identifier: GPL-2.0-or-later
10 #include <linux/delay.h>
22 /*----------------------------------------------------------------------*/
25 * FIRST PART (OPTIONAL): word-at-a-time spi_transfer support.
26 * Use this for GPIO or shift-register level hardware APIs.
28 * spi_bitbang_cs is in spi_device->controller_state, which is unavailable
30 * used, though maybe they're called from controller-aware code.
32 * chipselect() and friends may use spi_device->controller_data and
53 unsigned int ns, in bitbang_txrx_8() argument
58 unsigned int bits = t->bits_per_word; in bitbang_txrx_8()
[all …]
H A Dspi-rockchip.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Author: Addy Ke <addy.ke@rock-chips.com>
18 #define DRIVER_NAME "rockchip-spi"
67 /* ss_n to sclk_out delay */
158 * SPI_CTRLR1 is 16-bits, so we should support lengths of 0xffff + 1. However,
180 void *rx; member
196 bool cs_high_supported; /* native CS supports active-high polarity */
203 writel_relaxed((enable ? 1U : 0U), rs->regs + ROCKCHIP_SPI_SSIENR); in spi_enable_chip()
212 if (!(readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_TARGET_TX_BUSY) && in wait_for_tx_idle()
213 !((readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY))) in wait_for_tx_idle()
[all …]
/linux/arch/arm/boot/dts/ti/omap/
H A Dam335x-nano.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013 Newflow Ltd - https://www.newflow.co.uk/
5 /dts-v1/;
15 cpu0-supply = <&dcdc2_reg>;
25 compatible = "gpio-leds";
30 default-state = "off";
36 pinctrl-names = "default";
37 pinctrl-0 = <&misc_pins>;
39 misc_pins: misc-pins {
40 pinctrl-single,pins = <
[all …]
H A Dam335x-evm.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
5 /dts-v1/;
8 #include <dt-bindings/interrupt-controller/irq.h>
12 compatible = "ti,am335x-evm", "ti,am33xx";
16 cpu0-supply = <&vdd1_reg>;
26 stdout-path = &uart0;
30 compatible = "regulator-fixed";
31 regulator-name = "vbat";
32 regulator-min-microvolt = <5000000>;
[all …]
/linux/arch/arm64/boot/dts/renesas/
H A Dr8a779f0.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Device Tree Source for the R-Car S4-8 (R8A779F0) SoC
8 #include <dt-bindings/clock/r8a779f0-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/r8a779f0-sysc.h>
14 #address-cells = <2>;
15 #size-cells = <2>;
17 cluster01_opp: opp-table-0 {
18 compatible = "operating-points-v2";
19 opp-shared;
[all …]
/linux/arch/riscv/boot/dts/starfive/
H A Djh7100-starfive-visionfive-v1.dts1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include "jh7100-common.dtsi"
12 compatible = "starfive,visionfive-v1", "starfive,jh7100";
14 gpio-restart {
15 compatible = "gpio-restart";
22 phy-handle = <&phy>;
26 * The board uses a Motorcomm YT8521 PHY supporting RGMII-ID, but requires
27 * manual adjustment of the RX internal delay to work properly. The default
28 * RX delay provided by the driver (1.95ns) is too high, but applying a 50%
[all …]
/linux/arch/arm64/boot/dts/amd/
H A Delba-asic-common.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 * Copyright 2020-2022 Advanced Micro Devices, Inc.
7 clock-frequency = <400000000>;
11 clock-frequency = <200000000>;
15 clock-frequency = <400000000>;
19 clock-frequency = <156250000>;
26 compatible = "jedec,spi-nor";
28 spi-max-frequency = <40000000>;
29 spi-rx-bus-width = <2>;
30 m25p,fast-read;
[all …]
/linux/Documentation/devicetree/bindings/net/
H A Dti,dp83867.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - $ref: ethernet-controller.yaml#
14 - Andrew Davis <afd@ti.com>
18 transceiver with integrated PMD sublayers to support 10BASE-Te, 100BASE-TX
19 and 1000BASE-T Ethernet protocols.
34 nvmem-cells:
40 nvmem-cell-names:
42 - const: io_impedance_ctrl
[all …]
/linux/drivers/net/ethernet/microchip/sparx5/
H A Dsparx5_ptp.c1 // SPDX-License-Identifier: GPL-2.0+
7 * https://github.com/microchip-ung/sparx-5_reginfo
30 * (1/1000000)/((2^-59)/X) in sparx5_ptp_get_1ppm()
35 switch (sparx5->coreclock) { in sparx5_ptp_get_1ppm()
60 switch (sparx5->coreclock) { in sparx5_ptp_get_nominal_value()
85 struct sparx5 *sparx5 = port->sparx5; in sparx5_ptp_hwtstamp_set()
93 if (test_bit(port->portno, sparx5->bridge_mask)) in sparx5_ptp_hwtstamp_set()
94 return -EINVAL; in sparx5_ptp_hwtstamp_set()
96 switch (cfg->tx_type) { in sparx5_ptp_hwtstamp_set()
98 port->ptp_cmd = IFH_REW_OP_TWO_STEP_PTP; in sparx5_ptp_hwtstamp_set()
[all …]
/linux/arch/arm/boot/dts/renesas/
H A Dr8a7792.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Car V2H (R8A77920) SoC
8 #include <dt-bindings/clock/r8a7792-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/power/r8a7792-sysc.h>
15 #address-cells = <2>;
16 #size-cells = <2>;
39 compatible = "fixed-clock";
40 #clock-cells = <0>;
[all …]
H A Dr8a7793.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Car M2-N (R8A77930) SoC
5 * Copyright (C) 2014-2015 Renesas Electronics Corporation
8 #include <dt-bindings/clock/r8a7793-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/power/r8a7793-sysc.h>
15 #address-cells = <2>;
16 #size-cells = <2>;
37 compatible = "fixed-clock";
[all …]
H A Dr8a7794.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Car E2 (R8A77940) SoC
9 #include <dt-bindings/clock/r8a7794-cpg-mssr.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/power/r8a7794-sysc.h>
16 #address-cells = <2>;
17 #size-cells = <2>;
39 compatible = "fixed-clock";
40 #clock-cells = <0>;
[all …]
H A Dr8a77470.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/r8a77470-cpg-mssr.h>
11 #include <dt-bindings/power/r8a77470-sysc.h>
14 #address-cells = <2>;
15 #size-cells = <2>;
26 #address-cells = <1>;
27 #size-cells = <0>;
31 compatible = "arm,cortex-a7";
[all …]
/linux/Documentation/devicetree/bindings/i2c/
H A Drenesas,rcar-i2c.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/i2c/renesas,rcar-i2c.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car I2C Controller
10 - Wolfram Sang <wsa+renesas@sang-engineering.com>
15 - items:
16 - enum:
17 - renesas,i2c-r8a7778 # R-Car M1A
18 - renesas,i2c-r8a7779 # R-Car H1
[all …]
/linux/drivers/iio/resolver/
H A Dad2s1200.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright (c) 2018-2018 David Veenstra <davidjulianveenstra@gmail.com>
7 * Copyright (c) 2010-2010 Analog Devices Inc.
11 #include <linux/delay.h>
31 * struct ad2s1200_state - driver instance specific data.
32 * @lock: protects both the GPIO pins and the rx buffer.
36 * @rx: buffer for spi transfers.
43 __be16 rx __aligned(IIO_DMA_MINALIGN);
57 switch (chan->type) { in ad2s1200_read_raw()
59 /* 2 * Pi / (2^12 - 1) ~= 0.001534355 */ in ad2s1200_read_raw()
[all …]
/linux/arch/arm64/boot/dts/microchip/
H A Dsparx5_nand.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 cs14_pins: cs14-pins {
14 pinctrl-0 = <&si2_pins>;
15 pinctrl-names = "default";
17 compatible = "spi-mux";
18 mux-controls = <&mux>;
19 #address-cells = <1>;
20 #size-cells = <0>;
23 compatible = "spi-nand";
24 pinctrl-0 = <&cs14_pins>;
[all …]
/linux/arch/arm/boot/dts/st/
H A Dstm32mp157c-phycore-stm32mp15-som.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) 2022-2023 Steffen Trumtrar <kernel@pengutronix.de>
4 * Copyright (C) Phytec GmbH 2019-2020 - All Rights Reserved
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/leds/common.h>
13 #include <dt-bindings/leds/leds-pca9532.h>
14 #include <dt-bindings/mfd/st,stpmic1.h>
[all …]

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