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/linux/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/
H A Ducc.txt4 - device_type : should be "network", "hldc", "uart", "transparent"
6 - compatible : could be "ucc_geth" or "fsl_atm" and so on.
7 - cell-index : the ucc number(1-8), corresponding to UCCx in UM.
8 - reg : Offset and length of the register set for the device
9 - interrupts : <a b> where a is the interrupt number and b is a
14 - pio-handle : The phandle for the Parallel I/O port configuration.
15 - port-number : for UART drivers, the port number to use, between 0 and 3.
18 CPM UART driver, the port-number is required for the QE UART driver.
19 - soft-uart : for UART drivers, if specified this means the QE UART device
20 driver should use "Soft-UART" mode, which is needed on some SOCs that have
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/linux/Documentation/devicetree/bindings/soc/fsl/cpm_qe/
H A Dfsl,ucc-hdlc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,ucc-hdlc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: High-Level Data Link Control(HDLC)
12 - Frank Li <Frank.Li@nxp.com>
16 const: fsl,ucc-hdlc
24 cell-index:
27 rx-clock-name:
30 - pattern: "^brg([0-9]|1[0-6])$"
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H A Duqe_serial.txt4 compatible : must be "fsl,<chip>-ucc-uart". For t1040, must be
5 "fsl,t1040-ucc-uart".
6 port-number : port number of UCC-UART
7 tx/rx-clock-name : should be "brg1"-"brg16" for internal clock source,
8 should be "clk1"-"clk28" for external clock source.
13 compatible = "fsl,t1040-ucc-uart";
14 port-number = <0>;
15 rx-clock-name = "brg2";
16 tx-clock-name = "brg2";
/linux/Documentation/devicetree/bindings/net/
H A Dsnps,dwc-qos-ethernet.txt13 - compatible: One of:
14 - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10"
15 Represents the IP core when integrated into the Axis ARTPEC-6 SoC.
16 - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10"
18 - "snps,dwc-qos-ethernet-4.10"
20 "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10". It is supported to be
22 - reg: Address and length of the register set for the device
23 - clocks: Phandle and clock specifiers for each entry in clock-names, in the
24 same order. See ../clock/clock-bindings.txt.
25 - clock-names: May contain any/all of the following depending on the IP
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H A Dkeystone-netcp.txt6 switch sub-module to send and receive packets. NetCP also includes a packet
13 includes a 3-port Ethernet switch sub-module capable of 10Gb/s and 1Gb/s rates
16 Keystone NetCP driver has a plug-in module architecture where each of the NetCP
17 sub-modules exist as a loadable kernel module which plug in to the netcp core.
18 These sub-modules are represented as "netcp-devices" in the dts bindings. It is
19 mandatory to have the ethernet switch sub-module for the ethernet interface to
20 be operational. Any other sub-module like the PA is optional.
24 -----------------------------
26 -----------------------------
28 |-> NetCP Devices -> |
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/linux/sound/soc/intel/boards/
H A Dcht_bsw_rt5645.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * cht-bsw-rt5645.c - ASoc Machine driver for Intel Cherryview-based platforms
25 #include <sound/soc-acpi.h>
27 #include "../atom/sst-atom-controls.h"
28 #include "../common/soc-intel-quirks.h"
31 #define CHT_CODEC_DAI1 "rt5645-aif1"
32 #define CHT_CODEC_DAI2 "rt5645-aif2"
69 struct snd_soc_dapm_context *dapm = w->dapm; in platform_clock_control()
70 struct snd_soc_card *card = dapm->card; in platform_clock_control()
80 dev_err(card->dev, "Codec dai not found; Unable to set platform clock\n"); in platform_clock_control()
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H A Dcht_bsw_rt5672.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * cht_bsw_rt5672.c - ASoc Machine driver for Intel Cherryview-based platforms
21 #include <sound/soc-acpi.h>
23 #include "../atom/sst-atom-controls.h"
24 #include "../common/soc-intel-quirks.h"
27 /* The platform clock #3 outputs 19.2Mhz clock to codec as I2S MCLK */
29 #define CHT_CODEC_DAI "rt5670-aif1"
53 struct snd_soc_dapm_context *dapm = w->dapm; in platform_clock_control()
54 struct snd_soc_card *card = dapm->card; in platform_clock_control()
61 dev_err(card->dev, "Codec dai not found; Unable to set platform clock\n"); in platform_clock_control()
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H A Dbytcr_rt5651.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * bytcr_rt5651.c - ASoc Machine driver for Intel Byt CR platform
29 #include <sound/soc-acpi.h>
31 #include "../atom/sst-atom-controls.h"
32 #include "../common/soc-intel-quirks.h"
80 /* jack-detect-source + inv + dmic-en + ovcd-th + -sf + terminating entry */
93 /* Default: jack-detect on JD1_1, internal mic on in2, headsetmic on in3 */
97 static int quirk_override = -1;
99 MODULE_PARM_DESC(quirk, "Board-specific quirk override");
112 dev_info(dev, "quirk realtek,jack-detect-source %ld\n", in log_quirks()
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/linux/Documentation/devicetree/bindings/sound/
H A Ddavinci-mcasp-audio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/davinci-mcasp-audio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jayesh Choudhary <j-choudhary@ti.com>
15 - ti,dm646x-mcasp-audio
16 - ti,da830-mcasp-audio
17 - ti,am33xx-mcasp-audio
18 - ti,dra7-mcasp-audio
19 - ti,omap4-mcasp-audio
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H A Dallwinner,sun4i-a10-i2s.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/allwinner,sun4i-a10-i2s.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 "#sound-dai-cells":
19 - const: allwinner,sun4i-a10-i2s
20 - const: allwinner,sun6i-a31-i2s
21 - const: allwinner,sun8i-a83t-i2s
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/linux/Documentation/devicetree/bindings/crypto/
H A Domap-des.txt5 - compatible : Should contain "ti,omap4-des"
6 - ti,hwmods: Name of the hwmod associated with the DES module
7 - reg : Offset and length of the register set for the module
8 - interrupts : the interrupt-specifier for the DES module
9 - clocks : A phandle to the functional clock node of the DES module
10 corresponding to each entry in clock-names
11 - clock-names : Name of the functional clock, should be "fck"
14 - dmas: DMA specifiers for tx and rx dma. See the DMA client binding,
16 Each entry corresponds to an entry in dma-names
17 - dma-names: DMA request names should include "tx" and "rx" if present
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/linux/drivers/clk/tegra/
H A Dclk-bpmp.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2016-2022 NVIDIA Corporation
6 #include <linux/clk-provider.h>
12 #include <soc/tegra/bpmp-abi.h>
22 char name[MRQ_CLK_NAME_MAXLEN]; member
56 } rx; member
68 request.cmd_and_id = (clk->cmd << 24) | clk->id; in tegra_bpmp_clk_transfer()
72 * that contains all possible sub-command structures. Copy the data in tegra_bpmp_clk_transfer()
73 * to that union. Ideally we'd be able to refer to it by name, but in tegra_bpmp_clk_transfer()
77 memcpy(req + 4, clk->tx.data, clk->tx.size); in tegra_bpmp_clk_transfer()
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/linux/Documentation/devicetree/bindings/hsi/
H A Domap-ssi.txt9 - compatible: Should include "ti,omap3-ssi" or "ti,omap4-hsi"
10 - reg-names: Contains the values "sys" and "gdd" (in this order).
11 - reg: Contains a matching register specifier for each entry
12 in reg-names.
13 - interrupt-names: Contains the value "gdd_mpu".
14 - interrupts: Contains matching interrupt information for each entry
15 in interrupt-names.
16 - ranges: Represents the bus address mapping between the main
18 - clock-names: Must include the following entries:
19 "ssi_ssr_fck": The OMAP clock of that name
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/linux/arch/powerpc/boot/dts/
H A Dmpc836x_rdk.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Copyright 2007-2008 MontaVista Software, Inc.
11 /dts-v1/;
14 #address-cells = <1>;
15 #size-cells = <1>;
31 #address-cells = <1>;
32 #size-cells = <0>;
37 d-cache-line-size = <32>;
38 i-cache-line-size = <32>;
39 d-cache-size = <32768>;
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H A Dkmeter1.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * 2008-2011 DENX Software Engineering GmbH
8 /dts-v1/;
13 #address-cells = <1>;
14 #size-cells = <1>;
28 #address-cells = <1>;
29 #size-cells = <0>;
34 d-cache-line-size = <32>; // 32 bytes
35 i-cache-line-size = <32>; // 32 bytes
36 d-cache-size = <32768>; // L1, 32K
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/linux/arch/arm64/boot/dts/amlogic/
H A Dmeson-gxbb-nanopi-k2.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include "meson-gxbb.dtsi"
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/sound/meson-aiu.h>
13 compatible = "friendlyarm,nanopi-k2", "amlogic,meson-gxbb";
22 stdout-path = "serial0:115200n8";
31 compatible = "gpio-leds";
33 led-stat {
34 label = "nanopi-k2:blue:stat";
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/linux/arch/powerpc/boot/dts/fsl/
H A Dmpc8569mds.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
8 /include/ "mpc8569si-pre.dtsi"
13 #address-cells = <2>;
14 #size-cells = <2>;
15 interrupt-parent = <&mpic>;
40 #address-cells = <1>;
41 #size-cells = <1>;
42 compatible = "cfi-flash";
44 bank-width = <1>;
45 device-width = <1>;
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H A Dt104xd4rdb.dtsi13 * * Neither the name of Freescale Semiconductor nor the
36 reserved-memory {
37 #address-cells = <2>;
38 #size-cells = <2>;
41 bman_fbpr: bman-fbpr {
45 qman_fqd: qman-fqd {
49 qman_pfdr: qman-pfdr {
62 #address-cells = <1>;
63 #size-cells = <1>;
64 compatible = "cfi-flash";
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H A Dt104xrdb.dtsi4 * Copyright 2014 - 2015 Freescale Semiconductor Inc.
13 * * Neither the name of Freescale Semiconductor nor the
42 reserved-memory {
43 #address-cells = <2>;
44 #size-cells = <2>;
47 bman_fbpr: bman-fbpr {
51 qman_fqd: qman-fqd {
55 qman_pfdr: qman-pfdr {
68 #address-cells = <1>;
69 #size-cells = <1>;
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H A Dp1025twr.dtsi2 * P1025 TWR Device Tree Source stub (no addresses or top-level ranges)
13 * * Neither the name of Freescale Semiconductor nor the
44 #address-cells = <1>;
45 #size-cells = <1>;
46 compatible = "cfi-flash";
48 bank-width = <2>;
49 device-width = <1>;
55 label = "NOR Vitesse-7385 Firmware";
56 read-only;
82 read-only;
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/linux/sound/soc/fsl/
H A Dfsl_spdif.c1 // SPDX-License-Identifier: GPL-2.0
25 #include "imx-pcm.h"
45 #define RX_SAMPLE_RATE_KCONTROL "RX Sample Rate"
51 * @shared_root_clock: flag of sharing a clock source with others;
52 * so the driver shouldn't set root clock rate
57 * @rx_burst: rx maxburst size
97 * struct fsl_spdif_priv - Freescale SPDIF private data
102 * @rxrate_kcontrol: kcontrol for RX Sample Rate
111 * @txclk: tx clock sources for playback
112 * @rxclk: rx clock sources for capture
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H A Dfsl_ssi.c1 // SPDX-License-Identifier: GPL-2.0
7 // Copyright 2007-2010 Freescale Semiconductor, Inc.
9 // Some notes why imx-pcm-fiq is used instead of DMA on some boards:
16 // we receive in our (PCM-) data stream. The only chance we have is to
43 #include <linux/dma/imx-dma.h>
53 #include "imx-pcm.h"
55 /* Define RX and TX to index ssi->regvals array; Can be 0 or 1 only */
56 #define RX 0 macro
66 * (bit-endianness must match byte-endianness). Processors typically write
68 * written in. So if the host CPU is big-endian, then only big-endian
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/linux/Documentation/devicetree/bindings/mmc/
H A Dti-omap-hsmmc.txt10 --------------------
11 - compatible:
12 Should be "ti,omap2-hsmmc", for OMAP2 controllers
13 Should be "ti,omap3-hsmmc", for OMAP3 controllers
14 Should be "ti,omap3-pre-es3-hsmmc" for OMAP3 controllers pre ES3.0
15 Should be "ti,omap4-hsmmc", for OMAP4 controllers
16 Should be "ti,am33xx-hsmmc", for AM335x controllers
17 Should be "ti,k2g-hsmmc", "ti,omap4-hsmmc" for 66AK2G controllers.
20 ---------------------------------
22 - ti,hwmods: Must be "mmc<n>", n is controller instance starting 1.
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/linux/drivers/net/ethernet/intel/i40e/
H A Di40e_ptp.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2013 - 2018 Intel Corporation. */
5 #include <linux/posix-clock.h>
10 * the fundamental clock design. However, the clock operations are much simpler
39 CANT_DO_PINS = -1,
45 /* name idx func chan */
52 end = -2,
66 led_end = -2,
145 * i40e_ptp_extts0_work - workqueue task function
148 * Service for PTP external clock event
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/linux/drivers/spi/
H A Dspi-meson-spicc.c7 * SPDX-License-Identifier: GPL-2.0+
12 #include <linux/clk-provider.h>
30 * - all transfers are cutted in 16 words burst because the FIFO hangs on
31 * TX underflow, and there is no TX "Half-Empty" interrupt, so we go by
33 * - CS management is dumb, and goes UP between every burst, so is really a
69 #define SPICC_TH_EN BIT(1) /* TX FIFO Half-Full Interrupt */
71 #define SPICC_RR_EN BIT(3) /* RX FIFO Ready Interrupt */
72 #define SPICC_RH_EN BIT(4) /* RX FIFO Half-Full Interrupt */
73 #define SPICC_RF_EN BIT(5) /* RX FIFO Full Interrupt */
74 #define SPICC_RO_EN BIT(6) /* RX FIFO Overflow Interrupt */
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