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/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6qdl-dhcom-drc02.dtsi1 // SPDX-License-Identifier: GPL-2.0+
8 stdout-path = "serial0:115200n8";
15 * Tx and Rx are routed to the DHCOM UART1 rts/cts pins. Therefore the micro SD
16 * card must be disabled and the uart1 rts/cts must be output on other DHCOM
30 rs485-rx-en-hog {
31 gpio-hog;
32 gpios = <18 0>; /* GPIO Q */
33 line-name = "rs485-rx-en";
34 output-low;
39 gpio-line-names =
[all …]
H A Dimx6ull-dhcom-drc02.dts1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
6 * DHCM-iMX6ULL-C080-R051-F0409-SPI-E2-CAN2-SD-RTC-ADC-I-01D2
7 * DHCOR PCB number: 578-200 or newer
8 * DHCOM PCB number: 579-200 or newer
9 * DRC02 PCB number: 568-100 or newer (2nd ethernet by SoM)
11 /dts-v1/;
13 #include "imx6ull-dhcom-som.dtsi"
14 #include "imx6ull-dhcom-som-cfg-sdcard.dtsi"
18 compatible = "dh,imx6ull-dhcom-drc02", "dh,imx6ull-dhcom-som",
19 "dh,imx6ull-dhcor-som", "fsl,imx6ull";
[all …]
H A Dimx6ul-ccimx6ulsbcpro.dts1 // SPDX-License-Identifier: GPL-2.0
9 /dts-v1/;
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
13 #include "imx6ul-ccimx6ulsom.dtsi"
20 compatible = "pwm-backlight";
22 brightness-levels = <0 4 8 16 32 64 128 255>;
23 default-brightness-level = <6>;
29 power-supply = <&ldo4_ext>;
34 remote-endpoint = <&display_out>;
[all …]
/linux/Documentation/devicetree/bindings/leds/
H A Drichtek,rt8515.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
16 RFS and RTS.
22 enf-gpios:
26 ent-gpios:
30 richtek,rfs-ohms:
35 for the property flash-max-microamp to work, the RFS resistor
39 richtek,rts-ohms:
[all …]
/linux/Documentation/devicetree/bindings/serial/
H A Dserial.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
11 - Greg Kroah-Hartman <gregkh@linuxfoundation.org>
19 where N is the port number (non-negative decimal integer) as printed on the
28 cts-gpios:
34 dcd-gpios:
40 dsr-gpios:
46 dtr-gpios:
[all …]
H A Dst,stm32-uart.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/serial/st,stm32-uart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 - Erwan Le Ray <erwan.leray@foss.st.com>
15 - st,stm32-uart
16 - st,stm32f7-uart
17 - st,stm32h7-uart
34 st,hw-flow-ctrl:
38 rx-tx-swap: true
[all …]
H A Drs485.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
9 description: The RTS signal is capable of automatically controlling line
10 direction for the built-in half-duplex mode. The properties described
11 hereafter shall be given to a half-duplex capable UART node.
14 - Rob Herring <robh@kernel.org>
17 rs485-rts-delay:
18 description: prop-encoded-array <a b>
19 $ref: /schemas/types.yaml#/definitions/uint32-array
[all …]
H A D8250.yaml3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - devicetree@vger.kernel.org
13 - $ref: serial.yaml#
14 - $ref: /schemas/memory-controllers/mc-peripheral-props.yaml#
15 - if:
17 - required:
18 - aspeed,lpc-io-reg
19 - required:
20 - aspeed,lpc-interrupts
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mm-venice-gw72xx-0x-rs232-rts.dtso1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * GW72xx RS232 with RTS/CTS hardware flow control:
6 * - GPIO4_0 rs485_en needs to be driven low (in-active)
7 * - UART4_TX becomes RTS
8 * - UART4_RX becomes CTS
11 #include <dt-bindings/gpio/gpio.h>
13 #include "imx8mm-pinfunc.h"
15 /dts-v1/;
19 rs485-en-hog {
20 gpio-hog;
[all …]
H A Dimx8mm-venice-gw73xx-0x-rs232-rts.dtso1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * GW73xx RS232 with RTS/CTS hardware flow control:
6 * - GPIO4_0 rs485_en needs to be driven low (in-active)
7 * - UART4_TX becomes RTS
8 * - UART4_RX becomes CTS
11 #include <dt-bindings/gpio/gpio.h>
13 #include "imx8mm-pinfunc.h"
15 /dts-v1/;
19 rs485-en-hog {
20 gpio-hog;
[all …]
H A Dimx8mm-venice-gw7902.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/linux-event-codes.h>
10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/net/ti-dp83867.h>
12 #include <dt-bindings/phy/phy-imx8-pcie.h>
18 compatible = "gw,imx8mm-gw7902", "fsl,imx8mm";
29 stdout-path = &uart2;
38 compatible = "fixed-clock";
[all …]
H A Dimx8mn-rve-gateway.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/usb/pd.h>
9 #include "imx8mn-var-som.dtsi"
13 compatible = "rve,gateway", "variscite,var-som-mx8mn", "fsl,imx8mn";
15 crystal_duart_24m: crystal-duart-24m {
16 compatible = "fixed-clock";
17 #clock-cells = <0>;
18 clock-frequency = <24000000>;
21 gpio-keys {
[all …]
/linux/Documentation/devicetree/bindings/net/
H A Dintel,ixp4xx-hss.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/net/intel,ixp4xx-hss.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Linus Walleij <linus.walleij@linaro.org>
20 const: intel,ixp4xx-hss
26 intel,npe-handle:
27 $ref: /schemas/types.yaml#/definitions/phandle-array
30 - description: phandle to the NPE this HSS instance is using
31 - description: the NPE instance number
[all …]
/linux/arch/arm/boot/dts/microchip/
H A Daks-cdu.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * aks-cdu.dts - Device Tree file for AK signal CDU
9 /dts-v1/;
11 #include "ge863-pro3.dtsi"
20 clock-frequency = <32768>;
32 linux,rs485-enabled-at-boot-time;
33 rs485-rts-delay = <0 0>;
38 linux,rs485-enabled-at-boot-time;
39 rs485-rts-delay = <0 0>;
44 linux,rs485-enabled-at-boot-time;
[all …]
/linux/arch/arm/boot/dts/st/
H A Dstm32mp157a-iot-box.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
7 #include "stm32mp157a-stinger96.dtsi"
11 compatible = "shiratech,stm32mp157a-iot-box", "st,stm32mp157";
13 wlan_pwr: regulator-wlan {
14 compatible = "regulator-fixed";
16 regulator-name = "wl-reg";
17 regulator-min-microvolt = <3300000>;
18 regulator-max-microvolt = <3300000>;
20 gpios = <&gpiog 3 GPIO_ACTIVE_HIGH>;
[all …]
H A Dstm32mp153c-lxa-fairytux2-gen1.dts1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
6 /dts-v1/;
8 #include "stm32mp153c-lxa-fairytux2.dtsi"
12 compatible = "lxa,stm32mp153c-fairytux2-gen1", "oct,stm32mp153x-osd32", "st,stm32mp153";
14 gpio-keys {
15 compatible = "gpio-keys";
17 button-left {
20 gpios = <&gpioi 11 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
23 button-right {
26 gpios = <&gpioe 9 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
[all …]
/linux/arch/arm64/boot/dts/rockchip/
H A Dpx30-ringneck-haikou.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
7 #include "px30-ringneck.dtsi"
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/leds/common.h>
12 model = "Theobroma Systems PX30-uQ7 SoM on Haikou devkit";
13 compatible = "tsd,px30-ringneck-haikou", "rockchip,px30";
21 stdout-path = "serial0:115200n8";
24 gpio-keys {
25 compatible = "gpio-keys";
[all …]
/linux/Documentation/devicetree/bindings/pinctrl/
H A Dmarvell,dove-pinctrl.txt3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,dove-pinctrl"
8 - clocks: (optional) phandle of pdma clock
9 - reg: register specifiers of MPP, MPP4, and PMU MPP registers
18 mpp0 0 gpio, pmu, uart2(rts), sdio0(cd), lcd0(pwm), pmu*
21 uart1(rts), pmu*
23 uart1(cts), lcd-spi(cs1), pmu*
24 mpp4 4 gpio, pmu, uart3(rts), sdio1(cd), spi1(miso), pmu*
31 mpp11 11 gpio, pmu, sata(prsnt), sata-1(act), sdio0(ledctrl),
33 mpp12 12 gpio, pmu, uart2(rts), audio0(extclk), sdio1(cd),
[all …]
/linux/arch/arm/boot/dts/ti/omap/
H A Dam335x-netcom-plus-2xx.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
11 /dts-v1/;
13 #include "am335x-baltos.dtsi"
14 #include "am335x-baltos-leds.dtsi"
21 uart1_pins: uart1-pins {
22 pinctrl-single,pins = <
26 AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) /* RTS */
34 uart2_pins: uart2-pins {
35 pinctrl-single,pins = <
[all …]
H A Dam335x-nano.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013 Newflow Ltd - https://www.newflow.co.uk/
5 /dts-v1/;
15 cpu0-supply = <&dcdc2_reg>;
25 compatible = "gpio-leds";
29 gpios = <&gpio1 5 0>;
30 default-state = "off";
36 pinctrl-names = "default";
37 pinctrl-0 = <&misc_pins>;
39 misc_pins: misc-pins {
[all …]
H A Dam335x-regor.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/pinctrl/am33xx.h>
12 model = "Phytec AM335x phyBOARD-REGOR";
13 compatible = "phytec,am335x-regor", "phytec,am335x-phycore-som", "ti,am33xx";
16 compatible = "regulator-fixed";
17 regulator-name = "vcc3v3";
18 regulator-min-microvolt = <3300000>;
19 regulator-max-microvolt = <3300000>;
20 regulator-boot-on;
[all …]
/linux/arch/arm64/boot/dts/allwinner/
H A Dsun50i-a64-orangepi-win.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 // Copyright (C) 2017-2018 Samuel Holland <samuel@sholland.org>
5 /dts-v1/;
7 #include "sun50i-a64.dtsi"
8 #include "sun50i-a64-cpu-opp.dtsi"
10 #include <dt-bindings/gpio/gpio.h>
14 compatible = "xunlong,orangepi-win", "allwinner,sun50i-a64";
26 stdout-path = "serial0:115200n8";
29 hdmi-connector {
30 compatible = "hdmi-connector";
[all …]
/linux/arch/arm/boot/dts/intel/ixp/
H A Dintel-ixp42x-goramo-multilink.dts1 // SPDX-License-Identifier: ISC
5 * - MultiLink Basic (a box)
6 * - MultiLink Max (19" rack mount)
9 * This is one of the few devices supporting the IXP4xx High-Speed Serial
14 /dts-v1/;
16 #include "intel-ixp42x.dtsi"
17 #include <dt-bindings/input/input.h>
21 compatible = "goramo,multilink-router", "intel,ixp42x";
22 #address-cells = <1>;
23 #size-cells = <1>;
[all …]
/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8192-asurada-hayato-r1.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 /dts-v1/;
6 #include "mt8192-asurada.dtsi"
10 chassis-type = "convertible";
11 compatible = "google,hayato-rev1", "google,hayato", "mediatek,mt8192";
15 function-row-physmap = <
44 bt_pins: bt-pins {
45 pins-bt-kill {
47 output-low;
50 pins-bt-wake {
[all …]
/linux/Documentation/devicetree/bindings/soc/fsl/cpm_qe/
H A Dserial.txt4 - fsl,cpm1-smc-uart
5 - fsl,cpm2-smc-uart
6 - fsl,cpm1-scc-uart
7 - fsl,cpm2-scc-uart
8 - fsl,qe-uart
10 Modem control lines connected to GPIO controllers are listed in the gpios
11 property as described in booting-without-of.txt, section IX.1 in the following
14 CTS, RTS, DCD, DSR, DTR, and RI.
16 The gpios property is optional and can be left out when control lines are
23 compatible = "fsl,mpc8272-scc-uart",
[all …]

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