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/linux/drivers/mmc/host/
H A Dsdhci_f_sdh30.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2013 - 2015 Fujitsu Semiconductor, Ltd
20 #include "sdhci-pltfm.h"
26 struct reset_control *rst; member
42 u32 ctrl = 0; in sdhci_f_sdh30_soft_voltage_switch() local
45 ctrl = sdhci_readl(host, F_SDH30_IO_CONTROL2); in sdhci_f_sdh30_soft_voltage_switch()
46 ctrl |= F_SDH30_CRES_O_DN; in sdhci_f_sdh30_soft_voltage_switch()
47 sdhci_writel(host, ctrl, F_SDH30_IO_CONTROL2); in sdhci_f_sdh30_soft_voltage_switch()
48 ctrl |= F_SDH30_MSEL_O_1_8; in sdhci_f_sdh30_soft_voltage_switch()
49 sdhci_writel(host, ctrl, F_SDH30_IO_CONTROL2); in sdhci_f_sdh30_soft_voltage_switch()
[all …]
H A Dsdhci-of-ma35d1.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Author: Shan-Chun Hung <shanchun1218@gmail.com>
16 #include <linux/dma-mapping.h>
32 #include "sdhci-pltfm.h"
45 struct reset_control *rst; member
77 if (likely(!len || (ALIGN(addr, SZ_128M) == ALIGN(addr + len - 1, SZ_128M)))) { in ma35_adma_write_desc()
82 offset = addr & (SZ_128M - 1); in ma35_adma_write_desc()
83 tmplen = SZ_128M - offset; in ma35_adma_write_desc()
87 len -= tmplen; in ma35_adma_write_desc()
115 switch (ios->signal_voltage) { in ma35_start_signal_voltage_switch()
[all …]
/linux/drivers/pwm/
H A Dpwm-sun4i.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2014 Alexandre Belloni <alexandre.belloni@free-electrons.com>
8 * - When outputing the source clock directly, the PWM logic will be bypassed
46 #define PWM_PRD(prd) (((prd) - 1) << 16)
85 struct reset_control *rst; member
98 return readl(sun4ichip->base + offset); in sun4i_pwm_readl()
104 writel(val, sun4ichip->base + offset); in sun4i_pwm_writel()
116 clk_rate = clk_get_rate(sun4ichip->clk); in sun4i_pwm_get_state()
118 return -EINVAL; in sun4i_pwm_get_state()
127 if ((val & BIT_CH(PWM_BYPASS, pwm->hwpwm)) && in sun4i_pwm_get_state()
[all …]
/linux/drivers/iio/adc/
H A Dsun20i-gpadc-iio.c1 // SPDX-License-Identifier: GPL-2.0
3 * GPADC driver for sunxi platforms (D1, T113-S3 and R329)
18 #include <linux/iio/adc-helpers.h>
21 #define SUN20I_GPADC_DRIVER_NAME "sun20i-gpadc"
66 u32 ctrl; in sun20i_gpadc_adc_read() local
69 mutex_lock(&info->lock); in sun20i_gpadc_adc_read()
71 reinit_completion(&info->completion); in sun20i_gpadc_adc_read()
73 if (info->last_channel != chan->channel) { in sun20i_gpadc_adc_read()
74 info->last_channel = chan->channel; in sun20i_gpadc_adc_read()
77 writel(SUN20I_GPADC_CS_EN_ADC_CH(chan->channel), in sun20i_gpadc_adc_read()
[all …]
/linux/Documentation/devicetree/bindings/phy/
H A Dbrcm,ns2-drd-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/brcm,ns2-drd-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Florian Fainelli <florian.fainelli@broadcom.com>
11 - Hauke Mehrtens <hauke@hauke-m.de>
12 - Rafał Miłecki <zajec5@gmail.com>
16 const: brcm,ns2-drd-phy
20 - description: DRD ICFG configurations
21 - description: DRD IDM reset
[all …]
/linux/drivers/mtd/nand/raw/
H A Dtegra_nand.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (C) 2014-2015 Lucas Stach <dev@lynxeye.de>
10 #include <linux/dma-mapping.h>
34 #define COMMAND_TRANS_SIZE(size) ((((size) - 1) & 0xf) << 20)
40 #define COMMAND_CLE_SIZE(size) ((((size) - 1) & 0x3) << 4)
41 #define COMMAND_ALE_SIZE(size) ((((size) - 1) & 0xf) << 0)
156 #define OFFSET(val, off) ((val) < (off) ? 0 : (val) - (off))
207 int bytes_per_step = DIV_ROUND_UP(BITS_PER_STEP_RS * chip->ecc.strength, in tegra_nand_ooblayout_rs_ecc()
211 return -ERANGE; in tegra_nand_ooblayout_rs_ecc()
213 oobregion->offset = SKIP_SPARE_BYTES; in tegra_nand_ooblayout_rs_ecc()
[all …]
/linux/include/linux/platform_data/
H A Dmax197.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (c) 2012 Savoir-faire Linux Inc.
8 * For further information, see the Documentation/hwmon/max197.rst file.
15 * struct max197_platform_data - MAX197 connectivity info
16 * @convert: Function used to start a conversion with control byte ctrl.
20 int (*convert)(u8 ctrl);
/linux/drivers/char/hw_random/
H A Djh7110-trng.c1 // SPDX-License-Identifier: GPL-2.0
42 /* CTRL CMD */
100 struct reset_control *rst; member
107 /* protects against concurrent write to ctrl register */
113 MODULE_PARM_DESC(autoreq, "Auto-reseeding after random number requests by host reaches specified co…
114 " 0 - disable counter\n"
115 " other - reload value for internal counter");
119 MODULE_PARM_DESC(autoage, "Auto-reseeding after specified timer countdowns to 0:\n"
120 " 0 - disable timer\n"
121 " other - reload value for internal timer");
[all …]
/linux/drivers/phy/freescale/
H A Dphy-fsl-imx8qm-hsio.c1 // SPDX-License-Identifier: GPL-2.0+
19 #include <dt-bindings/phy/phy.h>
20 #include <dt-bindings/phy/phy-imx8-pcie.h>
93 struct regmap *ctrl; member
120 struct imx_hsio_priv *priv = lane->priv; in imx_hsio_init()
121 struct device *dev = priv->dev; in imx_hsio_init()
124 switch (lane->phy_type) { in imx_hsio_init()
126 lane->phy_mode = PHY_MODE_PCIE; in imx_hsio_init()
127 if (lane->ctrl_index == 0) { /* PCIEA */ in imx_hsio_init()
128 lane->ctrl_off = 0; in imx_hsio_init()
[all …]
/linux/Documentation/devicetree/bindings/ufs/
H A Dhisilicon,ufs.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Li Wei <liwei213@huawei.com>
18 - hisilicon,hi3660-ufs
19 - hisilicon,hi3670-ufs
21 - compatible
24 - $ref: ufs-common.yaml
29 - items:
30 - const: hisilicon,hi3660-ufs
[all …]
/linux/drivers/spi/
H A Dspi-stm32.c1 // SPDX-License-Identifier: GPL-2.0
5 // Copyright (C) 2017, STMicroelectronics - All Rights Reserved
12 #include <linux/dma-mapping.h>
202 #define STM32_SPI_HOST_MODE(stm32_spi) (!(stm32_spi)->device_mode)
203 #define STM32_SPI_DEVICE_MODE(stm32_spi) ((stm32_spi)->device_mode)
206 * struct stm32_spi_reg - stm32 SPI register & bitfield desc
218 * struct stm32_spi_regspec - stm32 registers definition, compatible dependent data
250 * struct stm32_spi_cfg - stm32 compatible configuration data
305 * struct stm32_spi - private data of the SPI controller
307 * @ctrl: controller interface
[all …]
/linux/drivers/media/i2c/
H A Dimx274.c1 // SPDX-License-Identifier: GPL-2.0
3 * imx274.c - IMX274 CMOS Image Sensor driver
23 #include <linux/v4l2-mediabus.h>
26 #include <media/v4l2-ctrls.h>
27 #include <media/v4l2-device.h>
28 #include <media/v4l2-fwnode.h>
29 #include <media/v4l2-subdev.h>
49 #define IMX274_GAIN_SHIFT_MASK ((1 << IMX274_GAIN_SHIFT) - 1)
59 / (2048 - IMX274_GAIN_REG_MAX))
76 * register SHR is limited to (SVR value + 1) x VMAX value - 4
[all …]
H A Dmax2175.c1 // SPDX-License-Identifier: GPL-2.0
23 #include <media/v4l2-ctrls.h>
24 #include <media/v4l2-device.h>
30 #define mxm_dbg(ctx, fmt, arg...) dev_dbg(&ctx->client->dev, fmt, ## arg)
31 #define mxm_err(ctx, fmt, arg...) dev_err(&ctx->client->dev, fmt, ## arg)
264 struct v4l2_subdev sd; /* Sub-device */
273 struct v4l2_ctrl *hsls; /* High-side/Low-side polarity */
288 bool am_hiz; /* AM Hi-Z filter */
321 ret = regmap_read(ctx->regmap, idx, &regval); in max2175_read()
334 ret = regmap_write(ctx->regmap, idx, val); in max2175_write()
[all …]
/linux/drivers/gpu/drm/sun4i/
H A Dsun8i_tcon_top.c1 // SPDX-License-Identifier: GPL-2.0+
14 #include <dt-bindings/clock/sun8i-tcon-top.h>
34 if (!sun8i_tcon_top_node_is_tcon_top(dev->of_node)) { in sun8i_tcon_top_set_hdmi_src()
36 return -EINVAL; in sun8i_tcon_top_set_hdmi_src()
41 return -EINVAL; in sun8i_tcon_top_set_hdmi_src()
44 spin_lock_irqsave(&tcon_top->reg_lock, flags); in sun8i_tcon_top_set_hdmi_src()
46 val = readl(tcon_top->regs + TCON_TOP_GATE_SRC_REG); in sun8i_tcon_top_set_hdmi_src()
48 val |= FIELD_PREP(TCON_TOP_HDMI_SRC_MSK, tcon - 1); in sun8i_tcon_top_set_hdmi_src()
49 writel(val, tcon_top->regs + TCON_TOP_GATE_SRC_REG); in sun8i_tcon_top_set_hdmi_src()
51 spin_unlock_irqrestore(&tcon_top->reg_lock, flags); in sun8i_tcon_top_set_hdmi_src()
[all …]
/linux/arch/arm64/boot/dts/hisilicon/
H A Dhip06.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "hisilicon,hip06-d03";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
[all …]
/linux/arch/arm64/boot/dts/renesas/
H A Drzg3e-smarc-som.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
13 * 0 - SD0 is connected to eMMC (default)
14 * 1 - SD0 is connected to uSD0 card
17 * 0 - Select Misc. Signals routing
18 * 1 - Select LCD
21 * 0 - Select CAN routing
22 * 1 - Select PDM
26 compatible = "renesas,rzg3e-smarcm", "renesas,r9a09g047e57", "renesas,r9a09g047";
42 reg_1p8v: regulator-1p8v {
43 compatible = "regulator-fixed";
[all …]
/linux/drivers/net/ethernet/intel/igbvf/
H A Dvf.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2009 - 2018 Intel Corporation. */
22 * e1000_init_mac_params_vf - Inits MAC params
27 struct e1000_mac_info *mac = &hw->mac; in e1000_init_mac_params_vf()
29 /* VF's have no MTA Registers - PF feature only */ in e1000_init_mac_params_vf()
30 mac->mta_reg_count = 128; in e1000_init_mac_params_vf()
32 mac->rar_entry_count = 1; in e1000_init_mac_params_vf()
36 mac->ops.reset_hw = e1000_reset_hw_vf; in e1000_init_mac_params_vf()
38 mac->ops.init_hw = e1000_init_hw_vf; in e1000_init_mac_params_vf()
40 mac->ops.check_for_link = e1000_check_for_link_vf; in e1000_init_mac_params_vf()
[all …]
/linux/Documentation/admin-guide/sysctl/
H A Dkernel.rst5 .. See scripts/check-sysctl-docs to keep this up to date
13 Documentation/admin-guide/sysctl/index.rst.
15 ------------------------------------------------------------------------------
39 If BSD-style process accounting is enabled these values control
58 See Documentation/power/video.rst. This allows the video resume mode to be set,
71 The machine hardware name, the same output as ``uname -m``
98 Documentation/arch/x86/boot.rst for additional information.
108 Documentation/arch/x86/boot.rst for additional information.
129 Ctrl-Alt-Delete). Writing a value to this file which doesn't
130 correspond to a running process will result in ``-ESRCH``.
[all …]
/linux/drivers/scsi/be2iscsi/
H A Dbe_cmds.h1 /* SPDX-License-Identifier: GPL-2.0-only */
7 * linux-drivers@broadcom.com
16 * using Work Request Blocks (WRBs) submitted to the MCC-WRB ring or via one
28 /* bits 0 - embedded */
29 /* bits 1 - 2 reserved */
30 /* bits 3 - 7 sge count */
31 /* bits 8 - 23 reserved */
32 /* bits 24 - 31 special */
43 struct be_sge sgl[19]; /* used by non-embedded cmds */
61 #define CQE_STATUS_COMPL_SHIFT 0 /* bits 0 - 15 */
[all …]
/linux/drivers/misc/
H A Dad525x_dpot.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright (c) 2009-2010 Analog Devices, Inc.
33 * AD5291 1 256 20, 50, 100 (20-TP)
34 * AD5292 1 1024 20, 50, 100 (20-TP)
56 * AD5270 1 1024 20, 50, 100 (50-TP)
57 * AD5271 1 256 20, 50, 100 (50-TP)
58 * AD5272 1 1024 20, 50, 100 (50-TP)
59 * AD5274 1 256 20, 50, 100 (50-TP)
61 * See Documentation/misc-devices/ad525x_dpot.rst for more info.
68 * Copyright (c) 2006-2011 Michael Hennerich <michael.hennerich@analog.com>
[all …]
/linux/Documentation/devicetree/bindings/i2c/
H A Di2c-mux-gpmux.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/i2c/i2c-mux-gpmux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Peter Rosin <peda@axentia.se>
16 .-----. .-----.
18 .------------. '-----' '-----'
20 | | .--------+--------'
21 | .------. | .------+ child bus A, on MUX value set to 0
22 | | I2C |-|--| Mux |
[all …]
/linux/drivers/ata/
H A Dsata_sil24.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * sata_sil24.c - Driver for Silicon Image 3124/3132 SATA-2 controllers
17 #include <linux/dma-mapping.h>
30 __le16 ctrl; member
57 SIL24_MAX_SGT = (PAGE_SIZE - SIL24_PRB_SZ)
113 PORT_CTRL_STAT = 0x1000, /* write: ctrl-set, read: stat */
114 PORT_CTRL_CLR = 0x1004, /* write: ctrl-clear */
116 PORT_IRQ_ENABLE_SET = 0x1010, /* write: enable-set */
117 PORT_IRQ_ENABLE_CLR = 0x1014, /* write: enable-clear */
135 PORT_EXEC_DIAG = 0x1e00, /* 32bit exec diag * 16 (64 bytes, 0-10 used on 3124) */
[all …]
/linux/Documentation/networking/
H A Dsnmp_counter.rst17 .. _RFC1213 ipInReceives: https://tools.ietf.org/html/rfc1213#page-26
30 .. _RFC1213 ipInDelivers: https://tools.ietf.org/html/rfc1213#page-28
41 .. _RFC1213 ipOutRequests: https://tools.ietf.org/html/rfc1213#page-28
60 .. _Explicit Congestion Notification: https://tools.ietf.org/html/rfc3168#page-6
73 .. _RFC1213 ipInHdrErrors: https://tools.ietf.org/html/rfc1213#page-27
81 .. _RFC1213 ipInAddrErrors: https://tools.ietf.org/html/rfc1213#page-27
98 .. _RFC1213 ipInUnknownProtos: https://tools.ietf.org/html/rfc1213#page-27
111 .. _RFC1213 ipInDiscards: https://tools.ietf.org/html/rfc1213#page-28
118 .. _RFC1213 ipOutDiscards: https://tools.ietf.org/html/rfc1213#page-28
125 .. _RFC1213 ipOutNoRoutes: https://tools.ietf.org/html/rfc1213#page-29
[all …]
/linux/drivers/ufs/host/
H A Dufs-hisi.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (c) 2016-2017 Linaro Ltd.
6 * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
14 #include <linux/dma-mapping.h>
19 #include "ufshcd-pltfrm.h"
21 #include "ufs-hisi.h"
57 dev_err(hba->dev, "%s: unable to get TX_FSM_STATE, err %d\n", in ufs_hisi_check_hibern8()
61 err = -1; in ufs_hisi_check_hibern8()
62 dev_err(hba->dev, "%s: invalid TX_FSM_STATE, lane0 = %d, lane1 = %d\n", in ufs_hisi_check_hibern8()
88 if (!IS_ERR(host->rst)) in ufs_hisi_soc_init()
[all …]
/linux/Documentation/fb/
H A Dsh7760fb.rst6 -----------
29 - drivers/video/sh7760fb.c
30 - include/asm-sh/sh7760fb.h
31 - Documentation/fb/sh7760fb.rst
34 -----------------
47 --------------------
62 * NEC NL6440bc26-01 640x480 TFT
82 .left_margin = 114, /* HTOT - (HSYNSLEN + HSYNSTART) */
83 .right_margin = 16, /* HSYNSTART - XRES */
84 .upper_margin = 33, /* VTOT - (VSYNLEN + VSYNSTART) */
[all …]

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