Lines Matching +full:rst +full:- +full:ctrl
1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2014 Alexandre Belloni <alexandre.belloni@free-electrons.com>
8 * - When outputing the source clock directly, the PWM logic will be bypassed
46 #define PWM_PRD(prd) (((prd) - 1) << 16)
85 struct reset_control *rst; member
98 return readl(sun4ichip->base + offset); in sun4i_pwm_readl()
104 writel(val, sun4ichip->base + offset); in sun4i_pwm_writel()
116 clk_rate = clk_get_rate(sun4ichip->clk); in sun4i_pwm_get_state()
118 return -EINVAL; in sun4i_pwm_get_state()
127 if ((val & BIT_CH(PWM_BYPASS, pwm->hwpwm)) && in sun4i_pwm_get_state()
128 sun4ichip->data->has_direct_mod_clk_output) { in sun4i_pwm_get_state()
129 state->period = DIV_ROUND_UP_ULL(NSEC_PER_SEC, clk_rate); in sun4i_pwm_get_state()
130 state->duty_cycle = DIV_ROUND_UP_ULL(state->period, 2); in sun4i_pwm_get_state()
131 state->polarity = PWM_POLARITY_NORMAL; in sun4i_pwm_get_state()
132 state->enabled = true; in sun4i_pwm_get_state()
136 if ((PWM_REG_PRESCAL(val, pwm->hwpwm) == PWM_PRESCAL_MASK) && in sun4i_pwm_get_state()
137 sun4ichip->data->has_prescaler_bypass) in sun4i_pwm_get_state()
140 prescaler = prescaler_table[PWM_REG_PRESCAL(val, pwm->hwpwm)]; in sun4i_pwm_get_state()
143 return -EINVAL; in sun4i_pwm_get_state()
145 if (val & BIT_CH(PWM_ACT_STATE, pwm->hwpwm)) in sun4i_pwm_get_state()
146 state->polarity = PWM_POLARITY_NORMAL; in sun4i_pwm_get_state()
148 state->polarity = PWM_POLARITY_INVERSED; in sun4i_pwm_get_state()
150 if ((val & BIT_CH(PWM_CLK_GATING | PWM_EN, pwm->hwpwm)) == in sun4i_pwm_get_state()
151 BIT_CH(PWM_CLK_GATING | PWM_EN, pwm->hwpwm)) in sun4i_pwm_get_state()
152 state->enabled = true; in sun4i_pwm_get_state()
154 state->enabled = false; in sun4i_pwm_get_state()
156 val = sun4i_pwm_readl(sun4ichip, PWM_CH_PRD(pwm->hwpwm)); in sun4i_pwm_get_state()
159 state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate); in sun4i_pwm_get_state()
162 state->period = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate); in sun4i_pwm_get_state()
175 clk_rate = clk_get_rate(sun4ichip->clk); in sun4i_pwm_calculate()
177 *bypass = sun4ichip->data->has_direct_mod_clk_output && in sun4i_pwm_calculate()
178 state->enabled && in sun4i_pwm_calculate()
179 (state->period * clk_rate >= NSEC_PER_SEC) && in sun4i_pwm_calculate()
180 (state->period * clk_rate < 2 * NSEC_PER_SEC) && in sun4i_pwm_calculate()
181 (state->duty_cycle * clk_rate * 2 >= NSEC_PER_SEC); in sun4i_pwm_calculate()
187 if (sun4ichip->data->has_prescaler_bypass) { in sun4i_pwm_calculate()
195 div = clk_rate * state->period + NSEC_PER_SEC / 2; in sun4i_pwm_calculate()
197 if (div - 1 > PWM_PRD_MASK) in sun4i_pwm_calculate()
211 div = div * state->period; in sun4i_pwm_calculate()
213 if (div - 1 <= PWM_PRD_MASK) in sun4i_pwm_calculate()
217 if (div - 1 > PWM_PRD_MASK) in sun4i_pwm_calculate()
218 return -EINVAL; in sun4i_pwm_calculate()
222 div *= state->duty_cycle; in sun4i_pwm_calculate()
223 do_div(div, state->period); in sun4i_pwm_calculate()
235 u32 ctrl, duty = 0, period = 0, val; in sun4i_pwm_apply() local
243 ret = clk_prepare_enable(sun4ichip->clk); in sun4i_pwm_apply()
255 clk_disable_unprepare(sun4ichip->clk); in sun4i_pwm_apply()
259 ctrl = sun4i_pwm_readl(sun4ichip, PWM_CTRL_REG); in sun4i_pwm_apply()
261 if (sun4ichip->data->has_direct_mod_clk_output) { in sun4i_pwm_apply()
263 ctrl |= BIT_CH(PWM_BYPASS, pwm->hwpwm); in sun4i_pwm_apply()
265 sun4i_pwm_writel(sun4ichip, ctrl, PWM_CTRL_REG); in sun4i_pwm_apply()
269 ctrl &= ~BIT_CH(PWM_BYPASS, pwm->hwpwm); in sun4i_pwm_apply()
272 if (PWM_REG_PRESCAL(ctrl, pwm->hwpwm) != prescaler) { in sun4i_pwm_apply()
274 ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm); in sun4i_pwm_apply()
275 sun4i_pwm_writel(sun4ichip, ctrl, PWM_CTRL_REG); in sun4i_pwm_apply()
277 ctrl &= ~BIT_CH(PWM_PRESCAL_MASK, pwm->hwpwm); in sun4i_pwm_apply()
278 ctrl |= BIT_CH(prescaler, pwm->hwpwm); in sun4i_pwm_apply()
282 sun4i_pwm_writel(sun4ichip, val, PWM_CH_PRD(pwm->hwpwm)); in sun4i_pwm_apply()
284 if (state->polarity != PWM_POLARITY_NORMAL) in sun4i_pwm_apply()
285 ctrl &= ~BIT_CH(PWM_ACT_STATE, pwm->hwpwm); in sun4i_pwm_apply()
287 ctrl |= BIT_CH(PWM_ACT_STATE, pwm->hwpwm); in sun4i_pwm_apply()
289 ctrl |= BIT_CH(PWM_CLK_GATING, pwm->hwpwm); in sun4i_pwm_apply()
291 if (state->enabled) in sun4i_pwm_apply()
292 ctrl |= BIT_CH(PWM_EN, pwm->hwpwm); in sun4i_pwm_apply()
294 sun4i_pwm_writel(sun4ichip, ctrl, PWM_CTRL_REG); in sun4i_pwm_apply()
296 if (state->enabled) in sun4i_pwm_apply()
306 ctrl = sun4i_pwm_readl(sun4ichip, PWM_CTRL_REG); in sun4i_pwm_apply()
307 ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm); in sun4i_pwm_apply()
308 ctrl &= ~BIT_CH(PWM_EN, pwm->hwpwm); in sun4i_pwm_apply()
309 sun4i_pwm_writel(sun4ichip, ctrl, PWM_CTRL_REG); in sun4i_pwm_apply()
311 clk_disable_unprepare(sun4ichip->clk); in sun4i_pwm_apply()
350 .compatible = "allwinner,sun4i-a10-pwm",
353 .compatible = "allwinner,sun5i-a10s-pwm",
356 .compatible = "allwinner,sun5i-a13-pwm",
359 .compatible = "allwinner,sun7i-a20-pwm",
362 .compatible = "allwinner,sun8i-h3-pwm",
365 .compatible = "allwinner,sun50i-a64-pwm",
368 .compatible = "allwinner,sun50i-h6-pwm",
383 data = of_device_get_match_data(&pdev->dev); in sun4i_pwm_probe()
385 return -ENODEV; in sun4i_pwm_probe()
387 chip = devm_pwmchip_alloc(&pdev->dev, data->npwm, sizeof(*sun4ichip)); in sun4i_pwm_probe()
392 sun4ichip->data = data; in sun4i_pwm_probe()
393 sun4ichip->base = devm_platform_ioremap_resource(pdev, 0); in sun4i_pwm_probe()
394 if (IS_ERR(sun4ichip->base)) in sun4i_pwm_probe()
395 return PTR_ERR(sun4ichip->base); in sun4i_pwm_probe()
408 sun4ichip->clk = devm_clk_get_optional(&pdev->dev, "mod"); in sun4i_pwm_probe()
409 if (IS_ERR(sun4ichip->clk)) in sun4i_pwm_probe()
410 return dev_err_probe(&pdev->dev, PTR_ERR(sun4ichip->clk), in sun4i_pwm_probe()
413 if (!sun4ichip->clk) { in sun4i_pwm_probe()
414 sun4ichip->clk = devm_clk_get(&pdev->dev, NULL); in sun4i_pwm_probe()
415 if (IS_ERR(sun4ichip->clk)) in sun4i_pwm_probe()
416 return dev_err_probe(&pdev->dev, PTR_ERR(sun4ichip->clk), in sun4i_pwm_probe()
420 sun4ichip->bus_clk = devm_clk_get_optional(&pdev->dev, "bus"); in sun4i_pwm_probe()
421 if (IS_ERR(sun4ichip->bus_clk)) in sun4i_pwm_probe()
422 return dev_err_probe(&pdev->dev, PTR_ERR(sun4ichip->bus_clk), in sun4i_pwm_probe()
425 sun4ichip->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL); in sun4i_pwm_probe()
426 if (IS_ERR(sun4ichip->rst)) in sun4i_pwm_probe()
427 return dev_err_probe(&pdev->dev, PTR_ERR(sun4ichip->rst), in sun4i_pwm_probe()
431 ret = reset_control_deassert(sun4ichip->rst); in sun4i_pwm_probe()
433 dev_err(&pdev->dev, "cannot deassert reset control: %pe\n", in sun4i_pwm_probe()
442 ret = clk_prepare_enable(sun4ichip->bus_clk); in sun4i_pwm_probe()
444 dev_err(&pdev->dev, "cannot prepare and enable bus_clk %pe\n", in sun4i_pwm_probe()
449 chip->ops = &sun4i_pwm_ops; in sun4i_pwm_probe()
453 dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret); in sun4i_pwm_probe()
462 clk_disable_unprepare(sun4ichip->bus_clk); in sun4i_pwm_probe()
464 reset_control_assert(sun4ichip->rst); in sun4i_pwm_probe()
476 clk_disable_unprepare(sun4ichip->bus_clk); in sun4i_pwm_remove()
477 reset_control_assert(sun4ichip->rst); in sun4i_pwm_remove()
482 .name = "sun4i-pwm",
490 MODULE_ALIAS("platform:sun4i-pwm");
491 MODULE_AUTHOR("Alexandre Belloni <alexandre.belloni@free-electrons.com>");