Lines Matching +full:rst +full:- +full:ctrl
1 // SPDX-License-Identifier: GPL-2.0
5 // Copyright (C) 2017, STMicroelectronics - All Rights Reserved
12 #include <linux/dma-mapping.h>
202 #define STM32_SPI_HOST_MODE(stm32_spi) (!(stm32_spi)->device_mode)
203 #define STM32_SPI_DEVICE_MODE(stm32_spi) ((stm32_spi)->device_mode)
206 * struct stm32_spi_reg - stm32 SPI register & bitfield desc
218 * struct stm32_spi_regspec - stm32 registers definition, compatible dependent data
250 * struct stm32_spi_cfg - stm32 compatible configuration data
305 * struct stm32_spi - private data of the SPI controller
307 * @ctrl: controller interface
317 * @cur_midi: host inter-data idleness in ns
341 struct spi_controller *ctrl; member
443 writel_relaxed(readl_relaxed(spi->base + offset) | bits, in stm32_spi_set_bits()
444 spi->base + offset); in stm32_spi_set_bits()
450 writel_relaxed(readl_relaxed(spi->base + offset) & ~bits, in stm32_spi_clr_bits()
451 spi->base + offset); in stm32_spi_clr_bits()
455 * stm32h7_spi_get_fifo_size - Return fifo size
463 spin_lock_irqsave(&spi->lock, flags); in stm32h7_spi_get_fifo_size()
467 while (readl_relaxed(spi->base + STM32H7_SPI_SR) & STM32H7_SPI_SR_TXP) in stm32h7_spi_get_fifo_size()
468 writeb_relaxed(++count, spi->base + STM32H7_SPI_TXDR); in stm32h7_spi_get_fifo_size()
472 spin_unlock_irqrestore(&spi->lock, flags); in stm32h7_spi_get_fifo_size()
474 dev_dbg(spi->dev, "%d x 8-bit fifo size\n", count); in stm32h7_spi_get_fifo_size()
480 * stm32f4_spi_get_bpw_mask - Return bits per word mask
485 dev_dbg(spi->dev, "8-bit or 16-bit data frame supported\n"); in stm32f4_spi_get_bpw_mask()
490 * stm32f7_spi_get_bpw_mask - Return bits per word mask
495 dev_dbg(spi->dev, "16-bit maximum data frame\n"); in stm32f7_spi_get_bpw_mask()
500 * stm32h7_spi_get_bpw_mask - Return bits per word mask
508 spin_lock_irqsave(&spi->lock, flags); in stm32h7_spi_get_bpw_mask()
512 * maximum data size of periperal instances is limited to 16-bit in stm32h7_spi_get_bpw_mask()
516 cfg1 = readl_relaxed(spi->base + STM32H7_SPI_CFG1); in stm32h7_spi_get_bpw_mask()
519 spin_unlock_irqrestore(&spi->lock, flags); in stm32h7_spi_get_bpw_mask()
521 dev_dbg(spi->dev, "%d-bit maximum data frame\n", max_bpw); in stm32h7_spi_get_bpw_mask()
527 * stm32mp25_spi_get_bpw_mask - Return bits per word mask
534 if (spi->feature_set == STM32_SPI_FEATURE_LIMITED) { in stm32mp25_spi_get_bpw_mask()
535 dev_dbg(spi->dev, "8-bit or 16-bit data frame supported\n"); in stm32mp25_spi_get_bpw_mask()
540 readl_relaxed(spi->base + STM32MP25_SPI_HWCFGR1)); in stm32mp25_spi_get_bpw_mask()
544 dev_dbg(spi->dev, "%d-bit maximum data frame\n", max_bpw); in stm32mp25_spi_get_bpw_mask()
549 * stm32_spi_prepare_mbr - Determine baud rate divisor value
555 * Return baud rate divisor value in case of success or -EINVAL
562 /* Ensure spi->clk_rate is even */ in stm32_spi_prepare_mbr()
563 div = DIV_ROUND_CLOSEST(spi->clk_rate & ~0x1, speed_hz); in stm32_spi_prepare_mbr()
566 * SPI framework set xfer->speed_hz to ctrl->max_speed_hz if in stm32_spi_prepare_mbr()
567 * xfer->speed_hz is greater than ctrl->max_speed_hz, and it returns in stm32_spi_prepare_mbr()
568 * an error when xfer->speed_hz is lower than ctrl->min_speed_hz, so in stm32_spi_prepare_mbr()
573 return -EINVAL; in stm32_spi_prepare_mbr()
576 if (div & (div - 1)) in stm32_spi_prepare_mbr()
579 mbrdiv = fls(div) - 1; in stm32_spi_prepare_mbr()
581 spi->cur_speed = spi->clk_rate / (1 << mbrdiv); in stm32_spi_prepare_mbr()
583 spi->cur_half_period = DIV_ROUND_CLOSEST(USEC_PER_SEC, 2 * spi->cur_speed); in stm32_spi_prepare_mbr()
585 return mbrdiv - 1; in stm32_spi_prepare_mbr()
589 * stm32h7_spi_prepare_fthlv - Determine FIFO threshold level
598 packet = clamp(xfer_len, 1U, spi->fifo_size / 2); in stm32h7_spi_prepare_fthlv()
601 bpw = DIV_ROUND_UP(spi->cur_bpw, 8); in stm32h7_spi_prepare_fthlv()
606 * stm32f4_spi_write_tx - Write bytes to Transmit Data Register
614 if ((spi->tx_len > 0) && (readl_relaxed(spi->base + STM32FX_SPI_SR) & in stm32f4_spi_write_tx()
616 u32 offs = spi->cur_xferlen - spi->tx_len; in stm32f4_spi_write_tx()
618 if (spi->cur_bpw == 16) { in stm32f4_spi_write_tx()
619 const u16 *tx_buf16 = (const u16 *)(spi->tx_buf + offs); in stm32f4_spi_write_tx()
621 writew_relaxed(*tx_buf16, spi->base + STM32FX_SPI_DR); in stm32f4_spi_write_tx()
622 spi->tx_len -= sizeof(u16); in stm32f4_spi_write_tx()
624 const u8 *tx_buf8 = (const u8 *)(spi->tx_buf + offs); in stm32f4_spi_write_tx()
626 writeb_relaxed(*tx_buf8, spi->base + STM32FX_SPI_DR); in stm32f4_spi_write_tx()
627 spi->tx_len -= sizeof(u8); in stm32f4_spi_write_tx()
631 dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->tx_len); in stm32f4_spi_write_tx()
635 * stm32f7_spi_write_tx - Write bytes to Transmit Data Register
643 if ((spi->tx_len > 0) && (readl_relaxed(spi->base + STM32FX_SPI_SR) & in stm32f7_spi_write_tx()
645 u32 offs = spi->cur_xferlen - spi->tx_len; in stm32f7_spi_write_tx()
647 if (spi->tx_len >= sizeof(u16)) { in stm32f7_spi_write_tx()
648 const u16 *tx_buf16 = (const u16 *)(spi->tx_buf + offs); in stm32f7_spi_write_tx()
650 writew_relaxed(*tx_buf16, spi->base + STM32FX_SPI_DR); in stm32f7_spi_write_tx()
651 spi->tx_len -= sizeof(u16); in stm32f7_spi_write_tx()
653 const u8 *tx_buf8 = (const u8 *)(spi->tx_buf + offs); in stm32f7_spi_write_tx()
655 writeb_relaxed(*tx_buf8, spi->base + STM32FX_SPI_DR); in stm32f7_spi_write_tx()
656 spi->tx_len -= sizeof(u8); in stm32f7_spi_write_tx()
660 dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->tx_len); in stm32f7_spi_write_tx()
664 * stm32h7_spi_write_txfifo - Write bytes in Transmit Data Register
672 while ((spi->tx_len > 0) && in stm32h7_spi_write_txfifo()
673 (readl_relaxed(spi->base + STM32H7_SPI_SR) & in stm32h7_spi_write_txfifo()
675 u32 offs = spi->cur_xferlen - spi->tx_len; in stm32h7_spi_write_txfifo()
677 if (spi->tx_len >= sizeof(u32)) { in stm32h7_spi_write_txfifo()
678 const u32 *tx_buf32 = (const u32 *)(spi->tx_buf + offs); in stm32h7_spi_write_txfifo()
680 writel_relaxed(*tx_buf32, spi->base + STM32H7_SPI_TXDR); in stm32h7_spi_write_txfifo()
681 spi->tx_len -= sizeof(u32); in stm32h7_spi_write_txfifo()
682 } else if (spi->tx_len >= sizeof(u16)) { in stm32h7_spi_write_txfifo()
683 const u16 *tx_buf16 = (const u16 *)(spi->tx_buf + offs); in stm32h7_spi_write_txfifo()
685 writew_relaxed(*tx_buf16, spi->base + STM32H7_SPI_TXDR); in stm32h7_spi_write_txfifo()
686 spi->tx_len -= sizeof(u16); in stm32h7_spi_write_txfifo()
688 const u8 *tx_buf8 = (const u8 *)(spi->tx_buf + offs); in stm32h7_spi_write_txfifo()
690 writeb_relaxed(*tx_buf8, spi->base + STM32H7_SPI_TXDR); in stm32h7_spi_write_txfifo()
691 spi->tx_len -= sizeof(u8); in stm32h7_spi_write_txfifo()
695 dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->tx_len); in stm32h7_spi_write_txfifo()
699 * stm32f4_spi_read_rx - Read bytes from Receive Data Register
707 if ((spi->rx_len > 0) && (readl_relaxed(spi->base + STM32FX_SPI_SR) & in stm32f4_spi_read_rx()
709 u32 offs = spi->cur_xferlen - spi->rx_len; in stm32f4_spi_read_rx()
711 if (spi->cur_bpw == 16) { in stm32f4_spi_read_rx()
712 u16 *rx_buf16 = (u16 *)(spi->rx_buf + offs); in stm32f4_spi_read_rx()
714 *rx_buf16 = readw_relaxed(spi->base + STM32FX_SPI_DR); in stm32f4_spi_read_rx()
715 spi->rx_len -= sizeof(u16); in stm32f4_spi_read_rx()
717 u8 *rx_buf8 = (u8 *)(spi->rx_buf + offs); in stm32f4_spi_read_rx()
719 *rx_buf8 = readb_relaxed(spi->base + STM32FX_SPI_DR); in stm32f4_spi_read_rx()
720 spi->rx_len -= sizeof(u8); in stm32f4_spi_read_rx()
724 dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->rx_len); in stm32f4_spi_read_rx()
728 * stm32f7_spi_read_rx - Read bytes from Receive Data Register
736 u32 sr = readl_relaxed(spi->base + STM32FX_SPI_SR); in stm32f7_spi_read_rx()
739 while ((spi->rx_len > 0) && (frlvl > 0)) { in stm32f7_spi_read_rx()
740 u32 offs = spi->cur_xferlen - spi->rx_len; in stm32f7_spi_read_rx()
742 if ((spi->rx_len >= sizeof(u16)) && (frlvl >= 2)) { in stm32f7_spi_read_rx()
743 u16 *rx_buf16 = (u16 *)(spi->rx_buf + offs); in stm32f7_spi_read_rx()
745 *rx_buf16 = readw_relaxed(spi->base + STM32FX_SPI_DR); in stm32f7_spi_read_rx()
746 spi->rx_len -= sizeof(u16); in stm32f7_spi_read_rx()
748 u8 *rx_buf8 = (u8 *)(spi->rx_buf + offs); in stm32f7_spi_read_rx()
750 *rx_buf8 = readb_relaxed(spi->base + STM32FX_SPI_DR); in stm32f7_spi_read_rx()
751 spi->rx_len -= sizeof(u8); in stm32f7_spi_read_rx()
754 sr = readl_relaxed(spi->base + STM32FX_SPI_SR); in stm32f7_spi_read_rx()
758 if (spi->rx_len >= sizeof(u16)) in stm32f7_spi_read_rx()
763 dev_dbg(spi->dev, "%s: %d bytes left (sr=%08x)\n", in stm32f7_spi_read_rx()
764 __func__, spi->rx_len, sr); in stm32f7_spi_read_rx()
768 * stm32h7_spi_read_rxfifo - Read bytes in Receive Data Register
776 u32 sr = readl_relaxed(spi->base + STM32H7_SPI_SR); in stm32h7_spi_read_rxfifo()
779 while ((spi->rx_len > 0) && in stm32h7_spi_read_rxfifo()
783 u32 offs = spi->cur_xferlen - spi->rx_len; in stm32h7_spi_read_rxfifo()
785 if ((spi->rx_len >= sizeof(u32)) || in stm32h7_spi_read_rxfifo()
787 u32 *rx_buf32 = (u32 *)(spi->rx_buf + offs); in stm32h7_spi_read_rxfifo()
789 *rx_buf32 = readl_relaxed(spi->base + STM32H7_SPI_RXDR); in stm32h7_spi_read_rxfifo()
790 spi->rx_len -= sizeof(u32); in stm32h7_spi_read_rxfifo()
791 } else if ((spi->rx_len >= sizeof(u16)) || in stm32h7_spi_read_rxfifo()
793 (rxplvl >= 2 || spi->cur_bpw > 8))) { in stm32h7_spi_read_rxfifo()
794 u16 *rx_buf16 = (u16 *)(spi->rx_buf + offs); in stm32h7_spi_read_rxfifo()
796 *rx_buf16 = readw_relaxed(spi->base + STM32H7_SPI_RXDR); in stm32h7_spi_read_rxfifo()
797 spi->rx_len -= sizeof(u16); in stm32h7_spi_read_rxfifo()
799 u8 *rx_buf8 = (u8 *)(spi->rx_buf + offs); in stm32h7_spi_read_rxfifo()
801 *rx_buf8 = readb_relaxed(spi->base + STM32H7_SPI_RXDR); in stm32h7_spi_read_rxfifo()
802 spi->rx_len -= sizeof(u8); in stm32h7_spi_read_rxfifo()
805 sr = readl_relaxed(spi->base + STM32H7_SPI_SR); in stm32h7_spi_read_rxfifo()
809 dev_dbg(spi->dev, "%s: %d bytes left (sr=%08x)\n", in stm32h7_spi_read_rxfifo()
810 __func__, spi->rx_len, sr); in stm32h7_spi_read_rxfifo()
814 * stm32_spi_enable - Enable SPI controller
819 dev_dbg(spi->dev, "enable controller\n"); in stm32_spi_enable()
821 stm32_spi_set_bits(spi, spi->cfg->regs->en.reg, in stm32_spi_enable()
822 spi->cfg->regs->en.mask); in stm32_spi_enable()
826 * stm32fx_spi_disable - Disable SPI controller
834 dev_dbg(spi->dev, "disable controller\n"); in stm32fx_spi_disable()
836 spin_lock_irqsave(&spi->lock, flags); in stm32fx_spi_disable()
838 if (!(readl_relaxed(spi->base + STM32FX_SPI_CR1) & in stm32fx_spi_disable()
840 spin_unlock_irqrestore(&spi->lock, flags); in stm32fx_spi_disable()
850 if (readl_relaxed_poll_timeout_atomic(spi->base + STM32FX_SPI_SR, in stm32fx_spi_disable()
853 dev_warn(spi->dev, "disabling condition timeout\n"); in stm32fx_spi_disable()
856 if (spi->cur_usedma && spi->dma_tx) in stm32fx_spi_disable()
857 dmaengine_terminate_async(spi->dma_tx); in stm32fx_spi_disable()
858 if (spi->cur_usedma && spi->dma_rx) in stm32fx_spi_disable()
859 dmaengine_terminate_async(spi->dma_rx); in stm32fx_spi_disable()
867 readl_relaxed(spi->base + STM32FX_SPI_DR); in stm32fx_spi_disable()
868 readl_relaxed(spi->base + STM32FX_SPI_SR); in stm32fx_spi_disable()
870 spin_unlock_irqrestore(&spi->lock, flags); in stm32fx_spi_disable()
874 * stm32h7_spi_disable - Disable SPI controller
877 * RX-Fifo is flushed when SPI controller is disabled.
884 dev_dbg(spi->dev, "disable controller\n"); in stm32h7_spi_disable()
886 spin_lock_irqsave(&spi->lock, flags); in stm32h7_spi_disable()
888 cr1 = readl_relaxed(spi->base + STM32H7_SPI_CR1); in stm32h7_spi_disable()
891 spin_unlock_irqrestore(&spi->lock, flags); in stm32h7_spi_disable()
896 if (spi->cur_half_period) in stm32h7_spi_disable()
897 udelay(spi->cur_half_period); in stm32h7_spi_disable()
899 if (spi->cur_usedma && spi->dma_tx) in stm32h7_spi_disable()
900 dmaengine_terminate_async(spi->dma_tx); in stm32h7_spi_disable()
901 if (spi->cur_usedma && spi->dma_rx) { in stm32h7_spi_disable()
902 dmaengine_terminate_async(spi->dma_rx); in stm32h7_spi_disable()
903 if (spi->mdma_rx) in stm32h7_spi_disable()
904 dmaengine_terminate_async(spi->mdma_rx); in stm32h7_spi_disable()
913 writel_relaxed(0, spi->base + STM32H7_SPI_IER); in stm32h7_spi_disable()
914 writel_relaxed(STM32H7_SPI_IFCR_ALL, spi->base + STM32H7_SPI_IFCR); in stm32h7_spi_disable()
916 spin_unlock_irqrestore(&spi->lock, flags); in stm32h7_spi_disable()
920 * stm32_spi_can_dma - Determine if the transfer is eligible for DMA use
921 * @ctrl: controller interface
928 static bool stm32_spi_can_dma(struct spi_controller *ctrl, in stm32_spi_can_dma() argument
933 struct stm32_spi *spi = spi_controller_get_devdata(ctrl); in stm32_spi_can_dma()
935 if (spi->cfg->has_fifo) in stm32_spi_can_dma()
936 dma_size = spi->fifo_size; in stm32_spi_can_dma()
940 dev_dbg(spi->dev, "%s: %s\n", __func__, in stm32_spi_can_dma()
941 (transfer->len > dma_size) ? "true" : "false"); in stm32_spi_can_dma()
943 return (transfer->len > dma_size); in stm32_spi_can_dma()
947 * stm32fx_spi_irq_event - Interrupt handler for SPI controller events
949 * @dev_id: SPI controller ctrl interface
953 struct spi_controller *ctrl = dev_id; in stm32fx_spi_irq_event() local
954 struct stm32_spi *spi = spi_controller_get_devdata(ctrl); in stm32fx_spi_irq_event()
958 spin_lock(&spi->lock); in stm32fx_spi_irq_event()
960 sr = readl_relaxed(spi->base + STM32FX_SPI_SR); in stm32fx_spi_irq_event()
967 if (!spi->cur_usedma && (spi->cur_comm == SPI_SIMPLEX_TX || in stm32fx_spi_irq_event()
968 spi->cur_comm == SPI_3WIRE_TX)) { in stm32fx_spi_irq_event()
974 if (!spi->cur_usedma && (spi->cur_comm == SPI_FULL_DUPLEX || in stm32fx_spi_irq_event()
975 spi->cur_comm == SPI_SIMPLEX_RX || in stm32fx_spi_irq_event()
976 spi->cur_comm == SPI_3WIRE_RX)) { in stm32fx_spi_irq_event()
983 dev_dbg(spi->dev, "spurious IT (sr=0x%08x)\n", sr); in stm32fx_spi_irq_event()
984 spin_unlock(&spi->lock); in stm32fx_spi_irq_event()
989 dev_warn(spi->dev, "Overrun: received value discarded\n"); in stm32fx_spi_irq_event()
992 readl_relaxed(spi->base + STM32FX_SPI_DR); in stm32fx_spi_irq_event()
993 readl_relaxed(spi->base + STM32FX_SPI_SR); in stm32fx_spi_irq_event()
1005 if (spi->tx_buf) in stm32fx_spi_irq_event()
1006 spi->cfg->write_tx(spi); in stm32fx_spi_irq_event()
1007 if (spi->tx_len == 0) in stm32fx_spi_irq_event()
1012 spi->cfg->read_rx(spi); in stm32fx_spi_irq_event()
1013 if (spi->rx_len == 0) in stm32fx_spi_irq_event()
1015 else if (spi->tx_buf)/* Load data for discontinuous mode */ in stm32fx_spi_irq_event()
1016 spi->cfg->write_tx(spi); in stm32fx_spi_irq_event()
1026 spin_unlock(&spi->lock); in stm32fx_spi_irq_event()
1030 spin_unlock(&spi->lock); in stm32fx_spi_irq_event()
1035 * stm32fx_spi_irq_thread - Thread of interrupt handler for SPI controller
1041 struct spi_controller *ctrl = dev_id; in stm32fx_spi_irq_thread() local
1042 struct stm32_spi *spi = spi_controller_get_devdata(ctrl); in stm32fx_spi_irq_thread()
1044 spi_finalize_current_transfer(ctrl); in stm32fx_spi_irq_thread()
1051 * stm32h7_spi_irq_thread - Thread of interrupt handler for SPI controller
1057 struct spi_controller *ctrl = dev_id; in stm32h7_spi_irq_thread() local
1058 struct stm32_spi *spi = spi_controller_get_devdata(ctrl); in stm32h7_spi_irq_thread()
1063 spin_lock_irqsave(&spi->lock, flags); in stm32h7_spi_irq_thread()
1065 sr = readl_relaxed(spi->base + STM32H7_SPI_SR); in stm32h7_spi_irq_thread()
1066 ier = readl_relaxed(spi->base + STM32H7_SPI_IER); in stm32h7_spi_irq_thread()
1076 * DXPIE is set in Full-Duplex, one IT will be raised if TXP and RXP in stm32h7_spi_irq_thread()
1077 * are set. So in case of Full-Duplex, need to poll TXP and RXP event. in stm32h7_spi_irq_thread()
1079 if ((spi->cur_comm == SPI_FULL_DUPLEX) && !spi->cur_usedma) in stm32h7_spi_irq_thread()
1083 dev_vdbg(spi->dev, "spurious IT (sr=0x%08x, ier=0x%08x)\n", in stm32h7_spi_irq_thread()
1085 spin_unlock_irqrestore(&spi->lock, flags); in stm32h7_spi_irq_thread()
1095 dev_dbg_ratelimited(spi->dev, "Communication suspended\n"); in stm32h7_spi_irq_thread()
1096 if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0))) in stm32h7_spi_irq_thread()
1102 if (spi->cur_usedma) in stm32h7_spi_irq_thread()
1107 dev_warn(spi->dev, "Mode fault: transfer aborted\n"); in stm32h7_spi_irq_thread()
1112 dev_err(spi->dev, "Overrun: RX data lost\n"); in stm32h7_spi_irq_thread()
1117 dev_dbg(spi->dev, "End of transfer\n"); in stm32h7_spi_irq_thread()
1118 if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0))) in stm32h7_spi_irq_thread()
1120 if (!spi->cur_usedma || in stm32h7_spi_irq_thread()
1121 (spi->cur_comm == SPI_SIMPLEX_TX || spi->cur_comm == SPI_3WIRE_TX) || in stm32h7_spi_irq_thread()
1122 (spi->mdma_rx && (spi->cur_comm == SPI_SIMPLEX_RX || in stm32h7_spi_irq_thread()
1123 spi->cur_comm == SPI_FULL_DUPLEX))) in stm32h7_spi_irq_thread()
1128 if (!spi->cur_usedma && (spi->tx_buf && (spi->tx_len > 0))) in stm32h7_spi_irq_thread()
1132 if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0))) in stm32h7_spi_irq_thread()
1135 writel_relaxed(sr & mask, spi->base + STM32H7_SPI_IFCR); in stm32h7_spi_irq_thread()
1137 spin_unlock_irqrestore(&spi->lock, flags); in stm32h7_spi_irq_thread()
1140 if (spi->cur_usedma && spi->mdma_rx) { in stm32h7_spi_irq_thread()
1141 dmaengine_pause(spi->dma_rx); in stm32h7_spi_irq_thread()
1146 spi_finalize_current_transfer(ctrl); in stm32h7_spi_irq_thread()
1154 struct spi_controller *ctrl = msg->spi->controller; in stm32_spi_optimize_message() local
1155 struct stm32_spi *spi = spi_controller_get_devdata(ctrl); in stm32_spi_optimize_message()
1161 if (spi->cfg->set_number_of_data) in stm32_spi_optimize_message()
1162 return spi_split_transfers_maxwords(ctrl, msg, spi->t_size_max); in stm32_spi_optimize_message()
1168 * stm32_spi_prepare_msg - set up the controller to transfer a single message
1169 * @ctrl: controller interface
1172 static int stm32_spi_prepare_msg(struct spi_controller *ctrl, in stm32_spi_prepare_msg() argument
1175 struct stm32_spi *spi = spi_controller_get_devdata(ctrl); in stm32_spi_prepare_msg()
1176 struct spi_device *spi_dev = msg->spi; in stm32_spi_prepare_msg()
1177 struct device_node *np = spi_dev->dev.of_node; in stm32_spi_prepare_msg()
1182 spi->cur_midi = 0; in stm32_spi_prepare_msg()
1183 if (np && !of_property_read_u32(np, "st,spi-midi-ns", &spi->cur_midi)) in stm32_spi_prepare_msg()
1184 dev_dbg(spi->dev, "%dns inter-data idleness\n", spi->cur_midi); in stm32_spi_prepare_msg()
1186 if (spi_dev->mode & SPI_CPOL) in stm32_spi_prepare_msg()
1187 setb |= spi->cfg->regs->cpol.mask; in stm32_spi_prepare_msg()
1189 clrb |= spi->cfg->regs->cpol.mask; in stm32_spi_prepare_msg()
1191 if (spi_dev->mode & SPI_CPHA) in stm32_spi_prepare_msg()
1192 setb |= spi->cfg->regs->cpha.mask; in stm32_spi_prepare_msg()
1194 clrb |= spi->cfg->regs->cpha.mask; in stm32_spi_prepare_msg()
1196 if (spi_dev->mode & SPI_LSB_FIRST) in stm32_spi_prepare_msg()
1197 setb |= spi->cfg->regs->lsb_first.mask; in stm32_spi_prepare_msg()
1199 clrb |= spi->cfg->regs->lsb_first.mask; in stm32_spi_prepare_msg()
1201 if (STM32_SPI_DEVICE_MODE(spi) && spi_dev->mode & SPI_CS_HIGH) in stm32_spi_prepare_msg()
1202 setb |= spi->cfg->regs->cs_high.mask; in stm32_spi_prepare_msg()
1204 clrb |= spi->cfg->regs->cs_high.mask; in stm32_spi_prepare_msg()
1206 if (spi_dev->mode & SPI_READY) in stm32_spi_prepare_msg()
1207 setb |= spi->cfg->regs->rdy_en.mask; in stm32_spi_prepare_msg()
1209 clrb |= spi->cfg->regs->rdy_en.mask; in stm32_spi_prepare_msg()
1211 dev_dbg(spi->dev, "cpol=%d cpha=%d lsb_first=%d cs_high=%d rdy=%d\n", in stm32_spi_prepare_msg()
1212 !!(spi_dev->mode & SPI_CPOL), in stm32_spi_prepare_msg()
1213 !!(spi_dev->mode & SPI_CPHA), in stm32_spi_prepare_msg()
1214 !!(spi_dev->mode & SPI_LSB_FIRST), in stm32_spi_prepare_msg()
1215 !!(spi_dev->mode & SPI_CS_HIGH), in stm32_spi_prepare_msg()
1216 !!(spi_dev->mode & SPI_READY)); in stm32_spi_prepare_msg()
1218 spin_lock_irqsave(&spi->lock, flags); in stm32_spi_prepare_msg()
1223 (readl_relaxed(spi->base + spi->cfg->regs->cpol.reg) & in stm32_spi_prepare_msg()
1225 spi->base + spi->cfg->regs->cpol.reg); in stm32_spi_prepare_msg()
1227 spin_unlock_irqrestore(&spi->lock, flags); in stm32_spi_prepare_msg()
1233 * stm32fx_spi_dma_tx_cb - dma callback
1242 if (spi->cur_comm == SPI_SIMPLEX_TX || spi->cur_comm == SPI_3WIRE_TX) { in stm32fx_spi_dma_tx_cb()
1243 spi_finalize_current_transfer(spi->ctrl); in stm32fx_spi_dma_tx_cb()
1249 * stm32_spi_dma_rx_cb - dma callback
1258 spi_finalize_current_transfer(spi->ctrl); in stm32_spi_dma_rx_cb()
1259 spi->cfg->disable(spi); in stm32_spi_dma_rx_cb()
1263 * stm32_spi_dma_config - configure dma slave channel depending on current
1280 if (spi->cur_bpw <= 8) in stm32_spi_dma_config()
1282 else if (spi->cur_bpw <= 16) in stm32_spi_dma_config()
1288 if (!spi->cfg->prevent_dma_burst && spi->cfg->has_fifo && spi->cur_fthlv != 2) in stm32_spi_dma_config()
1289 maxburst = spi->cur_fthlv; in stm32_spi_dma_config()
1297 dma_conf->direction = dir; in stm32_spi_dma_config()
1298 if (dma_conf->direction == DMA_DEV_TO_MEM) { /* RX */ in stm32_spi_dma_config()
1299 dma_conf->src_addr = spi->phys_addr + spi->cfg->regs->rx.reg; in stm32_spi_dma_config()
1300 dma_conf->src_addr_width = buswidth; in stm32_spi_dma_config()
1301 dma_conf->src_maxburst = maxburst; in stm32_spi_dma_config()
1303 dev_dbg(spi->dev, "Rx DMA config buswidth=%d, maxburst=%d\n", in stm32_spi_dma_config()
1305 } else if (dma_conf->direction == DMA_MEM_TO_DEV) { /* TX */ in stm32_spi_dma_config()
1306 dma_conf->dst_addr = spi->phys_addr + spi->cfg->regs->tx.reg; in stm32_spi_dma_config()
1307 dma_conf->dst_addr_width = buswidth; in stm32_spi_dma_config()
1308 dma_conf->dst_maxburst = maxburst; in stm32_spi_dma_config()
1310 dev_dbg(spi->dev, "Tx DMA config buswidth=%d, maxburst=%d\n", in stm32_spi_dma_config()
1316 * stm32fx_spi_transfer_one_irq - transfer a single spi_transfer using
1329 if (spi->cur_comm == SPI_SIMPLEX_TX || spi->cur_comm == SPI_3WIRE_TX) { in stm32fx_spi_transfer_one_irq()
1331 } else if (spi->cur_comm == SPI_FULL_DUPLEX || in stm32fx_spi_transfer_one_irq()
1332 spi->cur_comm == SPI_SIMPLEX_RX || in stm32fx_spi_transfer_one_irq()
1333 spi->cur_comm == SPI_3WIRE_RX) { in stm32fx_spi_transfer_one_irq()
1334 /* In transmit-only mode, the OVR flag is set in the SR register in stm32fx_spi_transfer_one_irq()
1340 return -EINVAL; in stm32fx_spi_transfer_one_irq()
1343 spin_lock_irqsave(&spi->lock, flags); in stm32fx_spi_transfer_one_irq()
1350 if (spi->tx_buf) in stm32fx_spi_transfer_one_irq()
1351 spi->cfg->write_tx(spi); in stm32fx_spi_transfer_one_irq()
1353 spin_unlock_irqrestore(&spi->lock, flags); in stm32fx_spi_transfer_one_irq()
1359 * stm32h7_spi_transfer_one_irq - transfer a single spi_transfer using
1372 if (spi->tx_buf && spi->rx_buf) /* Full Duplex */ in stm32h7_spi_transfer_one_irq()
1374 else if (spi->tx_buf) /* Half-Duplex TX dir or Simplex TX */ in stm32h7_spi_transfer_one_irq()
1376 else if (spi->rx_buf) /* Half-Duplex RX dir or Simplex RX */ in stm32h7_spi_transfer_one_irq()
1383 spin_lock_irqsave(&spi->lock, flags); in stm32h7_spi_transfer_one_irq()
1388 if (spi->tx_buf) in stm32h7_spi_transfer_one_irq()
1394 writel_relaxed(ier, spi->base + STM32H7_SPI_IER); in stm32h7_spi_transfer_one_irq()
1396 spin_unlock_irqrestore(&spi->lock, flags); in stm32h7_spi_transfer_one_irq()
1402 * stm32fx_spi_transfer_one_dma_start - Set SPI driver registers to start
1409 if (spi->cur_comm == SPI_SIMPLEX_RX || spi->cur_comm == SPI_3WIRE_RX || in stm32fx_spi_transfer_one_dma_start()
1410 spi->cur_comm == SPI_FULL_DUPLEX) { in stm32fx_spi_transfer_one_dma_start()
1412 * In transmit-only mode, the OVR flag is set in the SR register in stm32fx_spi_transfer_one_dma_start()
1423 * stm32f7_spi_transfer_one_dma_start - Set SPI driver registers to start
1430 if (spi->cur_bpw <= 8) in stm32f7_spi_transfer_one_dma_start()
1439 * stm32h7_spi_transfer_one_dma_start - Set SPI driver registers to start
1448 if (spi->cur_comm == SPI_SIMPLEX_TX || spi->cur_comm == SPI_3WIRE_TX) in stm32h7_spi_transfer_one_dma_start()
1450 if (spi->mdma_rx && (spi->cur_comm == SPI_SIMPLEX_RX || spi->cur_comm == SPI_FULL_DUPLEX)) in stm32h7_spi_transfer_one_dma_start()
1462 * stm32_spi_prepare_rx_dma_mdma_chaining - Prepare RX DMA and MDMA chaining
1486 sram_period = spi->sram_rx_buf_size / 2; in stm32_spi_prepare_rx_dma_mdma_chaining()
1489 rx_mdma_conf.direction = rx_dma_conf->direction; in stm32_spi_prepare_rx_dma_mdma_chaining()
1490 rx_mdma_conf.src_addr = spi->sram_dma_rx_buf; in stm32_spi_prepare_rx_dma_mdma_chaining()
1491 rx_mdma_conf.peripheral_config = rx_dma_conf->peripheral_config; in stm32_spi_prepare_rx_dma_mdma_chaining()
1492 rx_mdma_conf.peripheral_size = rx_dma_conf->peripheral_size; in stm32_spi_prepare_rx_dma_mdma_chaining()
1493 dmaengine_slave_config(spi->mdma_rx, &rx_mdma_conf); in stm32_spi_prepare_rx_dma_mdma_chaining()
1496 for_each_sg(xfer->rx_sg.sgl, spi_s, xfer->rx_sg.nents, i) in stm32_spi_prepare_rx_dma_mdma_chaining()
1507 spi_s = xfer->rx_sg.sgl; in stm32_spi_prepare_rx_dma_mdma_chaining()
1509 dma_buf = spi->sram_dma_rx_buf; in stm32_spi_prepare_rx_dma_mdma_chaining()
1515 spi_s_len -= bytes; in stm32_spi_prepare_rx_dma_mdma_chaining()
1520 dma_buf = spi->sram_dma_rx_buf; in stm32_spi_prepare_rx_dma_mdma_chaining()
1525 dma_buf = spi->sram_dma_rx_buf; in stm32_spi_prepare_rx_dma_mdma_chaining()
1529 _dma_desc = dmaengine_prep_slave_sg(spi->dma_rx, dma_sgt.sgl, in stm32_spi_prepare_rx_dma_mdma_chaining()
1530 dma_sgt.nents, rx_dma_conf->direction, in stm32_spi_prepare_rx_dma_mdma_chaining()
1535 return -EINVAL; in stm32_spi_prepare_rx_dma_mdma_chaining()
1544 spi_s = xfer->rx_sg.sgl; in stm32_spi_prepare_rx_dma_mdma_chaining()
1552 spi_s_len -= bytes; in stm32_spi_prepare_rx_dma_mdma_chaining()
1563 _mdma_desc = dmaengine_prep_slave_sg(spi->mdma_rx, mdma_sgt.sgl, in stm32_spi_prepare_rx_dma_mdma_chaining()
1570 return -EINVAL; in stm32_spi_prepare_rx_dma_mdma_chaining()
1577 * stm32_spi_transfer_one_dma - transfer a single spi_transfer using DMA
1593 spin_lock_irqsave(&spi->lock, flags); in stm32_spi_transfer_one_dma()
1595 if (spi->rx_buf && spi->dma_rx) { in stm32_spi_transfer_one_dma()
1596 stm32_spi_dma_config(spi, spi->dma_rx, &rx_dma_conf, DMA_DEV_TO_MEM); in stm32_spi_transfer_one_dma()
1597 if (spi->mdma_rx) { in stm32_spi_transfer_one_dma()
1599 dmaengine_slave_config(spi->dma_rx, &rx_dma_conf); in stm32_spi_transfer_one_dma()
1609 dmaengine_slave_config(spi->dma_rx, &rx_dma_conf); in stm32_spi_transfer_one_dma()
1610 rx_dma_desc = dmaengine_prep_slave_sg(spi->dma_rx, xfer->rx_sg.sgl, in stm32_spi_transfer_one_dma()
1611 xfer->rx_sg.nents, in stm32_spi_transfer_one_dma()
1617 if (spi->tx_buf && spi->dma_tx) { in stm32_spi_transfer_one_dma()
1618 stm32_spi_dma_config(spi, spi->dma_tx, &tx_dma_conf, DMA_MEM_TO_DEV); in stm32_spi_transfer_one_dma()
1619 dmaengine_slave_config(spi->dma_tx, &tx_dma_conf); in stm32_spi_transfer_one_dma()
1620 tx_dma_desc = dmaengine_prep_slave_sg(spi->dma_tx, xfer->tx_sg.sgl, in stm32_spi_transfer_one_dma()
1621 xfer->tx_sg.nents, in stm32_spi_transfer_one_dma()
1626 if ((spi->tx_buf && spi->dma_tx && !tx_dma_desc) || in stm32_spi_transfer_one_dma()
1627 (spi->rx_buf && spi->dma_rx && !rx_dma_desc)) in stm32_spi_transfer_one_dma()
1630 if (spi->cur_comm == SPI_FULL_DUPLEX && (!tx_dma_desc || !rx_dma_desc)) in stm32_spi_transfer_one_dma()
1635 rx_mdma_desc->callback = spi->cfg->dma_rx_cb; in stm32_spi_transfer_one_dma()
1636 rx_mdma_desc->callback_param = spi; in stm32_spi_transfer_one_dma()
1638 rx_dma_desc->callback = spi->cfg->dma_rx_cb; in stm32_spi_transfer_one_dma()
1639 rx_dma_desc->callback_param = spi; in stm32_spi_transfer_one_dma()
1643 stm32_spi_set_bits(spi, spi->cfg->regs->dma_rx_en.reg, in stm32_spi_transfer_one_dma()
1644 spi->cfg->regs->dma_rx_en.mask); in stm32_spi_transfer_one_dma()
1647 dev_err(spi->dev, "Rx MDMA submit failed\n"); in stm32_spi_transfer_one_dma()
1651 dma_async_issue_pending(spi->mdma_rx); in stm32_spi_transfer_one_dma()
1654 dev_err(spi->dev, "Rx DMA submit failed\n"); in stm32_spi_transfer_one_dma()
1658 dma_async_issue_pending(spi->dma_rx); in stm32_spi_transfer_one_dma()
1662 if (spi->cur_comm == SPI_SIMPLEX_TX || in stm32_spi_transfer_one_dma()
1663 spi->cur_comm == SPI_3WIRE_TX) { in stm32_spi_transfer_one_dma()
1664 tx_dma_desc->callback = spi->cfg->dma_tx_cb; in stm32_spi_transfer_one_dma()
1665 tx_dma_desc->callback_param = spi; in stm32_spi_transfer_one_dma()
1669 dev_err(spi->dev, "Tx DMA submit failed\n"); in stm32_spi_transfer_one_dma()
1673 dma_async_issue_pending(spi->dma_tx); in stm32_spi_transfer_one_dma()
1676 stm32_spi_set_bits(spi, spi->cfg->regs->dma_tx_en.reg, in stm32_spi_transfer_one_dma()
1677 spi->cfg->regs->dma_tx_en.mask); in stm32_spi_transfer_one_dma()
1680 spi->cfg->transfer_one_dma_start(spi); in stm32_spi_transfer_one_dma()
1682 spin_unlock_irqrestore(&spi->lock, flags); in stm32_spi_transfer_one_dma()
1687 if (spi->mdma_rx) in stm32_spi_transfer_one_dma()
1688 dmaengine_terminate_sync(spi->mdma_rx); in stm32_spi_transfer_one_dma()
1689 if (spi->dma_rx) in stm32_spi_transfer_one_dma()
1690 dmaengine_terminate_sync(spi->dma_rx); in stm32_spi_transfer_one_dma()
1693 stm32_spi_clr_bits(spi, spi->cfg->regs->dma_rx_en.reg, in stm32_spi_transfer_one_dma()
1694 spi->cfg->regs->dma_rx_en.mask); in stm32_spi_transfer_one_dma()
1696 spin_unlock_irqrestore(&spi->lock, flags); in stm32_spi_transfer_one_dma()
1698 dev_info(spi->dev, "DMA issue: fall back to irq transfer\n"); in stm32_spi_transfer_one_dma()
1700 if (spi->sram_rx_buf) in stm32_spi_transfer_one_dma()
1701 memset(spi->sram_rx_buf, 0, spi->sram_rx_buf_size); in stm32_spi_transfer_one_dma()
1703 spi->cur_usedma = false; in stm32_spi_transfer_one_dma()
1704 return spi->cfg->transfer_one_irq(spi); in stm32_spi_transfer_one_dma()
1708 * stm32f4_spi_set_bpw - Configure bits per word
1713 if (spi->cur_bpw == 16) in stm32f4_spi_set_bpw()
1720 * stm32f7_spi_set_bpw - Configure bits per word
1728 bpw = spi->cur_bpw - 1; in stm32f7_spi_set_bpw()
1733 if (spi->rx_len >= sizeof(u16)) in stm32f7_spi_set_bpw()
1739 (readl_relaxed(spi->base + STM32FX_SPI_CR2) & in stm32f7_spi_set_bpw()
1741 spi->base + STM32FX_SPI_CR2); in stm32f7_spi_set_bpw()
1745 * stm32h7_spi_set_bpw - configure bits per word
1753 bpw = spi->cur_bpw - 1; in stm32h7_spi_set_bpw()
1758 spi->cur_fthlv = stm32h7_spi_prepare_fthlv(spi, spi->cur_xferlen); in stm32h7_spi_set_bpw()
1759 fthlv = spi->cur_fthlv - 1; in stm32h7_spi_set_bpw()
1765 (readl_relaxed(spi->base + STM32H7_SPI_CFG1) & in stm32h7_spi_set_bpw()
1767 spi->base + STM32H7_SPI_CFG1); in stm32h7_spi_set_bpw()
1771 * stm32_spi_set_mbr - Configure baud rate divisor in host mode
1779 clrb |= spi->cfg->regs->br.mask; in stm32_spi_set_mbr()
1780 setb |= (mbrdiv << spi->cfg->regs->br.shift) & spi->cfg->regs->br.mask; in stm32_spi_set_mbr()
1782 writel_relaxed((readl_relaxed(spi->base + spi->cfg->regs->br.reg) & in stm32_spi_set_mbr()
1784 spi->base + spi->cfg->regs->br.reg); in stm32_spi_set_mbr()
1788 * stm32_spi_communication_type - return transfer communication type
1797 if (spi_dev->mode & SPI_3WIRE) { /* MISO/MOSI signals shared */ in stm32_spi_communication_type()
1799 * SPI_3WIRE and xfer->tx_buf != NULL and xfer->rx_buf != NULL in stm32_spi_communication_type()
1804 if (!transfer->tx_buf) in stm32_spi_communication_type()
1809 if (!transfer->tx_buf) in stm32_spi_communication_type()
1811 else if (!transfer->rx_buf) in stm32_spi_communication_type()
1819 * stm32fx_spi_set_mode - configure communication mode
1840 return -EINVAL; in stm32fx_spi_set_mode()
1847 * stm32h7_spi_set_mode - configure communication mode
1874 (readl_relaxed(spi->base + STM32H7_SPI_CFG2) & in stm32h7_spi_set_mode()
1876 spi->base + STM32H7_SPI_CFG2); in stm32h7_spi_set_mode()
1882 * stm32h7_spi_data_idleness - configure minimum time delay inserted between two
1890 u32 len = xfer->len; in stm32h7_spi_data_idleness()
1893 spi_delay_ns = spi_delay_to_ns(&xfer->word_delay, xfer); in stm32h7_spi_data_idleness()
1895 if (spi->cur_midi != 0) { in stm32h7_spi_data_idleness()
1896 dev_warn(spi->dev, "st,spi-midi-ns DT property is deprecated\n"); in stm32h7_spi_data_idleness()
1898 dev_warn(spi->dev, "Overriding st,spi-midi-ns with word_delay_ns %d\n", in stm32h7_spi_data_idleness()
1900 spi->cur_midi = spi_delay_ns; in stm32h7_spi_data_idleness()
1903 spi->cur_midi = spi_delay_ns; in stm32h7_spi_data_idleness()
1907 if ((len > 1) && (spi->cur_midi > 0)) { in stm32h7_spi_data_idleness()
1908 u32 sck_period_ns = DIV_ROUND_UP(NSEC_PER_SEC, spi->cur_speed); in stm32h7_spi_data_idleness()
1910 DIV_ROUND_UP(spi->cur_midi, sck_period_ns), in stm32h7_spi_data_idleness()
1915 dev_dbg(spi->dev, "period=%dns, midi=%d(=%dns)\n", in stm32h7_spi_data_idleness()
1920 writel_relaxed((readl_relaxed(spi->base + STM32H7_SPI_CFG2) & in stm32h7_spi_data_idleness()
1922 spi->base + STM32H7_SPI_CFG2); in stm32h7_spi_data_idleness()
1926 * stm32h7_spi_number_of_data - configure number of data at current transfer
1932 if (nb_words <= spi->t_size_max) { in stm32h7_spi_number_of_data()
1934 spi->base + STM32H7_SPI_CR2); in stm32h7_spi_number_of_data()
1936 return -EMSGSIZE; in stm32h7_spi_number_of_data()
1943 * stm32_spi_transfer_one_setup - common setup to transfer a single
1959 spin_lock_irqsave(&spi->lock, flags); in stm32_spi_transfer_one_setup()
1961 spi->cur_xferlen = transfer->len; in stm32_spi_transfer_one_setup()
1963 spi->cur_bpw = transfer->bits_per_word; in stm32_spi_transfer_one_setup()
1964 spi->cfg->set_bpw(spi); in stm32_spi_transfer_one_setup()
1966 if (spi_dev->mode & SPI_READY && spi->cur_bpw < 8) { in stm32_spi_transfer_one_setup()
1967 writel_relaxed(readl_relaxed(spi->base + spi->cfg->regs->rdy_en.reg) & in stm32_spi_transfer_one_setup()
1968 ~spi->cfg->regs->rdy_en.mask, in stm32_spi_transfer_one_setup()
1969 spi->base + spi->cfg->regs->rdy_en.reg); in stm32_spi_transfer_one_setup()
1970 dev_dbg(spi->dev, "RDY logic disabled as bits per word < 8\n"); in stm32_spi_transfer_one_setup()
1973 /* Update spi->cur_speed with real clock speed */ in stm32_spi_transfer_one_setup()
1975 mbr = stm32_spi_prepare_mbr(spi, transfer->speed_hz, in stm32_spi_transfer_one_setup()
1976 spi->cfg->baud_rate_div_min, in stm32_spi_transfer_one_setup()
1977 spi->cfg->baud_rate_div_max); in stm32_spi_transfer_one_setup()
1983 transfer->speed_hz = spi->cur_speed; in stm32_spi_transfer_one_setup()
1988 ret = spi->cfg->set_mode(spi, comm_type); in stm32_spi_transfer_one_setup()
1992 spi->cur_comm = comm_type; in stm32_spi_transfer_one_setup()
1994 if (STM32_SPI_HOST_MODE(spi) && spi->cfg->set_data_idleness) in stm32_spi_transfer_one_setup()
1995 spi->cfg->set_data_idleness(spi, transfer); in stm32_spi_transfer_one_setup()
1997 if (spi->cur_bpw <= 8) in stm32_spi_transfer_one_setup()
1998 nb_words = transfer->len; in stm32_spi_transfer_one_setup()
1999 else if (spi->cur_bpw <= 16) in stm32_spi_transfer_one_setup()
2000 nb_words = DIV_ROUND_UP(transfer->len * 8, 16); in stm32_spi_transfer_one_setup()
2002 nb_words = DIV_ROUND_UP(transfer->len * 8, 32); in stm32_spi_transfer_one_setup()
2004 if (spi->cfg->set_number_of_data) { in stm32_spi_transfer_one_setup()
2005 ret = spi->cfg->set_number_of_data(spi, nb_words); in stm32_spi_transfer_one_setup()
2010 dev_dbg(spi->dev, "transfer communication mode set to %d\n", in stm32_spi_transfer_one_setup()
2011 spi->cur_comm); in stm32_spi_transfer_one_setup()
2012 dev_dbg(spi->dev, in stm32_spi_transfer_one_setup()
2013 "data frame of %d-bit, data packet of %d data frames\n", in stm32_spi_transfer_one_setup()
2014 spi->cur_bpw, spi->cur_fthlv); in stm32_spi_transfer_one_setup()
2016 dev_dbg(spi->dev, "speed set to %dHz\n", spi->cur_speed); in stm32_spi_transfer_one_setup()
2017 dev_dbg(spi->dev, "transfer of %d bytes (%d data frames)\n", in stm32_spi_transfer_one_setup()
2018 spi->cur_xferlen, nb_words); in stm32_spi_transfer_one_setup()
2019 dev_dbg(spi->dev, "dma %s\n", in stm32_spi_transfer_one_setup()
2020 (spi->cur_usedma) ? "enabled" : "disabled"); in stm32_spi_transfer_one_setup()
2023 spin_unlock_irqrestore(&spi->lock, flags); in stm32_spi_transfer_one_setup()
2029 * stm32_spi_transfer_one - transfer a single spi_transfer
2030 * @ctrl: controller interface
2037 static int stm32_spi_transfer_one(struct spi_controller *ctrl, in stm32_spi_transfer_one() argument
2041 struct stm32_spi *spi = spi_controller_get_devdata(ctrl); in stm32_spi_transfer_one()
2044 spi->tx_buf = transfer->tx_buf; in stm32_spi_transfer_one()
2045 spi->rx_buf = transfer->rx_buf; in stm32_spi_transfer_one()
2046 spi->tx_len = spi->tx_buf ? transfer->len : 0; in stm32_spi_transfer_one()
2047 spi->rx_len = spi->rx_buf ? transfer->len : 0; in stm32_spi_transfer_one()
2049 spi->cur_usedma = (ctrl->can_dma && in stm32_spi_transfer_one()
2050 ctrl->can_dma(ctrl, spi_dev, transfer)); in stm32_spi_transfer_one()
2054 dev_err(spi->dev, "SPI transfer setup failed\n"); in stm32_spi_transfer_one()
2058 if (spi->cur_usedma) in stm32_spi_transfer_one()
2061 return spi->cfg->transfer_one_irq(spi); in stm32_spi_transfer_one()
2065 * stm32_spi_unprepare_msg - relax the hardware
2066 * @ctrl: controller interface
2069 static int stm32_spi_unprepare_msg(struct spi_controller *ctrl, in stm32_spi_unprepare_msg() argument
2072 struct stm32_spi *spi = spi_controller_get_devdata(ctrl); in stm32_spi_unprepare_msg()
2074 spi->cfg->disable(spi); in stm32_spi_unprepare_msg()
2076 if (spi->sram_rx_buf) in stm32_spi_unprepare_msg()
2077 memset(spi->sram_rx_buf, 0, spi->sram_rx_buf_size); in stm32_spi_unprepare_msg()
2083 * stm32fx_spi_config - Configure SPI controller as SPI host
2090 spin_lock_irqsave(&spi->lock, flags); in stm32fx_spi_config()
2097 * - SS input value high in stm32fx_spi_config()
2098 * - transmitter half duplex direction in stm32fx_spi_config()
2099 * - Set the host mode (default Motorola mode) in stm32fx_spi_config()
2100 * - Consider 1 host/n targets configuration and in stm32fx_spi_config()
2108 spin_unlock_irqrestore(&spi->lock, flags); in stm32fx_spi_config()
2114 * stm32h7_spi_config - Configure SPI controller
2122 spin_lock_irqsave(&spi->lock, flags); in stm32h7_spi_config()
2133 * - Transmitter half duplex direction in stm32h7_spi_config()
2134 * - Automatic communication suspend when RX-Fifo is full in stm32h7_spi_config()
2135 * - SS input value high in stm32h7_spi_config()
2140 * - Set the host mode (default Motorola mode) in stm32h7_spi_config()
2141 * - Consider 1 host/n devices configuration and in stm32h7_spi_config()
2143 * - keep control of all associated GPIOs in stm32h7_spi_config()
2151 spin_unlock_irqrestore(&spi->lock, flags); in stm32h7_spi_config()
2227 * - enforce the DMA maxburst value to 1
2228 * - spi8 have limited feature set (TSIZE_MAX = 1024, BPW of 8 OR 16)
2256 { .compatible = "st,stm32mp25-spi", .data = (void *)&stm32mp25_spi_cfg },
2257 { .compatible = "st,stm32h7-spi", .data = (void *)&stm32h7_spi_cfg },
2258 { .compatible = "st,stm32f4-spi", .data = (void *)&stm32f4_spi_cfg },
2259 { .compatible = "st,stm32f7-spi", .data = (void *)&stm32f7_spi_cfg },
2264 static int stm32h7_spi_device_abort(struct spi_controller *ctrl) in stm32h7_spi_device_abort() argument
2266 spi_finalize_current_transfer(ctrl); in stm32h7_spi_device_abort()
2272 struct spi_controller *ctrl; in stm32_spi_probe() local
2275 struct reset_control *rst; in stm32_spi_probe() local
2276 struct device_node *np = pdev->dev.of_node; in stm32_spi_probe()
2281 cfg = of_device_get_match_data(&pdev->dev); in stm32_spi_probe()
2283 dev_err(&pdev->dev, "Failed to get match data for platform\n"); in stm32_spi_probe()
2284 return -ENODEV; in stm32_spi_probe()
2287 device_mode = of_property_read_bool(np, "spi-slave"); in stm32_spi_probe()
2288 if (!cfg->has_device_mode && device_mode) { in stm32_spi_probe()
2289 dev_err(&pdev->dev, "spi-slave not supported\n"); in stm32_spi_probe()
2290 return -EPERM; in stm32_spi_probe()
2294 ctrl = devm_spi_alloc_target(&pdev->dev, sizeof(struct stm32_spi)); in stm32_spi_probe()
2296 ctrl = devm_spi_alloc_host(&pdev->dev, sizeof(struct stm32_spi)); in stm32_spi_probe()
2297 if (!ctrl) { in stm32_spi_probe()
2298 dev_err(&pdev->dev, "spi controller allocation failed\n"); in stm32_spi_probe()
2299 return -ENOMEM; in stm32_spi_probe()
2301 platform_set_drvdata(pdev, ctrl); in stm32_spi_probe()
2303 spi = spi_controller_get_devdata(ctrl); in stm32_spi_probe()
2304 spi->dev = &pdev->dev; in stm32_spi_probe()
2305 spi->ctrl = ctrl; in stm32_spi_probe()
2306 spi->device_mode = device_mode; in stm32_spi_probe()
2307 spin_lock_init(&spi->lock); in stm32_spi_probe()
2309 spi->cfg = cfg; in stm32_spi_probe()
2311 spi->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); in stm32_spi_probe()
2312 if (IS_ERR(spi->base)) in stm32_spi_probe()
2313 return PTR_ERR(spi->base); in stm32_spi_probe()
2315 spi->phys_addr = (dma_addr_t)res->start; in stm32_spi_probe()
2317 spi->irq = platform_get_irq(pdev, 0); in stm32_spi_probe()
2318 if (spi->irq <= 0) in stm32_spi_probe()
2319 return spi->irq; in stm32_spi_probe()
2321 ret = devm_request_threaded_irq(&pdev->dev, spi->irq, in stm32_spi_probe()
2322 spi->cfg->irq_handler_event, in stm32_spi_probe()
2323 spi->cfg->irq_handler_thread, in stm32_spi_probe()
2324 IRQF_ONESHOT, pdev->name, ctrl); in stm32_spi_probe()
2326 dev_err(&pdev->dev, "irq%d request failed: %d\n", spi->irq, in stm32_spi_probe()
2331 spi->clk = devm_clk_get(&pdev->dev, NULL); in stm32_spi_probe()
2332 if (IS_ERR(spi->clk)) { in stm32_spi_probe()
2333 ret = PTR_ERR(spi->clk); in stm32_spi_probe()
2334 dev_err(&pdev->dev, "clk get failed: %d\n", ret); in stm32_spi_probe()
2338 ret = clk_prepare_enable(spi->clk); in stm32_spi_probe()
2340 dev_err(&pdev->dev, "clk enable failed: %d\n", ret); in stm32_spi_probe()
2343 spi->clk_rate = clk_get_rate(spi->clk); in stm32_spi_probe()
2344 if (!spi->clk_rate) { in stm32_spi_probe()
2345 dev_err(&pdev->dev, "clk rate = 0\n"); in stm32_spi_probe()
2346 ret = -EINVAL; in stm32_spi_probe()
2350 rst = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL); in stm32_spi_probe()
2351 if (rst) { in stm32_spi_probe()
2352 if (IS_ERR(rst)) { in stm32_spi_probe()
2353 ret = dev_err_probe(&pdev->dev, PTR_ERR(rst), in stm32_spi_probe()
2358 reset_control_assert(rst); in stm32_spi_probe()
2360 reset_control_deassert(rst); in stm32_spi_probe()
2363 if (spi->cfg->has_fifo) in stm32_spi_probe()
2364 spi->fifo_size = spi->cfg->get_fifo_size(spi); in stm32_spi_probe()
2366 spi->feature_set = STM32_SPI_FEATURE_FULL; in stm32_spi_probe()
2367 if (spi->cfg->regs->fullcfg.reg) { in stm32_spi_probe()
2368 spi->feature_set = in stm32_spi_probe()
2370 readl_relaxed(spi->base + spi->cfg->regs->fullcfg.reg)); in stm32_spi_probe()
2372 dev_dbg(spi->dev, "%s feature set\n", in stm32_spi_probe()
2373 spi->feature_set == STM32_SPI_FEATURE_FULL ? "full" : "limited"); in stm32_spi_probe()
2377 spi->t_size_max = spi->feature_set == STM32_SPI_FEATURE_FULL ? in stm32_spi_probe()
2380 dev_dbg(spi->dev, "one message max size %d\n", spi->t_size_max); in stm32_spi_probe()
2382 ret = spi->cfg->config(spi); in stm32_spi_probe()
2384 dev_err(&pdev->dev, "controller configuration failed: %d\n", in stm32_spi_probe()
2389 ctrl->dev.of_node = pdev->dev.of_node; in stm32_spi_probe()
2390 ctrl->auto_runtime_pm = true; in stm32_spi_probe()
2391 ctrl->bus_num = pdev->id; in stm32_spi_probe()
2392 ctrl->mode_bits = SPI_CPHA | SPI_CPOL | SPI_CS_HIGH | SPI_LSB_FIRST | in stm32_spi_probe()
2394 ctrl->bits_per_word_mask = spi->cfg->get_bpw_mask(spi); in stm32_spi_probe()
2395 ctrl->max_speed_hz = spi->clk_rate / spi->cfg->baud_rate_div_min; in stm32_spi_probe()
2396 ctrl->min_speed_hz = spi->clk_rate / spi->cfg->baud_rate_div_max; in stm32_spi_probe()
2397 ctrl->use_gpio_descriptors = true; in stm32_spi_probe()
2398 ctrl->optimize_message = stm32_spi_optimize_message; in stm32_spi_probe()
2399 ctrl->prepare_message = stm32_spi_prepare_msg; in stm32_spi_probe()
2400 ctrl->transfer_one = stm32_spi_transfer_one; in stm32_spi_probe()
2401 ctrl->unprepare_message = stm32_spi_unprepare_msg; in stm32_spi_probe()
2402 ctrl->flags = spi->cfg->flags; in stm32_spi_probe()
2404 ctrl->target_abort = stm32h7_spi_device_abort; in stm32_spi_probe()
2406 spi->dma_tx = dma_request_chan(spi->dev, "tx"); in stm32_spi_probe()
2407 if (IS_ERR(spi->dma_tx)) { in stm32_spi_probe()
2408 ret = PTR_ERR(spi->dma_tx); in stm32_spi_probe()
2409 spi->dma_tx = NULL; in stm32_spi_probe()
2410 if (ret == -EPROBE_DEFER) in stm32_spi_probe()
2413 dev_warn(&pdev->dev, "failed to request tx dma channel\n"); in stm32_spi_probe()
2415 ctrl->dma_tx = spi->dma_tx; in stm32_spi_probe()
2418 spi->dma_rx = dma_request_chan(spi->dev, "rx"); in stm32_spi_probe()
2419 if (IS_ERR(spi->dma_rx)) { in stm32_spi_probe()
2420 ret = PTR_ERR(spi->dma_rx); in stm32_spi_probe()
2421 spi->dma_rx = NULL; in stm32_spi_probe()
2422 if (ret == -EPROBE_DEFER) in stm32_spi_probe()
2425 dev_warn(&pdev->dev, "failed to request rx dma channel\n"); in stm32_spi_probe()
2427 ctrl->dma_rx = spi->dma_rx; in stm32_spi_probe()
2430 if (spi->dma_tx || spi->dma_rx) in stm32_spi_probe()
2431 ctrl->can_dma = stm32_spi_can_dma; in stm32_spi_probe()
2433 spi->sram_pool = of_gen_pool_get(pdev->dev.of_node, "sram", 0); in stm32_spi_probe()
2434 if (spi->sram_pool) { in stm32_spi_probe()
2435 spi->sram_rx_buf_size = gen_pool_size(spi->sram_pool); in stm32_spi_probe()
2436 dev_info(&pdev->dev, "SRAM pool: %zu KiB for RX DMA/MDMA chaining\n", in stm32_spi_probe()
2437 spi->sram_rx_buf_size / 1024); in stm32_spi_probe()
2438 spi->sram_rx_buf = gen_pool_dma_zalloc(spi->sram_pool, spi->sram_rx_buf_size, in stm32_spi_probe()
2439 &spi->sram_dma_rx_buf); in stm32_spi_probe()
2440 if (!spi->sram_rx_buf) { in stm32_spi_probe()
2441 dev_err(&pdev->dev, "failed to allocate SRAM buffer\n"); in stm32_spi_probe()
2443 spi->mdma_rx = dma_request_chan(spi->dev, "rxm2m"); in stm32_spi_probe()
2444 if (IS_ERR(spi->mdma_rx)) { in stm32_spi_probe()
2445 ret = PTR_ERR(spi->mdma_rx); in stm32_spi_probe()
2446 spi->mdma_rx = NULL; in stm32_spi_probe()
2447 if (ret == -EPROBE_DEFER) { in stm32_spi_probe()
2450 gen_pool_free(spi->sram_pool, in stm32_spi_probe()
2451 (unsigned long)spi->sram_rx_buf, in stm32_spi_probe()
2452 spi->sram_rx_buf_size); in stm32_spi_probe()
2453 dev_warn(&pdev->dev, in stm32_spi_probe()
2460 pm_runtime_set_autosuspend_delay(&pdev->dev, in stm32_spi_probe()
2462 pm_runtime_use_autosuspend(&pdev->dev); in stm32_spi_probe()
2463 pm_runtime_set_active(&pdev->dev); in stm32_spi_probe()
2464 pm_runtime_get_noresume(&pdev->dev); in stm32_spi_probe()
2465 pm_runtime_enable(&pdev->dev); in stm32_spi_probe()
2467 ret = spi_register_controller(ctrl); in stm32_spi_probe()
2469 dev_err(&pdev->dev, "spi controller registration failed: %d\n", in stm32_spi_probe()
2474 pm_runtime_put_autosuspend(&pdev->dev); in stm32_spi_probe()
2476 dev_info(&pdev->dev, "driver initialized (%s mode)\n", in stm32_spi_probe()
2482 pm_runtime_disable(&pdev->dev); in stm32_spi_probe()
2483 pm_runtime_put_noidle(&pdev->dev); in stm32_spi_probe()
2484 pm_runtime_set_suspended(&pdev->dev); in stm32_spi_probe()
2485 pm_runtime_dont_use_autosuspend(&pdev->dev); in stm32_spi_probe()
2487 if (spi->mdma_rx) in stm32_spi_probe()
2488 dma_release_channel(spi->mdma_rx); in stm32_spi_probe()
2490 if (spi->sram_pool) in stm32_spi_probe()
2491 gen_pool_free(spi->sram_pool, (unsigned long)spi->sram_rx_buf, in stm32_spi_probe()
2492 spi->sram_rx_buf_size); in stm32_spi_probe()
2494 if (spi->dma_tx) in stm32_spi_probe()
2495 dma_release_channel(spi->dma_tx); in stm32_spi_probe()
2496 if (spi->dma_rx) in stm32_spi_probe()
2497 dma_release_channel(spi->dma_rx); in stm32_spi_probe()
2499 clk_disable_unprepare(spi->clk); in stm32_spi_probe()
2506 struct spi_controller *ctrl = platform_get_drvdata(pdev); in stm32_spi_remove() local
2507 struct stm32_spi *spi = spi_controller_get_devdata(ctrl); in stm32_spi_remove()
2509 pm_runtime_get_sync(&pdev->dev); in stm32_spi_remove()
2511 spi_unregister_controller(ctrl); in stm32_spi_remove()
2512 spi->cfg->disable(spi); in stm32_spi_remove()
2514 pm_runtime_disable(&pdev->dev); in stm32_spi_remove()
2515 pm_runtime_put_noidle(&pdev->dev); in stm32_spi_remove()
2516 pm_runtime_set_suspended(&pdev->dev); in stm32_spi_remove()
2517 pm_runtime_dont_use_autosuspend(&pdev->dev); in stm32_spi_remove()
2519 if (ctrl->dma_tx) in stm32_spi_remove()
2520 dma_release_channel(ctrl->dma_tx); in stm32_spi_remove()
2521 if (ctrl->dma_rx) in stm32_spi_remove()
2522 dma_release_channel(ctrl->dma_rx); in stm32_spi_remove()
2523 if (spi->mdma_rx) in stm32_spi_remove()
2524 dma_release_channel(spi->mdma_rx); in stm32_spi_remove()
2525 if (spi->sram_rx_buf) in stm32_spi_remove()
2526 gen_pool_free(spi->sram_pool, (unsigned long)spi->sram_rx_buf, in stm32_spi_remove()
2527 spi->sram_rx_buf_size); in stm32_spi_remove()
2529 clk_disable_unprepare(spi->clk); in stm32_spi_remove()
2532 pinctrl_pm_select_sleep_state(&pdev->dev); in stm32_spi_remove()
2537 struct spi_controller *ctrl = dev_get_drvdata(dev); in stm32_spi_runtime_suspend() local
2538 struct stm32_spi *spi = spi_controller_get_devdata(ctrl); in stm32_spi_runtime_suspend()
2540 clk_disable_unprepare(spi->clk); in stm32_spi_runtime_suspend()
2547 struct spi_controller *ctrl = dev_get_drvdata(dev); in stm32_spi_runtime_resume() local
2548 struct stm32_spi *spi = spi_controller_get_devdata(ctrl); in stm32_spi_runtime_resume()
2555 return clk_prepare_enable(spi->clk); in stm32_spi_runtime_resume()
2560 struct spi_controller *ctrl = dev_get_drvdata(dev); in stm32_spi_suspend() local
2563 ret = spi_controller_suspend(ctrl); in stm32_spi_suspend()
2572 struct spi_controller *ctrl = dev_get_drvdata(dev); in stm32_spi_resume() local
2573 struct stm32_spi *spi = spi_controller_get_devdata(ctrl); in stm32_spi_resume()
2580 ret = spi_controller_resume(ctrl); in stm32_spi_resume()
2582 clk_disable_unprepare(spi->clk); in stm32_spi_resume()
2592 spi->cfg->config(spi); in stm32_spi_resume()