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/linux/Documentation/devicetree/bindings/serial/
H A Drs485.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/serial/rs485.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RS485 serial communications
9 description: The RTS signal is capable of automatically controlling line
10 direction for the built-in half-duplex mode. The properties described
11 hereafter shall be given to a half-duplex capable UART node.
14 - Rob Herring <robh@kernel.org>
17 rs485-rts-delay:
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/linux/Documentation/driver-api/serial/
H A Dserial-rs485.rst2 RS485 Serial Communications
8 EIA-485, also known as TIA/EIA-485 or RS-485, is a standard defining the
15 2. Hardware-related Considerations
18 Some CPUs/UARTs (e.g., Atmel AT91 or 16C950 UART) contain a built-in
19 half-duplex mode capable of automatically controlling line direction by
20 toggling RTS or DTR signals. That can be used to control external
21 half-duplex hardware like an RS485 transceiver or any RS232-connected
22 half-duplex devices like some modems.
26 available at user-level to allow switching from one mode to the other, and
32 The Linux kernel provides the struct serial_rs485 to handle RS485
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/linux/arch/arm/boot/dts/ti/omap/
H A Dam335x-nano.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013 Newflow Ltd - https://www.newflow.co.uk/
5 /dts-v1/;
15 cpu0-supply = <&dcdc2_reg>;
25 compatible = "gpio-leds";
30 default-state = "off";
36 pinctrl-names = "default";
37 pinctrl-0 = <&misc_pins>;
39 misc_pins: misc-pins {
40 pinctrl-single,pins = <
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H A Dam335x-pdu001.dts6 * Copyright (C) 2018 EETS GmbH - https://www.eets.ch/
8 * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/
10 * SPDX-License-Identifier: GPL-2.0+
13 /dts-v1/;
16 #include <dt-bindings/interrupt-controller/irq.h>
17 #include <dt-bindings/leds/leds-pca9532.h>
24 stdout-path = &uart3;
29 cpu0-supply = <&vdd1_reg>;
39 compatible = "regulator-fixed";
40 regulator-name = "vbat";
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/linux/arch/arm/boot/dts/microchip/
H A Daks-cdu.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * aks-cdu.dts - Device Tree file for AK signal CDU
9 /dts-v1/;
11 #include "ge863-pro3.dtsi"
20 clock-frequency = <32768>;
32 linux,rs485-enabled-at-boot-time;
33 rs485-rts-delay = <0 0>;
38 linux,rs485-enabled-at-boot-time;
39 rs485-rts-delay = <0 0>;
44 linux,rs485-enabled-at-boot-time;
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/linux/include/uapi/linux/
H A Dserial.h1 /* SPDX-License-Identifier: GPL-1.0+ WITH Linux-syscall-note */
64 #define PORT_RSA 13 /* RSA-DV II/S card */
83 * Multiport serial configuration structure --- external structure
100 * Serial input interrupt line counters -- external structure
112 * struct serial_rs485 - serial interface for controlling RS485 settings.
113 * @flags: RS485 feature flags.
114 * @delay_rts_before_send: Delay before send (milliseconds).
115 * @delay_rts_after_send: Delay after send (milliseconds).
116 * @addr_recv: Receive filter for RS485 addressing mode
118 * @addr_dest: Destination address for RS485 addressing mode
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/linux/drivers/tty/serial/8250/
H A D8250_lpc18xx.c1 // SPDX-License-Identifier: GPL-2.0
36 struct serial_rs485 *rs485) in lpc18xx_rs485_config() argument
43 if (rs485->flags & SER_RS485_ENABLED) { in lpc18xx_rs485_config()
47 if (rs485->flags & SER_RS485_RTS_ON_SEND) in lpc18xx_rs485_config()
51 if (rs485->delay_rts_after_send) { in lpc18xx_rs485_config()
52 baud_clk = port->uartclk / up->dl_read(up); in lpc18xx_rs485_config()
53 rs485_dly_reg = DIV_ROUND_UP(rs485->delay_rts_after_send in lpc18xx_rs485_config()
59 /* Calculate the resulting delay in ms */ in lpc18xx_rs485_config()
60 rs485->delay_rts_after_send = (rs485_dly_reg * MSEC_PER_SEC) in lpc18xx_rs485_config()
80 offset = offset << p->regshift; in lpc18xx_uart_serial_out()
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H A D8250_pci1xxxx.c1 // SPDX-License-Identifier: GPL-2.0
3 * Probe module for 8250/16550-type MCHP PCI serial ports.
162 /* Delay RTS before send is not supported */
167 writel(UART_SYSLOCK, port->membase + UART_SYSLOCK_REG); in pci1xxxx_set_sys_lock()
168 return readl(port->membase + UART_SYSLOCK_REG); in pci1xxxx_set_sys_lock()
183 writel(0x0, port->membase + UART_SYSLOCK_REG); in pci1xxxx_release_sys_lock()
189 {0, 1, 2, -1}, /* PCI3p012 */
190 {0, 1, 3, -1}, /* PCI3p013 */
191 {0, 2, 3, -1}, /* PCI3p023 */
192 {1, 2, 3, -1}, /* PCI3p123 */
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H A D8250_exar.c1 // SPDX-License-Identifier: GPL-2.0
3 * Probe module for 8250/16550-type Exar chips PCI serial ports.
11 #include <linux/delay.h>
114 #define UART_EXAR_TXTRG 0x0a /* Tx FIFO trigger level write-only */
115 #define UART_EXAR_RXTRG 0x0b /* Rx FIFO trigger level write-only */
133 #define UART_EXAR_DLD_485_POLARITY 0x80 /* RS-485 Enable Signal Polarity */
150 * ---- ---- --------
154 * 3 - <reserved>
158 * 7 - <reserved>
161 * 10 - Red LED
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/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mp-verdin-dev.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
7 native-hdmi-connector {
8 compatible = "hdmi-connector";
14 remote-endpoint = <&hdmi_tx_out>;
19 reg_eth2phy: regulator-eth2phy {
20 compatible = "regulator-fixed";
21 enable-active-high;
23 off-on-delay-us = <500000>;
24 regulator-max-microvolt = <3300000>;
25 regulator-min-microvolt = <3300000>;
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H A Dimx8mm-venice-gw7902.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/linux-event-codes.h>
10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/net/ti-dp83867.h>
12 #include <dt-bindings/phy/phy-imx8-pcie.h>
18 compatible = "gw,imx8mm-gw7902", "fsl,imx8mm";
29 stdout-path = &uart2;
38 compatible = "fixed-clock";
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H A Dimx8mm-venice-gw7901.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/linux-event-codes.h>
10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/phy/phy-imx8-pcie.h>
17 compatible = "gw,imx8mm-gw7901", "fsl,imx8mm";
32 stdout-path = &uart2;
40 gpio-keys {
41 compatible = "gpio-keys";
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H A Dimx8mn-venice-gw7902.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/linux-event-codes.h>
10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/net/ti-dp83867.h>
17 compatible = "gw,imx8mn-gw7902", "fsl,imx8mn";
26 stdout-path = &uart2;
35 compatible = "fixed-clock";
36 #clock-cells = <0>;
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H A Dimx8mp-skov-reva.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 #include "imx8mp-nominal.dtsi"
6 #include <dt-bindings/leds/common.h>
27 compatible = "pwm-backlight";
28 pinctrl-0 = <&pinctrl_backlight>;
30 power-supply = <&reg_24v>;
31 enable-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>;
32 brightness-levels = <0 255>;
33 num-interpolated-steps = <17>;
34 default-brightness-level = <8>;
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/linux/drivers/tty/serial/
H A Dimx.c1 // SPDX-License-Identifier: GPL-2.0+
23 #include <linux/delay.h>
31 #include <linux/dma-mapping.h>
34 #include <linux/dma/imx-dma.h>
75 #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
83 #define UCR2_IRTS (1<<14) /* Ignore RTS pin */
126 #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7)
129 #define USR1_RTSS (1<<14) /* RTS pin status */
131 #define USR1_RTSD (1<<12) /* RTS delta */
149 #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
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H A Domap-serial.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Driver for OMAP-UART controller.
16 * this driver as required for the omap-platform.
24 #include <linux/delay.h>
38 #include <linux/platform_data/serial-omap.h>
79 #define OMAP_UART_DMA_CH_FREE -1
176 offset <<= up->port.regshift; in serial_in()
177 return readw(up->port.membase + offset); in serial_in()
182 offset <<= up->port.regshift; in serial_out()
183 writew(value, up->port.membase + offset); in serial_out()
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H A Dsc16is7xx.c1 // SPDX-License-Identifier: GPL-2.0+
3 * SC16IS7xx tty serial driver - common code
15 #include <linux/delay.h>
53 * - only on 75x/76x
56 * - only on 75x/76x
59 * - only on 75x/76x
62 * - only on 75x/76x
90 /* IER register bits - write only if (EFR[4] == 1) */
103 /* FCR register bits - write only if (EFR[4] == 1) */
113 #define SC16IS7XX_IIR_RTOI_SRC 0x0c /* RX time-out interrupt */
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H A Dxilinx_uartps.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (c) 2011 - 2014 Xilinx, Inc.
7 * This driver has originally been pushed by Xilinx using a Zynq-branding. This
27 #include <linux/delay.h>
41 MODULE_PARM_DESC(rx_trigger_level, "Rx trigger level, 1-63 bytes");
46 MODULE_PARM_DESC(rx_timeout, "Rx timeout, 1-255");
63 #define CDNS_UART_FLOWDEL 0x38 /* Flow Delay */
89 #define CDNS_UART_MR_CLKSEL 0x00000001 /* Pre-scalar selection */
189 * struct cdns_uart - device data
199 * @rs485_tx_started: RS485 tx state
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H A Damba-pl011.c1 // SPDX-License-Identifier: GPL-2.0+
9 * Copyright (C) 2010 ST-Ericsson SA
11 * This is a generic driver for ARM AMBA-type serial ports. They
12 * have a lot of 16550-like features, but are not register compatible.
14 * not have an RI input, nor do they have DTR or RTS outputs. If
35 #include <linux/dma-mapping.h>
37 #include <linux/delay.h>
82 /* The size of the array - must be last */
268 unsigned int fifosize; /* vendor-specific */
269 unsigned int fixed_baud; /* vendor-set fixed baud rate */
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H A Datmel_serial.c1 // SPDX-License-Identifier: GPL-2.0+
18 #include <linux/clk-provider.h>
24 #include <linux/dma-mapping.h>
46 * These two offsets are substracted from the RX FIFO size to define the RTS
62 /* Use device name ttyAT, major 204 and minor 154-169. This is necessary if we
71 /* Use device name ttyS, major 4, minor 64-68. This is the usual serial port
167 bool hd_start_rx; /* can start RX during half-duplex operation */
197 { .compatible = "atmel,at91rm9200-usart-serial" },
210 return __raw_readl(port->membase + reg); in atmel_uart_readl()
215 __raw_writel(value, port->membase + reg); in atmel_uart_writel()
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H A Dar933x_uart.c1 // SPDX-License-Identifier: GPL-2.0
3 * Atheros AR933X SoC built-in UART driver
15 #include <linux/delay.h>
31 #include <asm/mach-ath79/ar933x_uart.h>
35 #define DRIVER_NAME "ar933x-uart"
60 return readl(up->port.membase + offset); in ar933x_uart_read()
66 writel(value, up->port.membase + offset); in ar933x_uart_write()
98 up->ier |= AR933X_UART_INT_TX_EMPTY; in ar933x_uart_start_tx_interrupt()
99 ar933x_uart_write(up, AR933X_UART_INT_EN_REG, up->ier); in ar933x_uart_start_tx_interrupt()
104 up->ier &= ~AR933X_UART_INT_TX_EMPTY; in ar933x_uart_stop_tx_interrupt()
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/linux/arch/x86/platform/ts5500/
H A Dts5500.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Technologic Systems TS-5500 Single Board Computer support
5 * Copyright (C) 2013-2014 Savoir-faire Linux Inc.
8 * This driver registers the Technologic Systems TS-5500 Single Board Computer
11 * Documentation/ABI/testing/sysfs-platform-ts5500.
13 * This code may be extended to support similar x86-based platforms.
14 * Actually, the TS-5500 and TS-5400 are supported.
17 #include <linux/delay.h>
28 #define TS5500_PRODUCT_CODE 0x60 /* TS-5500 product code */
29 #define TS5400_PRODUCT_CODE 0x40 /* TS-5400 product code */
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/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx7-mba7.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR X11
3 * Device Tree Include file for TQ-Systems MBa7 carrier board.
5 * Copyright (C) 2016 TQ-Systems GmbH
6 * Author: Markus Niebel <Markus.Niebel@tq-group.com>
13 #include <dt-bindings/input/input.h>
14 #include <dt-bindings/net/ti-dp83867.h>
20 /delete-property/ mmc2;
26 compatible = "gpio-beeper";
31 stdout-path = &uart6;
34 gpio_buttons: gpio-keys {
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H A Dimx6dl-plybas.dts1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
7 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/leds/common.h>
17 stdout-path = &uart4;
21 compatible = "gpio-keys";
24 button-start {
30 button-clean {
38 compatible = "gpio-leds";
39 pinctrl-names = "default";
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/linux/arch/arm64/boot/dts/ti/
H A Dk3-am62p-verdin-ivy.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
7 * https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62p
8 * https://www.toradex.com/products/carrier-board/ivy-carrier-board
11 #include <dt-bindings/mux/mux.h>
12 #include <dt-bindings/leds/common.h>
13 #include <dt-bindings/net/ti-dp83867.h>
21 ain1_voltage_unmanaged: voltage-divider-ain1 {
22 compatible = "voltage-divider";
23 #io-channel-cells = <1>;
24 io-channels = <&ivy_adc1 0>;
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