Lines Matching +full:rs485 +full:- +full:rts +full:- +full:delay
1 // SPDX-License-Identifier: GPL-2.0
3 * Probe module for 8250/16550-type MCHP PCI serial ports.
162 /* Delay RTS before send is not supported */
167 writel(UART_SYSLOCK, port->membase + UART_SYSLOCK_REG); in pci1xxxx_set_sys_lock()
168 return readl(port->membase + UART_SYSLOCK_REG); in pci1xxxx_set_sys_lock()
183 writel(0x0, port->membase + UART_SYSLOCK_REG); in pci1xxxx_release_sys_lock()
189 {0, 1, 2, -1}, /* PCI3p012 */
190 {0, 1, 3, -1}, /* PCI3p013 */
191 {0, 2, 3, -1}, /* PCI3p023 */
192 {1, 2, 3, -1}, /* PCI3p123 */
193 {0, 1, -1, -1}, /* PCI2p01 */
194 {0, 2, -1, -1}, /* PCI2p02 */
195 {0, 3, -1, -1}, /* PCI2p03 */
196 {1, 2, -1, -1}, /* PCI2p12 */
197 {1, 3, -1, -1}, /* PCI2p13 */
198 {2, 3, -1, -1}, /* PCI2p23 */
199 {0, -1, -1, -1}, /* PCI1p0 */
200 {1, -1, -1, -1}, /* PCI1p1 */
201 {2, -1, -1, -1}, /* PCI1p2 */
202 {3, -1, -1, -1}, /* PCI1p3 */
207 switch (dev->subsystem_device) { in pci1xxxx_get_num_ports()
252 *frac = (NSEC_PER_SEC - quot * baud * uart_sample_cnt) * in pci1xxxx_get_divisor()
262 writel(UART_BIT_DIVISOR_8, port->membase + FRAC_DIV_CFG_REG); in pci1xxxx_set_divisor()
264 writel(UART_BIT_DIVISOR_16, port->membase + FRAC_DIV_CFG_REG); in pci1xxxx_set_divisor()
267 port->membase + UART_BAUD_CLK_DIVISOR_REG); in pci1xxxx_set_divisor()
277 adcl_cfg_reg = readl(port->membase + ADCL_CFG_REG); in pci1xxxx_set_mctrl()
283 modem_ctl_reg = readl(port->membase + UART_MODEM_CTL_REG); in pci1xxxx_set_mctrl()
288 line_stat_reg = readl(port->membase + UART_LINE_STAT_REG); in pci1xxxx_set_mctrl()
290 fract_div_cfg_reg = readl(port->membase + in pci1xxxx_set_mctrl()
295 port->membase + FRAC_DIV_CFG_REG); in pci1xxxx_set_mctrl()
300 port->membase + ADCL_CFG_REG); in pci1xxxx_set_mctrl()
303 writel(adcl_cfg_reg, port->membase + ADCL_CFG_REG); in pci1xxxx_set_mctrl()
305 writel(fract_div_cfg_reg, port->membase + in pci1xxxx_set_mctrl()
313 struct serial_rs485 *rs485) in pci1xxxx_rs485_config() argument
322 frac_div = readl(port->membase + FRAC_DIV_CFG_REG); in pci1xxxx_rs485_config()
330 * pci1xxxx's uart hardware supports only RTS delay after in pci1xxxx_rs485_config()
333 if (rs485->flags & SER_RS485_ENABLED) { in pci1xxxx_rs485_config()
336 if (!(rs485->flags & SER_RS485_RTS_ON_SEND)) in pci1xxxx_rs485_config()
339 if (rs485->delay_rts_after_send) { in pci1xxxx_rs485_config()
340 clock_div = readl(port->membase + UART_BAUD_CLK_DIVISOR_REG); in pci1xxxx_rs485_config()
345 rs485->delay_rts_after_send * NSEC_PER_MSEC / in pci1xxxx_rs485_config()
352 rs485->delay_rts_after_send = in pci1xxxx_rs485_config()
357 writel(mode_cfg, port->membase + ADCL_CFG_REG); in pci1xxxx_rs485_config()
365 status = readl(port->membase + UART_BURST_STATUS_REG); in pci1xxxx_read_burst_status()
369 port->membase + UART_FIFO_CTL); in pci1xxxx_read_burst_status()
370 port->icount.overrun++; in pci1xxxx_read_burst_status()
374 port->icount.frame++; in pci1xxxx_read_burst_status()
377 port->icount.parity++; in pci1xxxx_read_burst_status()
395 while (valid_burst_count--) { in pci1xxxx_process_read_data()
396 if (*buff_index > (RX_BUF_SIZE - UART_BURST_SIZE)) in pci1xxxx_process_read_data()
399 *burst_buf = readl(port->membase + UART_RX_BURST_FIFO); in pci1xxxx_process_read_data()
401 *valid_byte_count -= UART_BURST_SIZE; in pci1xxxx_process_read_data()
407 rx_buff[*buff_index] = readb(port->membase + in pci1xxxx_process_read_data()
410 *valid_byte_count -= UART_BYTE_SIZE; in pci1xxxx_process_read_data()
417 struct tty_port *tty_port = &port->state->port; in pci1xxxx_rx_burst()
431 port->icount.overrun += buff_index - copied_len; in pci1xxxx_rx_burst()
433 port->icount.rx += buff_index; in pci1xxxx_rx_burst()
442 struct tty_port *tport = &port->state->port; in pci1xxxx_process_write_data()
454 if (*data_empty_count - UART_BURST_SIZE < 0) in pci1xxxx_process_write_data()
456 if (kfifo_len(&tport->xmit_fifo) < UART_BURST_SIZE) in pci1xxxx_process_write_data()
458 if (WARN_ON(kfifo_out(&tport->xmit_fifo, (u8 *)&c, sizeof(c)) != in pci1xxxx_process_write_data()
461 writel(c, port->membase + UART_TX_BURST_FIFO); in pci1xxxx_process_write_data()
462 *valid_byte_count -= UART_BURST_SIZE; in pci1xxxx_process_write_data()
463 *data_empty_count -= UART_BURST_SIZE; in pci1xxxx_process_write_data()
464 valid_burst_count -= UART_BYTE_SIZE; in pci1xxxx_process_write_data()
470 if (!kfifo_get(&tport->xmit_fifo, &c)) in pci1xxxx_process_write_data()
472 writeb(c, port->membase + UART_TX_BYTE_FIFO); in pci1xxxx_process_write_data()
473 *data_empty_count -= UART_BYTE_SIZE; in pci1xxxx_process_write_data()
474 *valid_byte_count -= UART_BYTE_SIZE; in pci1xxxx_process_write_data()
481 kfifo_len(&tport->xmit_fifo) >= UART_BURST_SIZE) in pci1xxxx_process_write_data()
489 struct tty_port *tport = &port->state->port; in pci1xxxx_tx_burst()
493 if (port->x_char) { in pci1xxxx_tx_burst()
494 writeb(port->x_char, port->membase + UART_TX); in pci1xxxx_tx_burst()
495 port->icount.tx++; in pci1xxxx_tx_burst()
496 port->x_char = 0; in pci1xxxx_tx_burst()
500 if ((uart_tx_stopped(port)) || kfifo_is_empty(&tport->xmit_fifo)) { in pci1xxxx_tx_burst()
501 port->ops->stop_tx(port); in pci1xxxx_tx_burst()
506 valid_byte_count = kfifo_len(&tport->xmit_fifo); in pci1xxxx_tx_burst()
512 port->icount.tx++; in pci1xxxx_tx_burst()
513 if (kfifo_is_empty(&tport->xmit_fifo)) in pci1xxxx_tx_burst()
518 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) in pci1xxxx_tx_burst()
526 if (kfifo_is_empty(&tport->xmit_fifo) && in pci1xxxx_tx_burst()
527 !(up->capabilities & UART_CAP_RPM)) in pci1xxxx_tx_burst()
528 port->ops->stop_tx(port); in pci1xxxx_tx_burst()
541 spin_lock_irqsave(&port->lock, flags); in pci1xxxx_handle_irq()
549 spin_unlock_irqrestore(&port->lock, flags); in pci1xxxx_handle_irq()
557 struct uart_port *port = &up->port; in pci1xxxx_port_suspend()
558 struct tty_port *tport = &port->state->port; in pci1xxxx_port_suspend()
563 mutex_lock(&tport->mutex); in pci1xxxx_port_suspend()
564 if (port->suspended == 0 && port->dev) { in pci1xxxx_port_suspend()
565 wakeup_mask = readb(up->port.membase + UART_WAKE_MASK_REG); in pci1xxxx_port_suspend()
568 port->mctrl &= ~TIOCM_OUT2; in pci1xxxx_port_suspend()
569 port->ops->set_mctrl(port, port->mctrl); in pci1xxxx_port_suspend()
575 writeb(UART_WAKE_SRCS, port->membase + UART_WAKE_REG); in pci1xxxx_port_suspend()
576 mutex_unlock(&tport->mutex); in pci1xxxx_port_suspend()
584 struct uart_port *port = &up->port; in pci1xxxx_port_resume()
585 struct tty_port *tport = &port->state->port; in pci1xxxx_port_resume()
588 mutex_lock(&tport->mutex); in pci1xxxx_port_resume()
589 writeb(UART_BLOCK_SET_ACTIVE, port->membase + UART_ACTV_REG); in pci1xxxx_port_resume()
590 writeb(UART_WAKE_SRCS, port->membase + UART_WAKE_REG); in pci1xxxx_port_resume()
592 if (port->suspended == 0) { in pci1xxxx_port_resume()
594 port->mctrl |= TIOCM_OUT2; in pci1xxxx_port_resume()
595 port->ops->set_mctrl(port, port->mctrl); in pci1xxxx_port_resume()
598 mutex_unlock(&tport->mutex); in pci1xxxx_port_resume()
610 for (i = 0; i < priv->nr; i++) { in pci1xxxx_suspend()
611 if (priv->line[i] >= 0) { in pci1xxxx_suspend()
612 serial8250_suspend_port(priv->line[i]); in pci1xxxx_suspend()
613 wakeup |= pci1xxxx_port_suspend(priv->line[i]); in pci1xxxx_suspend()
620 return -ENOMEM; in pci1xxxx_suspend()
625 if (priv->dev_rev >= 0xC0) in pci1xxxx_suspend()
651 return -ENOMEM; in pci1xxxx_resume()
656 if (priv->dev_rev >= 0xC0) in pci1xxxx_resume()
663 for (i = 0; i < priv->nr; i++) { in pci1xxxx_resume()
664 if (priv->line[i] >= 0) { in pci1xxxx_resume()
665 pci1xxxx_port_resume(priv->line[i]); in pci1xxxx_resume()
666 serial8250_resume_port(priv->line[i]); in pci1xxxx_resume()
678 port->port.flags |= UPF_FIXED_TYPE | UPF_SKIP_TEST; in pci1xxxx_setup()
679 port->port.type = PORT_MCHP16550A; in pci1xxxx_setup()
690 port->port.uartclk = 64 * HZ_PER_MHZ; in pci1xxxx_setup()
691 port->port.set_termios = serial8250_do_set_termios; in pci1xxxx_setup()
692 port->port.get_divisor = pci1xxxx_get_divisor; in pci1xxxx_setup()
693 port->port.set_divisor = pci1xxxx_set_divisor; in pci1xxxx_setup()
694 port->port.rs485_config = pci1xxxx_rs485_config; in pci1xxxx_setup()
695 port->port.rs485_supported = pci1xxxx_rs485_supported; in pci1xxxx_setup()
699 * RTS workaround in mctrl is applicable only to B0. in pci1xxxx_setup()
702 port->port.handle_irq = pci1xxxx_handle_irq; in pci1xxxx_setup()
704 port->port.set_mctrl = pci1xxxx_set_mctrl; in pci1xxxx_setup()
710 writeb(UART_BLOCK_SET_ACTIVE, port->port.membase + UART_ACTV_REG); in pci1xxxx_setup()
711 writeb(UART_WAKE_SRCS, port->port.membase + UART_WAKE_REG); in pci1xxxx_setup()
712 writeb(UART_WAKE_N_PIN, port->port.membase + UART_WAKE_MASK_REG); in pci1xxxx_setup()
722 while (i--) { in pci1xxxx_get_max_port()
723 if (logical_to_physical_port_idx[subsys_dev][i] != -1) in pci1xxxx_get_max_port()
754 regval = readl(priv->membase + UART_DEV_REV_REG); in pci1xxxx_get_device_revision()
755 priv->dev_rev = regval & UART_DEV_REV_MASK; in pci1xxxx_get_device_revision()
765 struct device *dev = &pdev->dev; in pci1xxxx_serial_probe()
784 return -ENOMEM; in pci1xxxx_serial_probe()
786 priv->membase = pci_ioremap_bar(pdev, 0); in pci1xxxx_serial_probe()
787 if (!priv->membase) in pci1xxxx_serial_probe()
788 return -ENOMEM; in pci1xxxx_serial_probe()
796 priv->nr = nr_ports; in pci1xxxx_serial_probe()
798 subsys_dev = pdev->subsystem_device; in pci1xxxx_serial_probe()
803 pci_iounmap(pdev, priv->membase); in pci1xxxx_serial_probe()
812 writeb(UART_PCI_CTRL_SET_MULTIPLE_MSI, priv->membase + UART_PCI_CTRL_REG); in pci1xxxx_serial_probe()
815 priv->line[i] = -ENODEV; in pci1xxxx_serial_probe()
824 rc = pci1xxxx_setup(pdev, &uart, port_idx, priv->dev_rev); in pci1xxxx_serial_probe()
830 priv->line[i] = serial8250_register_8250_port(&uart); in pci1xxxx_serial_probe()
831 if (priv->line[i] < 0) { in pci1xxxx_serial_probe()
835 priv->line[i]); in pci1xxxx_serial_probe()
849 for (i = 0; i < priv->nr; i++) { in pci1xxxx_serial_remove()
850 if (priv->line[i] >= 0) in pci1xxxx_serial_remove()
851 serial8250_unregister_port(priv->line[i]); in pci1xxxx_serial_remove()
855 pci_iounmap(dev, priv->membase); in pci1xxxx_serial_remove()