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/linux/Documentation/devicetree/bindings/serial/
H A Drs485.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/serial/rs485.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RS485 serial communications
9 description: The RTS signal is capable of automatically controlling line
10 direction for the built-in half-duplex mode. The properties described
11 hereafter shall be given to a half-duplex capable UART node.
14 - Rob Herring <robh@kernel.org>
17 rs485-rts-delay:
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/linux/arch/arm/boot/dts/ti/omap/
H A Dam335x-nano.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013 Newflow Ltd - https://www.newflow.co.uk/
5 /dts-v1/;
15 cpu0-supply = <&dcdc2_reg>;
25 compatible = "gpio-leds";
30 default-state = "off";
36 pinctrl-names = "default";
37 pinctrl-0 = <&misc_pins>;
39 misc_pins: misc-pins {
40 pinctrl-single,pins = <
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H A Dam335x-regor.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/pinctrl/am33xx.h>
12 model = "Phytec AM335x phyBOARD-REGOR";
13 compatible = "phytec,am335x-regor", "phytec,am335x-phycore-som", "ti,am33xx";
16 compatible = "regulator-fixed";
17 regulator-name = "vcc3v3";
18 regulator-min-microvolt = <3300000>;
19 regulator-max-microvolt = <3300000>;
20 regulator-boot-on;
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H A Dam335x-pdu001.dts6 * Copyright (C) 2018 EETS GmbH - https://www.eets.ch/
8 * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/
10 * SPDX-License-Identifier: GPL-2.0+
13 /dts-v1/;
16 #include <dt-bindings/interrupt-controller/irq.h>
17 #include <dt-bindings/leds/leds-pca9532.h>
24 stdout-path = &uart3;
29 cpu0-supply = <&vdd1_reg>;
39 compatible = "regulator-fixed";
40 regulator-name = "vbat";
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/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mm-venice-gw72xx-0x-rs485.dtso1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * GW72xx RS485 HD:
6 * - GPIO1_0 rs485_term selects on-chip termination
7 * - GPIO4_0 rs485_en needs to be driven high (active)
8 * - GPIO4_2 rs485_hd needs to be driven high (active)
9 * - UART4_TX is DE for RS485 transmitter
10 * - RS485_EN needs to be pulled high
11 * - RS485_HALF needs to be pulled high
14 #include <dt-bindings/gpio/gpio.h>
16 #include "imx8mm-pinfunc.h"
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H A Dimx8mm-venice-gw73xx-0x-rs485.dtso1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * GW73xx RS485 HD:
6 * - GPIO1_0 rs485_term selects on-chip termination
7 * - GPIO4_0 rs485_en needs to be driven high (active)
8 * - GPIO4_2 rs485_hd needs to be driven high (active)
9 * - UART4_TX is DE for RS485 transmitter
10 * - RS485_EN needs to be pulled high
11 * - RS485_HALF needs to be pulled high
14 #include <dt-bindings/gpio/gpio.h>
16 #include "imx8mm-pinfunc.h"
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H A Dimx8mm-venice-gw72xx-0x-rs422.dtso1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * GW72xx RS422 (RS485 full duplex):
6 * - GPIO1_0 rs485_term selects on-chip termination
7 * - GPIO4_0 rs485_en needs to be driven high (active)
8 * - GPIO4_2 rs485_hd needs to be driven low (in-active)
9 * - UART4_TX is DE for RS485 transmitter
10 * - RS485_EN needs to be pulled high
11 * - RS485_HALF needs to be low
14 #include <dt-bindings/gpio/gpio.h>
16 #include "imx8mm-pinfunc.h"
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H A Dimx8mm-venice-gw73xx-0x-rs422.dtso1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * GW73xx RS422 (RS485 full duplex):
6 * - GPIO1_0 rs485_term selects on-chip termination
7 * - GPIO4_0 rs485_en needs to be driven high (active)
8 * - GPIO4_2 rs485_hd needs to be driven low (in-active)
9 * - UART4_TX is DE for RS485 transmitter
10 * - RS485_EN needs to be pulled high
11 * - RS485_HALF needs to be low
14 #include <dt-bindings/gpio/gpio.h>
16 #include "imx8mm-pinfunc.h"
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H A Dimx8mm-phygate-tauri-l-rs232-rs485.dtso1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 * Tauri-L RS232 + RS485:
7 * - GPIO3_20 uart4_rs485_en needs to be driven high (active)
8 * - GPIO3_25 RS485_DE Driver enable
11 #include <dt-bindings/clock/imx8mm-clock.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include "imx8mm-pinfunc.h"
15 /dts-v1/;
19 pinctrl-names = "default";
20 pinctrl-0 = <&pinctrl_gpio3_hog>;
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H A Dimx8mp-verdin-dev.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
7 native-hdmi-connector {
8 compatible = "hdmi-connector";
14 remote-endpoint = <&hdmi_tx_out>;
19 reg_eth2phy: regulator-eth2phy {
20 compatible = "regulator-fixed";
21 enable-active-high;
23 off-on-delay-us = <500000>;
24 regulator-max-microvolt = <3300000>;
25 regulator-min-microvolt = <3300000>;
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H A Dimx8mm-venice-gw7901.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/linux-event-codes.h>
10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/phy/phy-imx8-pcie.h>
17 compatible = "gw,imx8mm-gw7901", "fsl,imx8mm";
32 stdout-path = &uart2;
40 gpio-keys {
41 compatible = "gpio-keys";
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H A Dimx8mm-mx8menlo.dts1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 * Copyright 2021-2022 Marek Vasut <marex@denx.de>
6 /dts-v1/;
8 #include "imx8mm-verdin.dtsi"
13 "toradex,verdin-imx8mm-nonwifi",
14 "toradex,verdin-imx8mm",
17 /delete-node/ gpio-keys;
20 compatible = "gpio-leds";
21 pinctrl-names = "default";
22 pinctrl-0 = <&pinctrl_led>;
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H A Dimx8mm-venice-gw73xx.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/leds/common.h>
8 #include <dt-bindings/phy/phy-imx8-pcie.h>
17 led-controller {
18 compatible = "gpio-leds";
19 pinctrl-names = "default";
20 pinctrl-0 = <&pinctrl_gpio_leds>;
22 led-0 {
26 default-state = "on";
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H A Dimx8mm-venice-gw7902.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/linux-event-codes.h>
10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/net/ti-dp83867.h>
12 #include <dt-bindings/phy/phy-imx8-pcie.h>
18 compatible = "gw,imx8mm-gw7902", "fsl,imx8mm";
29 stdout-path = &uart2;
38 compatible = "fixed-clock";
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/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx7-mba7.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR X11
3 * Device Tree Include file for TQ-Systems MBa7 carrier board.
5 * Copyright (C) 2016 TQ-Systems GmbH
6 * Author: Markus Niebel <Markus.Niebel@tq-group.com>
13 #include <dt-bindings/input/input.h>
14 #include <dt-bindings/net/ti-dp83867.h>
20 /delete-property/ mmc2;
26 compatible = "gpio-beeper";
31 stdout-path = &uart6;
34 gpio_buttons: gpio-keys {
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H A Dimx6qdl-mba6.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright 2013-2021 TQ-Systems GmbH
6 * Author: Markus Niebel <Markus.Niebel@tq-group.com>
9 #include <dt-bindings/clock/imx6qdl-clock.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/sound/fsl-imx-audmux.h>
18 /delete-property/ mmc2;
19 /delete-property/ mmc3;
24 stdout-path = &uart2;
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H A Dimx6dl-plybas.dts1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
7 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/leds/common.h>
17 stdout-path = &uart4;
21 compatible = "gpio-keys";
24 button-start {
30 button-clean {
38 compatible = "gpio-leds";
39 pinctrl-names = "default";
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H A Dimx6ul-kontron-bl-common.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/gpio/gpio.h>
11 gpio-leds {
12 compatible = "gpio-leds";
13 pinctrl-names = "default";
14 pinctrl-0 = <&pinctrl_gpio_leds>;
17 label = "debug-led1";
19 default-state = "off";
20 linux,default-trigger = "heartbeat";
24 label = "debug-led2";
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/linux/drivers/usb/serial/
H A Dxr_serial.c1 // SPDX-License-Identifier: GPL-2.0+
10 * https://lore.kernel.org/r/20180404070634.nhspvmxcjwfgjkcv@advantechmxl-desktop
240 u8 channel; /* zero-based index or interface number */
241 struct serial_rs485 rs485; member
247 const struct xr_type *type = data->type; in xr_set_reg()
248 struct usb_serial *serial = port->serial; in xr_set_reg()
251 ret = usb_control_msg(serial->dev, usb_sndctrlpipe(serial->dev, 0), in xr_set_reg()
252 type->set_reg, in xr_set_reg()
253 USB_DIR_OUT | USB_TYPE_VENDOR | type->reg_recipient, in xr_set_reg()
257 dev_err(&port->dev, "Failed to set reg 0x%02x: %d\n", reg, ret); in xr_set_reg()
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/linux/drivers/tty/serial/
H A Dimx.c1 // SPDX-License-Identifier: GPL-2.0+
31 #include <linux/dma-mapping.h>
34 #include <linux/dma/imx-dma.h>
75 #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
83 #define UCR2_IRTS (1<<14) /* Ignore RTS pin */
126 #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7)
129 #define USR1_RTSS (1<<14) /* RTS pin status */
131 #define USR1_RTSD (1<<12) /* RTS delta */
149 #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
162 /* We've been assigned a range on the "Low-density serial ports" major */
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H A Domap-serial.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Driver for OMAP-UART controller.
16 * this driver as required for the omap-platform.
38 #include <linux/platform_data/serial-omap.h>
79 #define OMAP_UART_DMA_CH_FREE -1
176 offset <<= up->port.regshift; in serial_in()
177 return readw(up->port.membase + offset); in serial_in()
182 offset <<= up->port.regshift; in serial_out()
183 writew(value, up->port.membase + offset); in serial_out()
197 struct omap_uart_port_info *pdata = dev_get_platdata(up->dev); in serial_omap_get_context_loss_count()
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H A Dqcom_geni_serial.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2017-2018, The Linux foundation. All rights reserved.
21 #include <linux/soc/qcom/geni-se.h>
27 #include <dt-bindings/interconnect/qcom,icc.h>
175 * qcom_geni_set_rs485_mode - Set RTS pin state for RS485 mode
177 * @flag: RS485 flag to determine RTS polarity
179 * Enables manual RTS control for RS485. Sets RTS to READY or NOT_READY
180 * based on the specified flag if RS485 mode is enabled.
184 if (!(uport->rs485.flags & SER_RS485_ENABLED)) in qcom_geni_set_rs485_mode()
189 if (uport->rs485.flags & flag) in qcom_geni_set_rs485_mode()
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H A Datmel_serial.c1 // SPDX-License-Identifier: GPL-2.0+
18 #include <linux/clk-provider.h>
24 #include <linux/dma-mapping.h>
46 * These two offsets are substracted from the RX FIFO size to define the RTS
47 * high and low thresholds
62 /* Use device name ttyAT, major 204 and minor 154-169. This is necessary if we
71 /* Use device name ttyS, major 4, minor 64-68. This is the usual serial port
167 bool hd_start_rx; /* can start RX during half-duplex operation */
197 { .compatible = "atmel,at91rm9200-usart-serial" },
210 return __raw_readl(port->membase + reg); in atmel_uart_readl()
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H A Dsc16is7xx.c1 // SPDX-License-Identifier: GPL-2.0+
3 * SC16IS7xx tty serial driver - common code
53 * - only on 75x/76x
56 * - only on 75x/76x
59 * - only on 75x/76x
62 * - only on 75x/76x
72 #define SC16IS7XX_DLH_REG (0x01) /* Divisor Latch High */
90 /* IER register bits - write only if (EFR[4] == 1) */
103 /* FCR register bits - write only if (EFR[4] == 1) */
113 #define SC16IS7XX_IIR_RTOI_SRC 0x0c /* RX time-out interrupt */
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H A Dxilinx_uartps.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (c) 2011 - 2014 Xilinx, Inc.
7 * This driver has originally been pushed by Xilinx using a Zynq-branding. This
41 MODULE_PARM_DESC(rx_trigger_level, "Rx trigger level, 1-63 bytes");
46 MODULE_PARM_DESC(rx_timeout, "Rx timeout, 1-255");
89 #define CDNS_UART_MR_CLKSEL 0x00000001 /* Pre-scalar selection */
180 #define CDNS_UART_SR_TACTIVE 0x00000800 /* TX state machine active */
189 * struct cdns_uart - device data
199 * @rs485_tx_started: RS485 tx state
232 * cdns_uart_handle_rx - Handle the received bytes along with Rx errors.
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